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The UART interface is used for communication between the host and PAN1322-SPP. The lines UARTTXD and
UARTRXD are used for commands, events and data. The lines UARTRTS and UARTCTS are used for hardware
flow control.
Low power mode control of PAN1322-SPP and the host can be implemented in by using the pins P0.14 and P0.0.
P0.14 is used by the host to allow PAN1322-SPP to enter low power mode and P0.0 is used by PAN1322-SPP to
wake-up the host when attention is required. Additionally, the host could hardware reset PAN1322-SPP using the
RESET# pin.
Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages.
The UART and the GPIO's interfaces have separate supply voltages so that they can comply with host signaling.
1.6
SW Patch in EEPROM
Bug fixes for the SW in ROM are downloaded from the EEPROM. Panasonic may include new bug fixes in
EEPROM during product lifetime.
1.7
FW Version
PAN1322-SPP is available in different firmware (FW) versions. Please check corresponding release documents
for latest information in item [2].
The identifier about the software version will be visible on the module, please refer to
identifier SW (Software). For example SW01 match with FW3.1.
User's Manual
Hardware Description
14
PAN1322-SPP
ENW89841A3KF
General Device Overview
Figure
6, here it is the
Revision 1.3, 2013-08-14
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