Pin Description; Table 1 Pin Description - Panasonic PAN1322-SPP User Manual

1.4

Pin Description

The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might
be removed/changed in future variants. Pins not listed below shall not be connected.
Table 1 Pin Description
Pin Symbol
No.
A2 P1.6
A3 RESET#
A8 P1.5
B1 P1.7
B2 P1.8
B3 P1.0 /
TMS
B4 P1.4 /
RTCK
B5 ONOFF
B9 SLEEPX
C2 P0.9
C3 JTAG#
C4 TRST#
D1 P0.10
D2 P0.8
D3 P1.1 /
TCK
D4 P0.3
D5 P0.2
E1 P0.12 / SDA0
E2 P0.13 / SCL0
E3 P1.3 /
TDO
E4 P0.0
E5 P0.1
E6 P0.5 /
UARTRXD
F2 P1.2 /
TDI
F3 P0.11
User's Manual
Hardware Description
Input / Supply Voltage During
Output
I/O/OD Internal1
AI Internal1
I/O/OD Internal1
I/O/OD Internal1
I/O/OD Internal1
I/O/OD Internal2
I/O/OD Internal2
I
I/O VDDUART
I/O/OD Internal2
I Internal2
I Internal2
I/O/OD Internal2
I/O/OD Internal2
I/O/OD Internal2
I/O/OD VDD1
I/O/OD VDD1
I/O/OD Internal2
I/O/OD Internal2
I/O/OD Internal2
I/O/OD VDD1
I/O/OD VDD1
I/O/OD VDDUART
I/O/OD Internal2
I/O/OD Internal2
After
Reset Reset
Z Z
Input Input
Input Input
PD/ Input PD/ Input Port 1.7
PD PD
1) 1)
PU PU
Z Z
- -
PD H
Z Z
PU PU
PD PD
Z Z
PD PD
1) 1)
PU PU
Conf. Conf.
PD def. PD def.
Z Z
PU PU
PU PU
Z Z
PD PD
PD PD
Z Z
1) 1)
PU PU
Z Z
10
PAN1322-SPP
ENW89841A3KF
General Device Overview
Function
Port 1.6
Hardware Reset, active low
Port 1.5
Port 1.8
Port 1.0 or
JTAG interface
Port 1.4 or
JTAG interface
Connect to VDD1 and refer to
chapter 12 item [3].
Sleep indication signal
Port 0.9
Mode selection Port 1:
0: JTAG
1: Port
JTAG interface
Port 0.10
Port 0.8
Port 1.1 or
JTAG interface
Port 0.3
Port 0.2
I2C data signal
I2C clock signal
Port 1.3 or
JTAG interface
Port 0.0
LPM wakeup output
Port 0.1
Port 0.5 or
UART receive data
Port 1.2 or
JTAG interface
Port 0.11
Revision 1.3, 2013-08-14