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IIS-BUS INTERFACE
IIS MODE REGISTER (IISMOD) REGISTER
Register
IISMOD
0x55000004 (Li/W, Li/HW, Bi/W)
0x55000006 (Bi/HW)
IISMOD
Master Clock Select
Master/slave mode select
Transmit/receive mode
select
Active level of left/right
channel
Serial interface format
Serial data bit per channel
Master clock frequency
select
Serial bit clock frequency
select
1.
The IISMOD register is accessible for each halfword and wordunit using STRH/STR and LDRH/LDR instructions or short
int/int type pointer in Little/Big endian mode.
2.
(Li/HW/W) : Little/HalfWord/Word.
(Bi/HW/W) : Big/HalfWord/Word.
21-6
Address
Bit
[9]
Master clock select
0 = PCLK
[8]
0 = Master mode (IISLRCK and IISCLK are output
mode).
1 = Slave mode (IISLRCK and IISCLK are input mode).
[7:6]
00 = No transfer
10 = Transmit mode
[5]
0 = Low for left channel (High for right channel)
1 = High for left channel (Low for right channel)
[4]
0 = IIS compatible format
1 = MSB (Left)-justified format
[3]
0 = 8-bit
[2]
0 = 256fs
(fs : sampling frequency)
[1:0]
00 = 16fs
10 = 48fs
R/W
Description
R/W
IIS mode register
Description
1 = MPLLin
01 = Receive mode
11 = Transmit and receive mode
1 = 16-bit
1 = 384fs
01 = 32fs
11 = N/A
Notes
SC32442B RISC MICROPROCESSOR
Reset Value
Initial State
0x0
0
0
00
0
0
0
0
00
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