Samsung SC32442B54 User Manual page 243

SC32442B RISC MICROPROCESSOR
DMA SPECIAL REGISTERS
Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of
the control registers control the DMA transfer, and other three ones monitor the status of DMA controller. The
details of those registers are as follows.
DMA INITIAL SOURCE (DISRC) REGISTER
Register
DISRC0 0x4B000000
DISRC1 0x4B000040
DISRC2 0x4B000080
DISRC3 0x4B0000C0
DISRCn Bit
S_ADDR [30:0]
DMA INITIAL SOURCE CONTROL (DISRCC) REGISTER
Register
DISRCC0 0x4B000004
DISRCC1 0x4B000044
DISRCC2 0x4B000084
DISRCC3 0x4B0000C4
DISRCCn Bit
LOC
INC
Address R/W
R/W
R/W
R/W
R/W
Base address (start address) of source data to transfer. This bit
value will be loaded into CURR_SRC only if the CURR_SRC is 0
and the DMA ACK is 1.
Address R/W
R/W
R/W
R/W
R/W
[1] Bit 1 is used to select the location of source.
0: the source is in the system bus (AHB).
1: the source is in the peripheral bus (APB).
[0] Bit 0 is used to select the address increment.
0 = Increment
If it is 0, the address is increased by its data size after each
transfer in burst and single transfer mode.
If it is 1, the address is not changed after the transfer. (In the
burst mode, address is increased during the burst transfer, but
the address is recovered to its first value after the transfer.)
Description
DMA 0 initial source register
DMA 1 initial source register
DMA 2 initial source register
DMA 3 initial source register
Description
Description
DMA 0 initial source control register
DMA 1 initial source control register
DMA 2 initial source control register
DMA 3 initial source control register
Description
1= Fixed
DMA
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
Initial State
0x00000000
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
Initial State
0
0
8-7