Service Processor; Service Processor Base - IBM p5 550 Technical Overview And Introduction

2.11 Service processor

The service processor (SP) is an embedded controller based on a PowerPC 405GP
processor (PPC405) implementation running the SP internal operating system. The SP
operating system contains specific programs and device drivers for the SP hardware
(Figure 2-13 on page 36).
The p5-550 uses the SP implementation. The key components include a FSP-Base (FSP-B)
and an Extender chipset (FSP-E). FSP-B and FSP-E are implemented on a dedicated card.
Figure 2-13 Service processor logical diagram

2.11.1 Service processor base

The PPC405 core is 5-stage pipeline instruction processor and contains 32-bit general
purpose registers. The Flash ROM contains a compressed image of a software load.
The SP base unit offers the following connections:
Two Ethernet Media Access Controller3 (MAC3) cores, which is a generic implementation
of the Ethernet Media Access (MAC) protocol compliant with ANSI/IEEE 802.3, IEEE
802.3u, ISO/IEC 8802.3 CSMA/CD standard. The Ethernet MAC3 supports both half
duplex (CSMA/CD) and full duplex operation at 10/100 Mbps. Both Ethernet port are
visible only to the service processor.
Two serial interfaces, accessible only though the serial ports of p5-550 on the rear side. At
the time of writing, the System Management Interface (SMI) is usable if a connection is
established to serial port 1. Terminals connected to serial port 2 receive only boot
sequence information without manual interaction. When the HMC is connected to the SP,
the serial ports are disabled and do not provide any external connection.
36
p5-550 Technical Overview and Introduction
Rear serial
ports system
S1
S2
Rear ports
FSP
HMC1
HMC2
FSP-E
SPCN1
UART
#3
SPCN2
UART
#4
System planar
MUX
UART UART
#2 #1
Flash
NVRAM
RJ45
Ethn.1
DDR
Interface
Ethn.2
FSP-B
RJ45
Flash ROM NVRAM
48 MB controller
SRAM
ALE
1 MB
DDR
64 MB