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Enhanced SMT features
To improve SMT performance for various workload mixes and provide robust quality of
service, POWER5 provides two features:
Dynamic resource balancing
– The objective of dynamic resource balancing is to ensure that the two threads
executing on the same processor flow smoothly through the system.
– Depending on the situation, the POWER5 processor resource balancing logic has
different thread throttling mechanisms.
Adjustable thread priority
– Adjustable thread priority lets software determine when one thread should have a
greater (or lesser) share of execution resources.
– POWER5 supports eight software-controlled priority levels for each thread.
ST operation
Not all applications benefit from SMT. Having threads executing on the same processor will
not increase the performance of applications with execution unit limited performance or
applications that consume all the chip's memory bandwidth. For this reason, the POWER5
supports the ST execution mode. In this mode, the POWER5 processor gives all the physical
resources to the active thread, allowing it to achieve higher performance than a POWER4
processor-based system at equivalent frequencies. Highly optimized scientific codes are one
example where ST operation is ideal.
Dynamic power management
In current Complimentary Metal Oxide Semiconductor (CMOS) technologies, chip power is
one of the most important design parameters. With the introduction of SMT, more instructions
execute per cycle per processor core, thus increasing the core's and the chip's total switching
power. To reduce switching power, POWER5 chips use a fine-grained, dynamic clock gating
mechanism extensively. This mechanism gates off clocks to a local clock buffer if dynamic
power management logic knows the set of latches driven by the buffer will not be used in the
next cycle. This allows substantial power saving with no performance impact. In every cycle,
the dynamic power management logic determines whether a local clock buffer that drives a
set of latches can be clock gated in the next cycle.
In addition to the switching power, leakage power has become a performance limiter. To
reduce leakage power, the POWER5 chip uses transistors with low threshold voltage only in
critical paths. The POWER5 chip also has a low-power mode, enabled when the system
software instructs the hardware to execute both threads at the lowest available priority. In low
power mode, instructions dispatch once every 32 cycles at most, further reducing switching
power. The POWER5 chip uses this mode only when there is no ready task to run on either
thread.
2.1.1 POWER chip evolution
The p5-550 system complies with the RS/6000 platform architecture, which is an evolution of
the PowerPC Common Hardware Reference Platform (CHRP) specifications. Figure 2-3
shows the POWER evolution.
Chapter 2. Architecture and technical overview
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