Available Processor Speeds - IBM p5 550 Technical Overview And Introduction

has a single DCM containing a POWER5 processor chip and a 36 MB L3 module. I/O
connects to the Central Electronic Complex (CEC) subsystem through the GX+ bus. Each
DCM provides a single GX+ bus for a total system capability of two GX+ buses. The GX+ bus
provides an interface to a single device such as the RIO-2 buses, as shown in Figure 2-4.
GX+ Controller
Figure 2-4 p5-550 DCM diagram
Each processor card contains a single DCM and the local memory storage subsystem for that
DCM. The processor card also contains LEDs for each FRU
CPU card itself. See Figure 2-5 for a processor card layout view.
Figure 2-5 Processor card with DDR1 memory socket layout view

2.2.1 Available processor speeds

The p5-550 operates with a processor clock rate of 1.65 GHz for POWER5 processor-based
systems.
To determine the processor characteristics on a running system, use one of the following
commands:
lsattr -El procX
1
Field Replacement Unit
2
The output of the lsattr command has been expanded with AIX 5L to include the processor clock rate.
D I D I
core core
1.9 MB L2
Where X is the number of the processor, for example, proc0 is the first
processor in the system. The output from the command
L3 Cache
Data Unit
36 MB
SMI II
SMI II
1
on the CPU card including the
Chapter 2. Architecture and technical overview
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
2
would be
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