Yamaha SB168-ES Service Manual page 21

PIN OUTER
NAME I/O
NO. NO.
159 L1 MA15 O Wave memory address bus 15
160 L2 MA16 O Wave memory address bus 16
161 L3 MA17 O Wave memory address bus 17
162 L4 MA18 O Wave memory address bus 18
163 L5 VDD - Power supply +1.2 V
164 L9 VSS -
165 L10 VSS -
Ground
166 L11 VSS -
167 L12 VSS -
168 L16 VDD - Power supply +1.2 V
169 L17 D11 I/O SH2A-CPU data bus 11
170 L18 D12 I/O SH2A-CPU data bus 12
171 L19 D13 I/O SH2A-CPU data bus 13
172 L20 D14 I/O SH2A-CPU data bus 14
173 M1 MA19 O Wave memory address bus 19
174 M2 MA20 O Wave memory address bus 20
175 M3 MA21 O Wave memory address bus 21
176 M4 MA22 O Wave memory address bus 22
177 M5 VSS -
178 M9 VSS -
179 M10 VSS -
Ground
VSS
180 M11 -
181 M12 VSS -
182 M16 VSS -
183 M17 D7 I/O SH2A-CPU data bus 7
184 M18 D8 I/O SH2A-CPU data bus 8
185 M19 D9 I/O SH2A-CPU data bus 9
186 M20 D10 I/O SH2A-CPU data bus 10
187 N1 MA23/PG4 O Wave memory address bus 23
188 N2 MA24/PG5 O Wave memory address bus 24
189 N3 MA25/PG6 O Wave memory address bus 25
190 N4 MA26/PG7 O Wave memory address bus 26
191 N5 VCCQ -
Power supply +3.3 V
192 N16 VCCQ -
193 N17 D3 I/O SH2A-CPU data bus 3
194 N18 D4 I/O SH2A-CPU data bus 4
195 N19 D5 I/O SH2A-CPU data bus 5
SH2A-CPU data bus 6
196 N20 D6 I/O
197 P1 MCS3N/PG3 O Wave memory chip select 3
198 P2 MCS2N/PG2 O Wave memory chip select 2
199 P3 MCS1N/PG1 O Wave memory chip select 1
200 P4 MWRN/PG0 O Wave memory write enable
201 P5 VSS -
Ground
202 P16 VSS -
203 P17 RD/WRN O SH2A-CPU read/write enable
204 P18 D0 I/O SH2A-CPU data bus 0
205 P19 D1 I/O SH2A-CPU data bus 1
206 P20 D2 I/O SH2A-CPU data bus 2
207 R1 MCS0N O Wave memory chip select 0
208 R2 MRDN O Wave memory read enable
209 R3 BTCHG I BOOT ROM switching control
210 R4 PA0 I/O Parallel port A0
211 R5 VDD -
Power supply +1.2 V
212 R16 -
VDD
213 R17 WE3N/DQMUU/PH3 O Writing byte of D31 - D24/Selecting D31 - D24 in case of SDRAM
214 R18 RASLN O RAS output for SDRAM
215 R19 CASLN O CAS output for SDRAM
216 R20 RDN O SH2A-CPU read enable
217 T1 PA1 I/O Parallel port A1
218 T2 PA2 I/O Parallel port A2
219 T3 PA3 I/O Parallel port A3
220 T4 PA4 I/O Parallel port A4
221 T5 VDD -
Power supply +1.2 V
222 T6 VDD -
223 T7 VSS - Ground
224 T8 VCCQ - Power supply +3.3 V
225 T9 VSS - Ground
226 T10 VCCQ -
Power supply +3.3 V
227 T11 VCCQ -
228 T12 -
VSS Ground
229 T13 VCCQ - Power supply +3.3 V
230 T14 VSS - Ground
231 T15 VDD -
Power supply +1.2 V
232 T16 VDD -
233 T17 A0/PH4 O SH2A-CPU address bus 0
234 T18 WE0N/DQMLL/PH0 O Writing byte of D7 - D0/Selecting D7 - D0 in case of SDRAM
235 T19 WE1N/DQMLU/PH1 O Writing byte of D15 - D8/Selecting D15 - D8 in case of SDRAM
236 T20 WE2N/DQMUL/PH2 O Writing byte of D23 - D16/Selecting D23 - D16 in case of SDRAM
237 U1 PA5 I/O Parallel port A5
PIN
FUNCTION
NO.
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
OUTER
NAME I/O
NO.
U2 PA6 I/O Parallel port A6
U3 PA7 I/O Parallel port A7
U4 VCCQ - Power supply +3.3 V
U5 ED1/PC1 I/O External CPU data bus 1
U6 ED5/PC5 I/O External CPU data bus 5
External CPU data bus 9
U7 ED9/PD1 I/O
U8 ED13/PD5 I/O External CPU data bus 13
U9 EA2/PK1 I External CPU address bus 2
U10 ECSN I External CPU chip select
U11 BCLK O Bit clock output
U12 IRQ0 I Interrupt input 0
U13 A25 O SH2A-CPU address bus 25
U14 A21 O SH2A-CPU address bus 21
U15 A17 O SH2A-CPU address bus 17
U16 A13 O SH2A-CPU address bus 13
U17 VCCQ - Power supply +3.3 V
U18 A3 O SH2A-CPU address bus 3
U19 A2 O SH2A-CPU address bus 2
U20 A1 O SH2A-CPU address bus 1
V1 PB0 I/O Parallel port B0
V2 PB1 I/O Parallel port B1
VCCQ Power supply +3.3 V
V3 -
V4 PB6 I/O Parallel port B6
V5 ED2/PC2 I/O External CPU data bus 2
V6 ED6/PC6 I/O External CPU data bus 6
V7 ED10/PD2 I/O External CPU data bus 10
V8 ED14/PD6 I/O External CPU data bus 14
V9 EA3/PK2 I External CPU address bus 3
V10 SDI0/PK5 I Serial audio input 0
V11 WCLK2/SDO2 O Word clock output 2/Serial audio output 2
V12 IRQ1 I Interrupt input 1
V13 BW_MD0 I SH2A-CPU data bus width configuration
V14 A22/PH5 O SH2A-CPU address bus 22
V15 A18 O SH2A-CPU address bus 18
V16 A14 O SH2A-CPU address bus 14
V17 A10 O SH2A-CPU address bus 10
V18 VCCQ - Power supply +3.3 V
SH2A-CPU address bus 5
V19 A5 O
V20 A4 O SH2A-CPU address bus 4
W1 PB2 I/O Parallel port B2
W2 VCCQ - Power supply +3.3 V
W3 PB4 I/O Parallel port B4
W4 PB7 I/O Parallel port B7
W5 ED3/PC3 I/O External CPU data bus 3
W6 ED7/PC7 I/O External CPU data bus 7
W7 ED11/PD3 I/O External CPU data bus 11
W8 ED15/PD7 I/O External CPU data bus 15
W9 ERDN/PK3 I External CPU read enable
W10 SDI1/PK6 I Serial audio input 1
W11 WCLK O Word clock output
W12 SYSCLK2 O Clock output 2
W13 WAITN/PK7 I External wait input
W14 A23/PH6 O SH2A-CPU address bus 23
W15 O SH2A-CPU address bus 19
A19
W16 A15 O SH2A-CPU address bus 15
W17 A11 O SH2A-CPU address bus 11
W18 A8 O SH2A-CPU address bus 8
W19 VCCQ - Power supply +3.3 V
W20 A6 O SH2A-CPU address bus 6
Y1 VCCQ - Power supply +3.3 V
Y2 PB3 I/O Parallel port B3
Y3 PB5 I/O Parallel port B5
Y4 ED0/PC0 I/O External CPU data bus 0
Y5 ED4/PC4 I/O External CPU data bus 4
Y6 ED8/PD0 I/O External CPU data bus 8
Y7 ED12/PD4 I/O External CPU data bus 12
Y8 EA1/PK0 I External CPU address bus 1
Y9 EWRN/PK4 I External CPU write enable
Y10 SDO0 O Serial audio output 0
Y11 O Serial audio output 1
SDO1
Y12 SYSCLK O Clock output
Y13 SYI I Sync. input from external device
Y14 A24/PH7 O SH2A-CPU address bus 24
Y15 A20 O SH2A-CPU address bus 20
Y16 A16 O SH2A-CPU address bus 16
Y17 A12 O SH2A-CPU address bus 12
Y18 A9 O SH2A-CPU address bus 9
Y19 A7 O SH2A-CPU address bus 7
Y20 VCCQ - Power supply +3.3 V
SB168-ES
FUNCTION
21