Wait Cycles Insertion - Texas Instruments OMAP5910 Reference Manual

Traffic Controller Memory Interface Registers
Table 16. Wait Cycles Insertion
Table 17. EMIF Fast Interface SDRAM Configuration Register 1
(EMIFF_SDRAM_CONFIG)
Bit Field
31−28 Reserved
27 CLK
56 Memory Interface Traffic Controller
RDWST
0
1
2
3
4
5
There is no automatic hardware adjustment of the programmed latencies
when the system clock frequency changes.
The following restrictions apply when synchronous burst read Intel protocol is
selected:
Only full-page burst mode is supported
-
Only sequential data access order is supported
-
Only 1 clock cycle data duration mode is supported (there is no advantage
-
in supporting 2 clock cycle duration since FLASH.CLK may be divided).
Page crossing is supported in page mode ROM burst read.
In asynchronous read mode, FLASH.ADV is activated during one FLASH.CLK
cycle in order to ensure compatibility with burst flash.
Value Description
Read is undefined. Writes must be zero.
SDRAM clock disable. See section 4.3.3.6, SDRAM
Clock Disable, for details related to disabling the
SDRAM clock.
0 Clock is not disabled.
1 Clock is disabled.
CLK is one of the prerequisites to meet TC idle. CLK
must be set before the memory interface can
acknowledge a TC idle request.
Number of Cycles Inserted
2
3
4
5
6
7
Reset
Value
Access
R All 0
R/W 0
SPRU673