Texas Instruments OMAP5910 Reference Manual page 28

Memory Interfaces
30 Memory Interface Traffic Controller
Two configuration registers are used in this operating mode:
FCLKDIV. Specifies the frequency ratio between the TC clock and
-
FLASH.CLK (see Table 14, EMIF Slow Chip-Select Configuration
Registers).
RDWST. Specifies the number of FLASH.CLK cycles between the falling
-
edge of FLASH.ADV and the edge at which first data is valid (see Table 14,
EMIF Slow Chip-Select Configuration Registers).
The FLASH.RDY signal is not used in this mode: however, it is used during
flash program and erase operations.
Note: Intel Burst Flash Operation
Intel burst flash (such as the Intel 28FxxxK3, 28FxxxK18, and 28FxxxW18),
requires the OMAP5910 FLASH.RDY pin to be pulled up instead of being
tied to the flash's WAIT pin. The traffic controller properly handles all timing
requirements without the WAIT pin assertion. Connecting these two pins
may cause a performance penalty.
SPRU673