A1~A7
D00~D15
PS1
PS2
PS3
PS4
*GAP
*INLCK
FANALM1
FANALM2
FANALM3
RFTIM
TLFTIM
RFALM
CSFALM
TLFALMS
TLFALML
Figure 5.3.12 Head/motor control LSI block diagram
Address
decoder
General-purpose
Input port
Motor Control
Interrupt control
Alarm detection
control
164
RFM0~RFM3
TLFM0~TLFM3
TLFI0~TLFI1
FCSFM0~FCSFM3
RCSFM0~RCSFM3
FANCNT1~FANCNT2
MT1I
POWST1