Yamaha RX-V2600 Service Manual page 65
Av receiver/av amplifier
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Also See for RX-V2600:
- Owner's manual (903 pages) ,
- Owner's manual (144 pages) ,
- Owner's manual (144 pages)
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IC301: M30845FJGP (FUNCTION P.C.B)
16-bit Microprocessor
Terminal Name
No.
Port Name
(P.C.B.)
1
TXD4
TXDH (MtoV)
2
CLK4
CLKH
3
DA1
LIMIT
4
DA0
FAN
5
SDA3/TXD3/TB2in
HDIMT
6
SCL3/RXD3/TB1in
/EN232C
7
TB0in
HRES
8
P146
/ICH
9
P145
HREQ
10
P144
DMT
11
P143
/CSDAC3
12
P142
/CSDAC2
13
P141
/CSDAC1
14
P140
/CSY
15
BYTE
BYTE
16
CNVss
CNVss
17
P87
/ICD
18
P86
/ICTI
19
RESET
RESET
20
Xout
Xout
21
Vss
Vss
22
Xin
Xin
23
Vcc
Vcc
24
NMI
NMI
25
INT2
REM1
26
INT1
REM2
27
INT0
RXDR
28
TA4in
/VSYNC
29
P80
/CSTI
30
TA3in/P77
TIBUSY
31
P76
SPIRDY
32
TA2in
/INTTI
33
P74
/CSDIR
34
TA1in
/INTDIR
35
P72/CLK2/TA1out
BT232C
36
P71/RxD2/SCO2
DRXM
37
P70/TXD2/SDA2
DTXM
38
P67/TxD1
TXDR
39
Vcc
Vcc
40
P66/RxD1
RXDR
41
Vss
Vss
42
P65/CLK1
RTS / CLKF
43
P64/CTS1/RTS1/
CTS / YDCBUSY
44
P63/TxD0
TXDD
45
P62/RxD0
RXDD
46
P61/CLK0
CLKD
I/O
PowerOn
Standby
MCUSleep [OFF]
SO
O
O
SO
O
O
DA
O
O
DA
O
O
TMR
O
O
I
O
O
TMR
O
O
O
O
O
TMR
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
MCU
MCU
MCU
MCU
MCU
MCU
O
O
O
O
O
O
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
IRQ
I
I
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
TMR
O
O
O
O
O
I
O
O
I / I
O / O
O / O
TMR
O
O
O
O
O
TMR
O
O
I / I
I / I
O / O
SI
O
O
SO
O
O
SO / SO
SO / SO
O / SO
MCU
MCU
MCU
SI / SI
SI / SI
SI [O] / SI
MCU
MCU
MCU
SO / SO
SO / SO
O / SO
I / O
I / O
I [O] / O
SO
O
O
SI
O
O
SO
O
O
Function
Data transmits to VIDEO_CPU
Clock transmits to VIDEO_CPU
Limiter control output
Temperature control FAN control output
HDMI MUTE input
VIDEO_CPU 232C communication line enable control
VIDEO_CPU response return input
VIDEO_CPU reset
VIDEO_CPUI transmission demand input
Digital FULL MUTE (HI=MUTE)
* Chip enable for S, C, SW2chDAC (Reserve)
2shDAC (PCM1791A) * Chip enable for 6
* Chip enable for YSS930 (#0 / #1 Common)
External data bus width change: 16 bit
Processor mode selection: Single chip mode/Hi: To boot mode
with a built-in flash/At the time of hard reset: It is to boot mode at
P50=H, P55=L, and CNVss=H
DIR initial clear
TI initial clear
Remote control pulse input 1
Remote control pulse input 2/Remote control pulse input for zone
remote control
RS232C/YDC reception detection
Vertical sync pulse INT
Chip enable for TI decoder DSP DA601
TI BUSY detection/CDDA write-in DATA input
DA601 GP0(0): TI DA601 Serial Ready / DRI WCK output: DIR
WCK input (WCK input for CDDA writing)
TI (DA601) interruption
Chip enable for DIR
DIR interruption
RS232C flash write-in mode detection / MULTI CH INPUT key
detection
DABIC IC RxD (XM data reception) / 1.5k pull up to +5SPC
DABIC IC TxD / 1.5k pull up to +5SPC
RS232C: Usual RS-232C asynchronous communication data
output / YDC: Transmitting terminal for AF220
Usual RS-232C asynchronous communication data input / At the
time of 232C driver OFF, since driver output is set to HiZ, it is
LowFix processing / Transmitting terminal for AF220
Usual RS-232C asynchronous communication RTS output /
Clock input for AF220
Usual RS-232C asynchronous communication CTS input / At the
time of 232C driver OFF, since driver output is set to HiZ, it is
LowFix processing / BUSY output for AF220
Serial data output to DIR, TI (DA601), YSS930, and DAC / DIR/
YSS: 4M, LSBF/TI: 1M, MSBF
Serial data reception to DIR, TI (DA601), YSS930, and DAC /
DIR/YSS: 4M, LSBF/TI: 1M, MSBF
Serial Clock output to DIR, TI (DA601), YSS930, and DAC
RX-V2600/DSP-AX2600
65
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