Schematic Diagram - Yamaha RX-V2600 Service Manual

A B C
SCHEMATIC DIAGRAM (DSP 1/2)
1
2
3
14 5.0
4
0.1 6
0
0.1
5.0 5 0
0
0.1 1 0
3
4 0.1
5.0 2
0
7
0
INPUT
SELECTOR
4.1
0
4.8 4.1 4.8
4.1 4.1
4.1 0
0.1 0
4.3 0.1
4.1 0.1
5 3.4
0 0 3.4
4.8 0 0.6
0.1
0
0.6
0.6
4.1 4.8 0
4.1 3.4
4.1 4.1
0 0 4.3
4.1
4.3
0
4.8 0.1
4.3 0.1 0
3.4
0.1
0 3.4 0
0 0.1
4.1
0 RECOUT
4.8 SELECTOR
6
DIGITAL IN
0.1
0.1
14 4.8 3.3
0
0
2.3 2.8 0 0.6
2.3 2.8 0.6
7
2.3 2.8 0.6
8
XM DT
U, C models
9
IC501: SN74LVU04APWR IC502: SN74AHCT00PWR IC504, 505: SN74LS151NSR
Hex Inverters Quad 2-Input Nand Gate 8-input Multiplexer
1A 1 14 VCC
1A 1 14 Vcc
9
S2
10
1Y 2 13 6A 1B 2 13 4B
S1
11
S0
2A 3 12 6Y 1Y 3 12 4A
7
E
2Y 4 11 5A 2A 4 11 4Y
10
2B 5 10 3B
3A 5 10 5Y
VCC = PIN 16
GND = PIN 8
2Y 6 9 3A
3Y 6 9 4A = PIN NUMBERS
GND 7 8 3Y
GND 7 8 4Y
D E F
Page 107 G7 Page 105 F3 Page 103
to POWER (5)_W7 to OPERATION (3)_CB904 to FUNCTION (1)_CB317
3.4 4.8
3.4 4.8
0
3.4
0.1
0.1
0
1.7
0
0.1 0
3.4
1.3 0
3.4 0
0
12
0 11 3.4
13
0.1
3.4
1.3
0
3.4
3.4
3.4
3.4
3.4
0.1
0.1 0
0 1.3
DIR
0
3.4
1.7 0.1
1.7 1.3
A-1 0
1.7
3.4
3.4
0 0.1
0.1
0
3.3
3.4
1.3
0
0
3.4
0
2.7
ANALOG IN 0
1.3
0
0
3.0
0
0
1.3
0.1
3.4
0 3.4 0 3.4
0.1
0 3.4 0
3.4
0
0 3.4 0 3.4
1.3
0
0 0 3.3
3.4
0.1
0.1 0.1 0
3.4
0.1 0
1.7 1.7
1.3 1.3
1.7
1.7 1.7
3.4
0
0
0 1.7
1.3
1.3
3.4
0
0
1.3
1.3
0
IC507: PQ012FZ01ZPH IC508: PQ025EZ5MZP
Voltage Regulator Regulator
DC input DC output
I0 I1 I2 I3 I4 I5 I6 I7
1 3 Vin 1
(Vin) (Vo)
4 3 2 1 15 14 13 12
Specific IC
NC 4
Bias power supply ON/OFF control
2 4
(VB) (Vc)
5
GND
6 5
Z Z
G H
J2 Page 103 J3 Page 103 J4
to FUNCTION (1)_CB318 to FUNCTION (1)_CB319
0
DECODER
No replacement part available.
サービス部品供給なし
IC512: D60YA003BPYP225
Decoder
Digital Signal Processors
EMIF32 L2 Cache/
L1P Cache
Memory
4 Banks Direct Mapped
McASP1 4K Bytes Total
64K Bytes
Total
McASP0
(4-Way)
C67x TM CPU
McBSP1
Instruction Fetch Control
Registers
McBSP0 Instruction Dispatch
Control
L2 Instruction Decode Logic
I2C1 Enhanced Memory
DMA Data Path A Data Path B
Test
Controller
DA610:
I2C0 (16 channel) A Register File B Register File
192K Bytes In-Circuit
Emulation
Timer 1 DA601:
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t Interrupt
Control
Timer 0
GP1
L1D Cache
GP0 2-Way Set
R2 ROM
Associative
512K 4K Bytes Total
HPI16 Bytes
Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
IC509: µPC29M33T-E1-AZ
IC510, 551:
Voltage Regulator SINGLE 2-INPUT POSITIVE-OR GATE
3 Vo
A 1
1 INPUT
B 2
Specific IC
2 Vc
GND 3
5 Safety Drive
Limiter
GND
Amp.
3 OUTPUT
Excessive Electric
Current Protection
GND
2
I J K
POINT A-1 Pin 26 of IC508
U, C, R, T, K, A, B, G, L models
J model
0.1
3.4
3.4
0
1.8
0.1
0.7
1.2
0
1.3
1.3
3.3
3.3
1.3
0
3.4
1.8
1.0
3.4
0
1.3
3.3
3.3
3.3
3.3
3.3
3.3
3.4
0
1.3
3.3
3.3
3.3
DIGITAL IN
3.3
3.3
ANALOG IN
3.3
3.3
1.3
0
3.4
3.3 3.4 0
3.3 3.3 3.3 0.1
3.3 3.3 3.3 0.1
0 0 0.1
3.4
3.3 3.3 0.1
3.4 3.3 3.4 ~
3.4 0.1
3.4 3.4
0 3.3 3.3 0.1
1.3 3.3 3.3 0.1
0 0
3.3
3.3
3.4
3.3
3.4
3.4
3.4 3.4
3.4 1.8
3.4
3.4 0.1
3.4
0.1
~ 0.1 2.5
0.1
0.1 ~
0.1 3.5 3.0
0.1 ~ ~
3.1 3.0 3.1
3.1 ~ 3.1
3.4 0 0.1
IC511: SN74AHCT08PWR IC571: SN74AHC1G08DCKR
SN74AHCT1G32DCKR Quad 2-Input And Gate 2-input positive-AND gate
1A 1 14 Vcc
A 1 5 Vcc
1B 2 13 4B
5 Vcc
1Y 3 12 4A B 2
2A 4 11 4Y
GND 3 4 Y
4 Y 2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
L M N
RX-V2600/DSP-AX2600
IC506: LC89057W-VF4A-E
Digital Audio Interface Transceiver
EMPHA/UO AUDIO/VO INT CL CE CI XMODE
32 33 35 48 39 38 41
Microcontroller
RXOUT 1
Cbit, Ubit 37 DO
I/F
RX0 2
36 RERR
RX1 3
RX2 4
Demodulation
Input Data
RX3 5 & 21 RDATA
Selector Selector
Lock detect
RX4 8
RX5/VI 9
24 SDIN
RX6/UI
10
16 RMCK
LPF 13 PLL
17 RBCK
Clock 20
RLRCK
TMCK/PIO0 44
Selector
22 SBCK
TBCK/PIO1 45 Modulation
1/N
& 23 SLRCK
46
TLRCK/PIO2
Parallel Port
TDATA/PIO3 47
TXO/PIOEN 48
29 28 27 34
XIN XOUT XMCK CKST
IC533, 534: TC74VHC153FT
IC513, 552: SN74LV245APWR
Dual 4-Channel Multiplexer
Octal Bus Transceiver
with 3-state Outputs
A 14
S0
S0
DIR 1 20 Vcc
S1
S1
A1 2 19 OE
B 2
S2
S2
A2 3 18 B1
S3
S3
A3 4 17 B2
1C0 6
7 1Y
A4 5 16 B3
S0
1C1 5
A5 6 15 B4
S1
1C2 4
A6 7 14 B5
S2
A7 8 13 B6 1C3 3
S3
A8 9 12 B7
1G 1
GND 10 11 B8 2C0 10
9 2Y
S0
2C1 11
S1
12
2C2
S2
2C3 13
S3
2G 15
IC514: SN74LV157APWR
Quadruple 2-line to 1-line data selectors/multiplexers
1A 2
4 1Y
1B 3
A/B 1 16 V
2A 5 CC
1A G
2 15
7 2Y
2B 6 1B 3 14 4A
1Y 4B
4 13
3A 11 2A 5 12 4Y
2B 6 11 3A
3Y
9
3B
10 2Y 7 10 3B
GND 8 9 3Y
4A
14
12 4Y
4B 13
G 15
A/B 1
IC515: W9816G6CH-7
512K x 2 Banks x 16 Bits SDRAM
CLK 35
CLOCK
BUFFER
CKE 34
COLUMN DECODER
CS 18 CONTROL
SIGNAL R
RAS 17 GENERATOR O
COMMAND
W
CAS 16 DECODER
D CELL ARRAY
2 DQ0
WE 15 E BANK #0
C
3 DQ1
O
D
E 5 DQ2
R
A10 20 6 DQ3
SENSE AMPLIFIER
8 DQ4
9 DQ5
MODE
0.1 A0 21 11 DQ6
REGISTER
12 DQ7
3.4 A3 24 ADDRESS
REFRESH DQ
BUFFER
0 COUNTER BUFFER 39 DQ8
A4 27
3.3 40 DQ9
A9 32
42 DQ10
3.3
BA 19
43 DQ11
3.3
45 DQ12
46 DQ13
3.3
REFRESH COLUMN COLUMN DECODER
48 DQ14
3.3 COUNTER COUNTER
R
3.3 O 49 DQ15
W
3.3
D CELL ARRAY
E BANK #1
C
O
3.3
D
E
14 LDQM
3.3 R
36 UDQM
3.3 SENSE AMPLIFIER
3.3
3.3
3.3
3.3
3.3
IC542: MBM29LV400BC-70
3.4
0 FLASH MEMORY
3.4
0.3
DQ to DQ
0 15
RY/BY
RY/BY
Buffer
V CC
V SS Erase Voltage Input/Output
Generator Buffers
001.sht
WE
State
BYTE Control
RESET
Command
DSP
Register
Program Voltage
Generator Chip Enable
STB Data Latch
Output Enable
Logic
CE
OE
Y-Decoder Y-Gating
STB
Timer for
Address
Low V CC Detector Program/Erase
Latch
X-Decoder
Cell Matrix
A 0 to A 17
A
-1
101