Yamaha YMC-700 Service Manual page 78

A B C
YMC-700/YMC-500
DIGITAL 4/8
1
Q Q
3
2
EEPROM
IC445
3
to DIGITAL 8/8
3.3
0
0
to DIGITAL 3/8
3.3
0
4
to DIGITAL 8/8 3.2
1.3
3.3
3.3
3.3
to DIGITAL 8/8
0
3.3
0.2
0
0
0
0
0
0
0
1.3
5
0.9
1.7
0
0
0
0
0
T E
L 1 3
3.3
to DIGITAL 3/8 3.1
3.3
to DIGITAL 6/8
3.3
IC450
to DIGITAL 3/8 0
0
6 0
0
0
0
0
CB341
7
IC449
0
3.3
0
0
3.3
IC449
8
9
w w w
10
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★ Components having special characteristics are marked
and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
78
D E F
to DIGITAL 8/8
7 1 5
6 3
1.4
0
3.3
POINT D XL341 (Pin 10 of IC341)
D
1.3
1.3
3.3
IC341
0
MICROPROCESSOR
3.3
1.6
No replacement part available.
9 4 2 2 9 6 5 1 3
1.3
1.3
BUS BUFFER
POINT E 1 / R4429 (+3.3EX), 2 / Pin 13 of IC341
x a o
. i
R4429 1 R4429 1
(+3.3EX) (+3.3EX)
IC341 2 IC341 2
(13 pin) (13 pin)
POWER ON POWER OFF POWER ON
G http://www.xiaoyu163.com H
YMC-700 YMC-500
1 5 2
0 1
E
1.4 3.3
1.9
1.4
IC347
IC347
IC346
3.3 3.3 0
3.3 0 0 3.3 3.3
3.3
IC447
0
3.3
2.4
0 IC447
IC447
3.3
0
1.3
2.4
IC447
0
0
3.3
IC347
2.4 1.3
IC346
3.3
3.3
3.3
3.3
3.3
0
3.3
0
3.3
0
3.3
3.3
2.7
3.3
0
1.7
3.3
2.9
3.3
2.2
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
0.2
1.2
1.4
2.6
2.8
2.9
3.3
Q Q SDRAM
3
0
3.3 0
0.5 3.1
1.8
3.3 0
1.7
1.8
0.3 0.4
1.4
0 3.3
1.4
1.7
0.3 0.4
1.3
3.3 0
1.4
3.3
0.3 0.6
0
0 3.3
3.3 0
3.3 0.2
2.9 1.7
3.3 3.3
2.7 1.3
2.4 1.4
0 1.7
2.2 1.4
1.4 1.4
2.6 1.8
2.8 1.7
2.9 1.8
3.3 0
SDRAM
3.3 0
0.4 0.4
3.3 0
0.3 0.4
0 3.3
0.3 0.5
3.3 0
0.3
2.3
0 3.3
3.3 0
3.3 1.2
2.9 1.7
3.3 3.3
2.7
1.3
2.4 1.4
0 1.7
2.2 1.4
1.4 1.4
2.6 1.8
2.8 1.7
to DIGITAL 6/8, 7/8
2.9
1.8
3.3 0
u 1 6 3
y
R4429 1
(+3.3EX)
IC341 2
(13 pin)
POWER OFF
I J K
2 4
8 9
3.3 3.3 3.3 3.3 3.3
IC347
IC346 IC348 IC446 IC447
0 0 0 0 0
IC347
0.2 3.3
0 3.3
3.3
3.3
3.3
3.3
3.3 0
3.3 0
3.3
3.3
0
3.3
3.3
0 3.3 3.3 3.3
IC345
0 IC348
3.3
3.3
3.3 IC348
3.3
3.3
2.2 IC348
2.2
3.3
IC348
3.3
1.3
IC349
3.3
3.3
3.3 0
2.4 IC446 3.3
3.3
3.3 3.3 3.3
3.3
0.6 3.3
3.3
3.3
IC446 3.3 0
3.3
1.3
3.3 3.3
3.3
3.3
3.3
3.3 3.3
3.3
3.3
3.3
3.3
0 3.3
7 6 3 1 5 1 5 0 8
FLASH MEMORY
0 0
3.3
0
0 0
1.3 0.4
1.4 3.1
1.3 0.4
1.7 0.4
1.4 0.5
3.3 0.4
2.3
0
3.3 0.6
3.3
0 0.3
3.3 0.3
3.3
2.4
0.3
0.3
0
1.4 0.3
1.8 0.4
1.7 0.5
1.8 3.3
0
2.9
3.3
2.8
2.6 1.4
IC445: LE25LA322M-TLM-E
32 k-bit serial SPI EEPROM
m
X ·
c o
DECODER
ADDRESS
BUFFERS
and
LATCHES
.
CONTROL
LOGIC
SERIAL INTERFACE
CS# SCK SI SO WP# HOLD#
L M N
IC341: AD91089ZSKBC
Microprocessor 2
9 8 9 9
JTAG test Event controller/
Watch dock timer
and emulation Core timer
Real time clock
Voltage
regulator
to DIGITAL 5/8
UART port IrDA®
Memory
L1 instruction L1 data
management
memory memory
unit
Timer0, Timer1, Timer2
Core/System bus interface
PPI/GPIO
to DIGITAL 8/8
DMA controller
Serial port (2)
SPI port
Boot ROM
External port FLASH,
SDRAM control
IC342, 343: K4S560832J-UC75000
256 M synchronous DRAM
LWE
Data Input Register
LDQM
Bank Select
16M x 4 / 8M x 8 / 4M x 16 V DD 1 54
to DIGITAL 8/8
DQ0 2 53
V 3
16M x 4 / 8M x 8 / 4M x 16 DDQ 52
DQi DQ1 4
51
16M x 4 / 8M x 8 / 4M x 16 DQ2 5 50
V SSQ 6 49
CLK
16M x 4 / 8M x 8 / 4M x 16 DQ3 7 48
DQ4 8 47
ADD V DDQ 9 46
DQ5 10 45
Column Decoder
DQ6 11 44
V
SSQ 12 43
DQ7 13 42
Latency & Burst Length V 14 41
DD
LDQM 15 40
WE 16 39
LCKE
Programming Register CAS 17 38
RAS 18 37
LRAS LCBR LWE LCAS LWCBR LDQM
CS 19 36
BA0 20 35
BA1
21 34
Timing Register A10/AP 22 33
A0 23 32
A1 24 31
A2 25 30
CLK CKE CS RAS CAS WE L(U)DQM
A3 26 29
V DD 27 28
IC344: K8P6415UQB-PI4B000
64 Mb page mode NOR flash
to DIGITAL 6/8
to DIGITAL 6/8
Bank 0 X Bank 0
Address Dec Cell Array
to DIGITAL 5/8
Y Dec Latch and
Vcc Control
A15 1
48
A14 2 47
Vss A13 3 46
to DIGITAL 6/8
A12 4 45
CE Latch and A11 5 44
Y Dec Control
A10 6 43
OE Bank 1 X Bank 1 A9 7 42
I/O
Address Dec A8 8 41
to DIGITAL 5/8, 6/8 Interface Cell Array
A19 9 40
WE A20 10 39
and
WE 11 38
Bank
RESET RESET 12 37
Control
A21 13 36
RY/BY Bank 3 X Bank 3 WP/ACC 14 35
Address Dec Cell Array RY/BY 15 34
WP/ACC A18 16 33
Latch and
Y Dec Control A17 17 32
A7 18 31
A0-A21 30
A6 19
A5 20 29
Erase
DQ0-DQ15 A4 21 28
Control
High A3 22 27
Block
Voltage A2 23 26
Inform Gen.
Program A1 24 25
Control
9 2 4 9 8 2 9 9
IC345: SN74LV123APWR
Dual retriggerable monostable multivibrators with schmitt-trigger inputs
1A 1 16 VCC
1B 1R ext /C ext
2 15
1C ext
1CLR 3 14
R ext /C ext
1Q 4 13 1Q
A
C ext
2Q 5 12 2Q
2C ext 6 11 2CLR
B Q
2R ext /C ext 7 10
2B
GND 8 9 2A
R Q
CLR
IC346: 74LVC08APW
Quad 2 input AND gate
1A 1 14 Vcc
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y
IC347: 74LVC14APW
Hex inverter schmitt trigger with 5 V tolerant input
1A 1 14 Vcc
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y
IC349, 441-444: 74LVC245APW,118
IC348, 446: 74LVC32APW
Quad 2 input OR gate Octal bus transceiver with direction pin
with 5 V tolerant input/outputs (3-state)
1A 1 14 Vcc
DIR 1 20 Vcc
1B 2 13 4B
A0 2 19 OE
1Y 3 12 4A A1
3 18 B0
2A 4 11 4Y A2 4 17 B1
A3 5 16 B2
2B 5 10 3B
A4 6 15 B3
2Y 6 9 3A
A5 7 14 B4
GND 7 8 3Y
A6 8 13 B5
A7 9 12 B6
GND 10 11 B7
EEPROM IC447: 74LVC00APW IC448-450: 74LVC1G08GW
Cell Array
Quad 2 input NAND gate
Single 2 input AND gate
1A 1 14 Vcc
Y ·DECODER
B 1 5 Vcc
1B 2 13 4B
I/O BUFFERS A 2
1Y 3 12 4A
and
DATA LATCHES CS# 1 8 VDD
2A 4 11 4Y
2 7 GND 3 4 Y
SO HOLD#
2B 5 10 3B
WP# 3 6 SCK
VSS 4 5 SI 2Y 6 9 3A
GND 7 8 3Y
V SS
DQ15
V
SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N.C/RFU
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V SS
A16
N.C
Vss
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
Vss
CE
A0