QQ
3 7 63 1515 0
Pin No.
Pin Name
D13
HADRS[18]
D14
HADRS[14]
D15
HADRS[9]
D16
MSINS
D17
SCLK[2]
D18
CTS[2]
D19
TX[0]
D20
TX[3]
D21
RX[3]
D22
VMCLK
D23
RX[0]
D24
HDATA[13]
D25
HDATA[10]
E1
AT2CS[1]
E2
AT1RESET
E3
AT1DATA[7]
E4
AT1DATA[8]
E5
VDD
E6
VSS
E7
VDD
E8
VDD33
E9
VSS
E10
VDD
E11
VSS
TE
L 13942296513
E12
VDD33
E13
VDD
E14
VSS
E15
VDD
E16
VSS
E17
VDD33
E18
VDD
E19
VSS
E20
VDD
E21
VDD33
E22
HDATA[4]
E22
HDATA[14]
E23
HDATA[12]
E24
HDATA[9]
E25
HDATA[8]
F1
AT2ADR[1]
F2
AT2ADR[0]
F3
AT2ADR[2]
F4
AT2CS[0]
F5
VSS
F21
VDD
F22
HDATA[11]
F23
TEST
www
F24
HDATA[7]
F25
HDATA[5]
G1
AT2DIOR
.
G2
AT2IORDY
G3
AT2DMACK
G4
AT2INTRQ
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I/O
O
Output of address 18
O
Output of address 14
O
Output of address 9
—
Fixed at "L"
—
Fixed at "H"
O
Output of UART(CSIO)/GPIO
O
Output of UART(CSIO)/GPIO
O
Fixed at "H"
O
Fixed at "H"
I
Input of 27MHz system clock
O
Output of UART(CSIO)/GPIO
—
Input/output of data 13
—
Input/output of data 10
O
Output of chip select signal for HDD driver
O
Output of reset signal
I/O
Input/output of data 7 for DVD
I/O
Input/output of data 8 for DVD
—
Power supply input (Digital 1.0V)
Digital GND
—
Power supply input (Digital 1.0V)
—
Power supply input (Digital 3.3V)
Digital GND
—
Power supply input (Digital 1.0V)
Digital GND
—
Power supply input (Digital 3.3V)
—
Power supply input (Digital 1.0V)
Digital GND
—
Power supply input (Digital 1.0V)
Digital GND
—
Power supply input (Digital 3.3V)
—
Power supply input (Digital 1.0V)
Digital GND
—
Power supply input (Digital 1.0V)
—
Power supply input (Digital 3.3V)
I/O
Input/output of data 4
I/O
Input/output of data 14
I/O
Input/output of data 12
I/O
Input/output of data 9
I/O
Input/output of data 8
O
Output of device address 1 for HDD driver
O
Output of device address 0 for HDD driver
O
Output of device address 2 for HDD driver
O
Output of chip select signal for HDD driver
Digital GND
—
Power supply input (Digital 1.0V)
I/O
Input/output of data 11
—
Fixed at GND
I/O
Input/output of data 7
x
ao
u163
y
I/O
Input/output of data 5
O
Output of I/O read signal
i
I
Input of I/O ready signal
O
Output of ACK signal from DMA
I
Input of IRQ signal
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2 9
8
Function
Q Q
3
6 7
1 3
1 5
co
.
5-8
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9