Radio Shack TRS-80 Service Manual page 16
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TC40H139
Truth
Table
n
YO
Input
Output
EtW!U:
SELECT
G
A
B
YO
Yl
Ya
Y8
Yi
H
*
*
H
H
H
H
L
L
I.
L
H
H
H
A
Y2
L
H
L
H
I.
H
ill
V3
c
L
L
H
H
H
L
H
L
H
H
H
H
H
L
*=
I
rre
leVllnt
•
Selection of I
YO
- I Y3 by the decoder IC (TC40H
l
39H)
is
done
when
the
gate signal
(IG)
input
BFO is
low.
YO
With
low
st ate
of AD
14 and
ADI
5,
the YO
output
becomes
low to select the system ROM
area
of
the
module
unit.
(IYli)
(0
000
- 3FFF address setup)
Yi
With
ltigh
state
of ADl4 and
low state of ADI5,
the YI output
becomes low to
select
the gate
(G2A) of
the
IC
(IYI)
(TC40HJ38F)
. (4000-7FFF
address
setup)
Y2
With
low
state
of
ADl4
and high state of ADIS, the
Y2
output becomes
low
to
select the
expansion
ROM •rea
of
(
1 Y2)
the
module
unit.
(8000-
BFFF address
setup)
Y3
With high
state of
ADl4
and
ADI S,
the Y3
output becomes low to select
the system program
ROM (SC-0131281')
(I Y3)
and
the 1/0
port
(LHS811)
.
(COOO
-
FFFF address setup)
•
Selection of SO
- S7 by
the decoder IC (TC40Hl38F) is
done when
the gate signal
input
MEO (GI)
is
high,
YI (GiA) low,
and
G2B.is
low
(wltich
is
nom1ally low).
SO
With all of
AD
I
I
, ADl2 and ADJ3
in
low
st
ate, SO goes
to
the
low state and selects
the
RAM3
(TC5517AF).
(YO)
(4000-
47FF
address setup)
S
J
With
high
state
of
ADI
I
and Jow
state
of ADI 2
and
AD13,
SI goes to the low state
to
select
tlte
option user
RAM
(Y
I)
area.
(4800-4FFF address
setup)
S2
With
low
st ate
of
ADI
I
and
high state of
AD12
and
low
state of
ADJ3,
S2
goes
t
o
the
low
state to
select
the option
(Yi)
RAM ;11ea. (5000
-
57FF
address setup)
S3
With high
st ate
of
ADJ! and
ADl2
and
low
state
of
ADl3,
S3 goes
to
the low
state
to
select
the
option user RAM
(Y3)
area. (5800-
SFFF
address
setup)
S6
With low state of ADI
I
and ltigh
state of
ADl2 and
AD13,
S6 goes to
the low
state to receive the
interrupt
input
(Y6)
from
•n
option into
the
1/0 port. (7000 - 77FF
~dd
ress
setup)
57
Wit
h
all
of ADI
I; ADl2,
and
ADl3
in ltigh
state,
S7 goesto the low
state
t
o
select the
system 111emory
RAM! and
(Y7)
2
(
TCSSJ4P). (7800 - 7FFF
addres setup)
RAMI and RAM2 ;11e 4·bit
RAMs,
independently
used to assume low
order
and high
order bits
to
comprise one
byte with a pair
of
4
bits
each.
•
Selection
of 2Y2 and 2Y3
by the
de<:oder IC (fC40Hi39) is done when
the
gate of
2G
becomes
active
with
the select
ion of
the
TC40H 138F output, $6
(Y6).
2Y2
With low state of AD8 and hlgh state
of
DMEO,
the
ffi
output
goes
to the low
stat
e
so
that
the
NANO
gate output
(V2)
V2 is turned ltigh to select the display chip I and 3
. (7600-
76FF address
setup)
2Y3
With
ltish state
of AD8 and
DMEO,
the
2Y3
output
goes
to
the
low state
so that
the
NANO
g•
t•
e
out V3
is turned
(V3)
high
t
o
select t
he
display
chip
2
and 4.
(7700
-
7FFF
address setup)
•
Display cltip (SC882G)
is
a 4·bit
RAM,
comprised of
one
byte of
data wit
h
4
low order
bits and 4 ltigh
order bits
of
data,
so tlt3t
even
the
cltip select signals are
used
in
pair of cltip
I
with
cltip 3
•nd
chip 2
with chip 4.
Do not sale
this
PDF !!!
-13-
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