Lh581 L 1/0 Port - Radio Shack TRS-80 Service Manual

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3.
LH5811 110 PORT
(1)
Outline
The
LHSS
l
I
1/0
port is
the
single
chip
LSI
of
CMOS s1a1ic
circuit thal can be
connecled with
a
general
iPUrpose 8·bit
Cl'U.
It
has lhe
following
funclions:
(I)
Two
pairs of
S·bit bidlreclional pons
(2) One pair of 8-bit bidirectional ports
(3) Two lines of interrupt request inputs.
one
of
lhem
is the
input
from pon.
(4)
One
line of
interrupt request
oulpul.
(5)
CPU
wait control
(6)
Serial
control
(2
) Functions
(I)
Ports.
PAO-
PA7 and
PBO -
Pll7, can be
programmed
for
1/0
directions
by each
bit.
The
CPU
can
access
PAO-
PA7 and
PBO-
PB7 as though
one
Jocalion
of
memory.
(2) PCO
-
PC7 is the port
of
output
type.
The
CPU
can
access
it as
though one location of
memory.
Also, lhe latch clock P9 to
the
PC pon can be supplied directly from 1n ex1emal
source.
(3) LHS81 J incorporates two interrupt request inpuls, JRQ and P67, when
apply
inlerrupt
requesl
of
the CPU at lhe
rising
edge
of the
inpul
when
the
corresponding
bit
of the internol mask
register
is "I".
Signal
PB7 represents the
8th
bit
of the
poll
PB
and
ii
needs
lo
be
In
the
input mode
when the
interrupt
inpul is
applied.
(4)
The I.H58J J
has a
CPU
wail
conlrol
circuit
which
11ses two output Hnes of memoiy
enable
signals
for
a
memory
Iha!
has
slower access time.
In
addition.
two
input
lines
for
the
wait
conditions
are
used.
Six differe.nt
of
access
times
can
be
chosen
by
progr:unming.
(5) The following
funclions
>re provided
for serial
conlrol.
A.
Serial
data transmi$$ion
Serial
data
transmission
is used
~11he
formal
ofstarl
bit/8-bil
data/2
slop
bils.
Trilllsmission
clock
is
programmable
by changing
internal
and
external
clocks, as well
as
changing
the
clock
rate;
I
/I, 1/2,
1/l
28, 1/256, 1/512, 1/1024,
1/2048
and
1/4096
of the basic
clock.
B.
Serial data reception
When
a stan bil
is
re.cei\•ed
in
the
idle state,
8 bits
of data
is
received. and
stored
in the internal register
a.
n d
the
in1errupt
request
flt1R
is set
on
.
Receplion
clock
l.
s
sent from the
exlernal
clnck
0
11d
must
be
synchronized with
the
serial d313
Input
.
C.
LCD
driver
con1rol
The LCD driver
Is
COMCCted
with three
signal
lines of
the
lransmission clock, a
serial
data bus, and a
synchronous
signal line
10
carry
ou1
data
transfer
for chip
selec1,
addressing,
and dola
read/write.
For the
transml~sion
clock in
this
case,
the
clock
rate
can be prograrnmed in
the
same
manner
as
In the
serial datu
transmission clock. (Transmission
clock
to
the LCD
driver
is
I Ml
lz.)
D.
Pulse
waveform
The
pulse
waveform
can
be senl
out
in continuation. Eiglit sons
of
frequencies
are
programmable; 1/1,
1/2, 1
/128,
1/256,
l/5
I
2, 1/1024, and 1/4096 of the basic
clock.
E.
Transmission to
audio cassette
tape
recorder
The
modulated
signal can
be senl from
the
SDO
ou1put
in the format
of
s1ar1 bit/8·bll
data/2
stop
bits.
Modulation
clock.
s ,
FX
and
FY,
can be set
sepuatcly
to
any
of cl<>ck
rate;
I
/64,
I/
128,
I
/256,
I /S 12,
and
1/
1024
of the
basic
clock.
·
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