Sony BDP-CX7000ES Service Manual page 92

BDP-CX7000ES
QQ
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Pin No. Pin Name
G9 VDD3
G10 GND
G11 VOHSB
G12 AOHBD0
G13 VODY9
G14 VDD3
G15 AOHLRCK
G16 SAVDDIG
G17 SAVDDANA
G18, G19 SAGNDDIG
G20 GPIO36
G21 VDD10
G22 GND
G23, G24 VDD3
G25 GPIO11
G26 VDD10
G27 VRGND
G28 TMODE2
G29 S2CKIN
G30 S0DOUT
G31 S0CKOUT
G32 S2DIN
G33 S0DIN
H1 GND
H2 CLKSEL
TE
H3 PCICLKI
L 13942296513
H4 GND
H5 PCIRSTB
H6 VDD3
H7 VDD10
H27, H28 TMODE4, TMODE1
H29 S2CSB
H30 GND
H31 UA1DCDB
H32 UA1RIB
H33 UA1RSTB
J1 UMDQS1
J2 GND
J3 UMVDD18
J4 CLK27OUT
J5 PCIAD30
J6 VDD3
J7 VDD10
J27 TMODE0
J28 RSTSWB
J29 UA1DRSB
J30 UA1TXDB
J31 UA1CTSB
J32 UA1DTRB
J33 UA1RXDB
K1 UMDQSB1
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K2 GND
K3 UMDQ10
K4, K5 GND
K6 UMVDD18
.
K7 GND
K27 NMI
K28 GND
92
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I/O
- Power supply terminal (+3.3V)
- Ground terminal
O Horizontal sync signal output to the digital video format converter
O Audio signal output to the HDMI transmitter
O Digital video (Y) signal output to the digital video format converter
- Power supply terminal (+3.3V)
O L/R sampling clock signal output to the HDMI transmitter
- Power supply terminal (+1.05V) (digital system)
- Power supply terminal (+1.8V) (analog system)
- Ground terminal (digital system)
I/O Not used
- Power supply terminal (+1.05V)
- Ground terminal
- Power supply terminal (+3.3V)
I/O Not used
- Power supply terminal (+1.05V)
- Ground terminal
I Test terminal Not used
I Serial data transfer clock signal input from the system controller
O Serial data output to the D/A converter, FPGA, HDMI interface and component interface
Serial data transfer clock signal output to the D/A converter, FPGA, HDMI interface and
O
component interface
I Serial data input from the system controller
I Serial data input from the FPGA, HDMI interface and component interface
- Ground terminal
System clock selection signal input terminal
I
Fixed at "L" in this set
I 33 MHz clock signal input terminal
- Ground terminal
I Reset signal input from the system controller
- Power supply terminal (+3.3V)
- Power supply terminal (+1.05V)
I Test terminal Not used
I Chip Select signal input from the system controller
- Ground terminal
I Interrupt signal input from the HDMI transmitter
I Not used
O Chip select signal output to the FPGA
O Data strobe signal (positive) output to the SD-RAM
- Ground terminal
- Power supply terminal (+1.8V)
O 27 MHz clock signal output terminal
I/O Two-way address and data bus with the USB interface
- Power supply terminal (+3.3V)
- Power supply terminal (+1.05V)
I Test terminal Not used
I Reset signal input from the system controller
O Not used
O Not used
O Reset signal output to the digital video format converter and FPGA
O Power supply on/off control signal output terminal for VBUS
I Not used
O Data strobe signal (negative) output to the SD-RAM
- Ground terminal
I/O Two-way data bus with the SD-RAM
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y
- Ground terminal
- Power supply terminal (+1.8V)
i
- Ground terminal
I Non maskable interrupt signal input terminal
- Ground terminal
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2 9
8
Description
"L": OSC input, "H": External clock signal input
Q Q
3 6 7 1 3 1 5
"L": reset
Not used
"L": reset
co
.
Not used
9 4 2 8
0 5 8 2 9 9 4 2 8
"L": reset
"H": power on
m
9 9
9 9