Schematic Diagram - Control Section (1/5) - Sony BDP-CX7000ES Service Manual

Hide thumbs Also See for BDP-CX7000ES:
Table of Contents

Advertisement

Q Q
3 7 6 3 1 5 1 5 0

6-37. SCHEMATIC DIAGRAM - CONTROL Section (1/5) -

1
2
IMD (ES) BOARD
(Page 71)
IMD (ES)
61
A
BOARD
TEMP
(3/5)
SYSCON_REQ
(Page
IMD (ES)
62
LED_BD
BOARD
71)
LED_DOOR
(3/5)
HAL_TXD
IMD (ES)
63
BOARD
HAL_RXD
(5/5)
(Page 73)
B
64
FL_XRESET
C
FL_XCS
FL_CLK
IMD (ES)
BOARD
FL_DATA
(3/5)
FLD_XPCONT
(Page 71)
JOG_B
65
JOG_A
KEY_3
D
IMD (ES)
KEY_2
BOARD
KEY_1
(3/5)
KEY_0
(Page 71)
IMD (ES)
66
DOOR_SW
BOARD
(4/5)
LOAD_SW
(Page 72)
T E
L
1 3 9 4 2 2 9 6 5 1 3
DSENSE
67
E
1SS367-T3SONY
IMD (ES)
SNSR_PCONT
BOARD
RV1001
(4/5)
20k
(Page 72)
SENSOR LEVEL
R1001
3.3k
F
G
R1028
33
68
CHK_HHOUT
R1033
CHK_DSENS
IMD (ES)
SIRCS
(Page 73)
H
BOARD
DBG_CNVSS
(5/5)
CHK_SW1
69
TSENSE4
TSENSE3
IMD (ES)
(Page 72)
TSENSE2
BOARD
(4/5)
TSENSE1
R1055
DRM-
I
R1057
70
LDM-
R1059
w w w
DRM+
R1061
IMD (ES)
LDM+
(Page 72)
R1063
BOARD
TBM-
R1070
(4/5)
TBM+
R1066
CEC_OUT
71
CEC_IN
J
IM_XRESET
IMD (ES)
(Page 73)
BOARD
(5/5)
BDP-CX7000ES
• See page 67 for waveforms. • See page 89 for IC Pin Function Description.
3
4
5
(1/5)
R1031
R1030
R1029
80
79
78
77
R1014
33
3.3
81
FL_XRESET
R1015
33
3.1
FL_XCS
82
R1016
33
3.3
FL_CLK
83
R1017
33
0
84
FL_DATA
CL1001
85
CL1002
86
3.3
87
JOG_B
R1002
10k
C1024
0.01
3.3
88
JOG_A
R1003
10k
C1025
0.01
3.3
89
KEY_3
R1004
10k
C1001
0.01
3.3
90
KEY_2
R1005
10k
C1002
0.01
3.3
91
KEY_1
R1006
10k
C1003
0.01
3.3
KEY_0
92
R1007
10k
C1004
0.01
1.4
BOARD REVISION
R1008 47k
93
0
94
DOOR_SW
R1009
10k
C1005
0.01
0.3
LOAD_SW
95
R1010
10k
C1006
0.01
AVSS
96
3.4
97
DSENSE
3.3
D1001
98
VREF
3.3
C1007
AVCC
R1023
99
0.01
33
3.3
SNSR_
100
PCONT
R1043
C1009
100k
10
16V
1
2
3
R1034
33
R1013
C1008
10
1
FB1001
33
33
33
33
33
33
x
a o
33
y
33
.
i
http://www.xiaoyu163.com
6
7
8
33
33
33
R1046
2.7k
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
IC1001
SYSTEM CONTROLLER
IC1001
R5F3640MDFAR
Q
Q
3
7
6
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
C1013
0.1
11
R1040
0
X1002
6MHz
u 1 6 3
69
69
2
4
8
9
9
9
10
11
JL3026
R1032
33
R1056
33
R1058
33
R1060
33
R1064
33
R1067
33
R1018
100k
53
52
51
R1072
33
2.9
IM_CS
50
R1073
33
3.2
IM_SCK
49
0.3
IM_SDI
48
0.1
R1075
33
IM_SDO
47
R1019
100k
0
46
R1077
33
R1020
100k
3.3
ATA_PCONT
45
3.3
R1078
33
R1021
100k
PCONT1
44
R1079
33
R1022
100k
3.1
PCONT2
43
R1080
33
R1025
100k
3.1
PCONT3
42
3.3
R1035
33
R1026
100k
CIS_PCONT
41
R1082
R1027
100k
3.3
33
PCONT4
40
R1083
33
R1036
100k
3.3
HDMI_PCONT
39
3.3
DBG_SW2
38
3.3
DBG_SW1
37
3.3
CIS_RXD
36
R1087
33
3.3
CIS_TXD
35
0
3
DBG_BUSY
1
34
5
1
5
0
8
9
0
DBG_SCLK
33
3.3
DBG_RXD
32
3.3
DBG_TXD
31
R1091
33
IC1003
RESET SIGNAL
R1096
GENERATOR
22k
C1019
C1014
C1016
100
0.1
0.1
6.3V
R1097
C1021
10k
0.01
R1039
R1012
100
10k
R1071
10k
C1010
0.22
Q1001
2SC3052EF-T1-LEF
R1093
3.3
RESET SWITCH
R1041
10k
47k
0
R1024
C1018
R1094
C1020
100k
0.01
0.01
22k
D1002
MA2J1110GLS0
IC1002
RESET SIGNAL
GENERATOR
m
IC1002
S-80929CNMC-G8ZT2G
3.3
c o
CD
1
OUT
5
3.3
2
VDD
S1001
3
VSS
NC
4
.
(RESET)
C1015
0.1
BDP-CX7000ES
2
8
9
9
12
13
14
(Page 71)
FAN1_CONT0
IMD (ES)
73
BOARD
FAN1_CONT1
(3/5)
FAN1_CONT2
IMD (ES)
START_BIT
74
(Page
BOARD
SYSCON_RST
(3/5)
PERI_PCONT
IMD (ES)
75
BOARD
(2/5)
ATA_PCONT
(Page 70)
CIS_PCONT
IMD (ES)
76
CIS_RXD
BOARD
(3/5)
CIS_TXD
(Page 71)
IM_CS
77
IMD (ES)
IM_SCK
BOARD
IM_SDI
(3/5)
IM_SDO
(Page 71)
PCONT3
78
IMD (ES)
BOARD
PCONT1
(2/5)
(Page 70)
PCONT2
79
PCONT3
IMD (ES)
PCONT4
BOARD
HDMI_PCONT
(3/5)
(Page 71)
DBG_SW1
80
DBG_SW2
2
4
9
8
2
9
9
DBG_BUSY
IMD (ES)
DBG_SCLK
BOARD
DBG_RXD
(5/5)
DBG_TXD
(Page 73)
UNSW12V
IC B/D
IC1003
S-80929CNMC-G8ZT2G
81
3.3
0
1
CD
5
OUT
3.9
2
VDD
IMD (ES)
NC
3
VSS
4
BOARD
C1023
(2/5)
4700p
(Page 70)
GND
UNSW3.3V
UNSW5.8V
IC1004
IC B/D
RESET SIGNAL
GENERATOR
IC1004
S-80929CNMC-G8ZT2G
3.3
0
1
OUT
CD
5
4
2
VDD
3
VSS
NC
4
C1022
4700p
IC B/D
0
C1017
0.022
71)

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents