Sony BDP-CX7000ES Service Manual page 108

BDP-CX7000ES
QQ
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Pin No. Pin Name
HDO[2], HDO[6],
L15 to L18
HDO[5], HDO[7]
M1 to M4 DT2[9] to DT2[6]
M5 IOVDD
M6 DVDD
M7 to M12 GND
M13 DVDD
M14 XTVDD
M15 XTVSS
M16 to HDO[3], HDO[1],
M18 HDO[4]
N1 to N4 DT2[5] to DT2[2]
N5 IOVDD
N6 GND
N7 DVDD
N8 to N10 GND
N11, N12 DVDD
N13 GND
N14 PVSSA
N15 GND
N16 ATEST1
N17 EXT_OUT
N18 HDO[0]
P1, P2 DT2[1], DT2[0]
P3 DT2_CK
P4 FD_SEl
P5 GND
TE
P6 to P10 MVDD
L 13942296513
P11 MDT[31]
P12, P13 MVDD
P14 GND
P15 PVDDA
P16 ATEST2
P17 XTAL1
P18 EXT_IN
R1 DT2_FD
R2 DT2_VS
R3 DT2_HS
MDT[8], MDT[9],
MDT[15], MDT[11],
R4 to R11
MDT[17], MDT[21],
MDT[25], MDT[30]
R12 DDRREF
R13 CS1Z
R14, R15 MAD[2], MAD[5]
R16 NCAL
R17 CKE
R18 XTAL2
MDT[0], MDT[2],
MDT[5], MDT[6],
MDT[10], MDT[13],
T1 to T11
MDT[16], MDT[18],
MDT[22], MDT[24],
MDT[29]
T12 CASZ
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T13 RASZ
T14 CS2Z
MAD[0], MAD[4],
T15 to T18
.
MAD[8], MAD[11]
U1, U2 MDT[1], MDT[3]
U3 GND
108
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I/O
O Digital video (Cb/Cr) signal output to the FPGA
I Digital video signal input terminal
- Power supply terminal (+3.3V)
- Power supply terminal (+1.2V)
- Ground terminal
- Power supply terminal (+1.2V)
- Power supply terminal (+3.3V)
- Ground terminal
O Digital video (Cb/Cr) signal output to the FPGA
I Digital video signal input terminal
- Power supply terminal (+3.3V)
- Ground terminal
- Power supply terminal (+1.2V)
- Ground terminal
- Power supply terminal (+1.2V)
- Ground terminal
- Ground terminal
- Ground terminal
- Test terminal
O External PLL signal output terminal
O Digital video (Cb/Cr) signal output to the FPGA
I Digital video signal input terminal
I Clock signal input terminal
I Field selection signal input terminal
- Ground terminal
- Power supply terminal (+2.5V)
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+2.5V)
- Ground terminal
- Power supply terminal (+3.3V)
- Test terminal
I System clock input terminal (20 MHz)
I External PLL signal input terminal
I Field ID signal input terminal
I Vertical sync signal input terminal
I Horizontal sync signal input terminal
I/O Two-way data bus with the SD-RAM
I Reference voltage (+1.25V) input terminal
O Chip select signal output to the SD-RAM
O Address signal output to the SD-RAM
I NMOS calibration terminal
O Clock enable signal output to the SD-RAM
O System clock output terminal (20 MHz)
I/O Two-way data bus with the SD-RAM
O Column address select signal output to the SD-RAM
O Row address select signal output to the SD-RAM
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O Chip select signal output to the SD-RAM
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O Address signal output to the SD-RAM
i
I/O Two-way data bus with the SD-RAM
- Ground terminal
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2 9
8
Description
Not used
Not used
Not used
Not used
No used
Not used
Q Q
3 6 7 1 3 1 5
Not used
No used
No used
No used
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.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9