Yamaha RX-V565 Service Manual page 117

A B C
DIGITAL 5/5
1
2
1.9
3.3
0
3
4
0
0
0.5
0
0
0.3
0
0.4
5
0
0.4
0
0
3.3
1.6
2.0
0
3.3
0.9
1.8
0
0.7
0.4
0
1.7
0
6
0.4
0.4
0
0
0
0
3.3
2.5
2.5
3.3
0
0
0
0
7
0
8
9
10
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
★ Components having special characteristics are marked
and must be replaced ●
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
● 本回路図は標準回路図です。改良のため予告なく変更することがございます。
D E F
Page 124 B3
to VIDEO (9)_CB391
( B, G, E, F models)
3.3
1.8
2.9
IC73 IC74
2.9
0
3.3
D
0
VIDEO DECODER & I/P
3.3
1.8
0
IC70
1.8
0
3.3
2.6
3.1
3.1
1.6 1.6
0
1.6
3.3
1.6
0.3
1.6
0
0
0
0
1.7
0
0
1.7
0
0
0
0
POINT D XL70 (Pin 81 of IC70)
印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
G H
Page 122 K9
to VIDEO (1)_CB305
IC72
2.6
3.1
3.3
1.8
0 0
1.7
SCALER
0
0
0
IC75
1.7
0
0
IC71
0
0
0
3.3
0
0
3.3
1.8
0
0.8
0
0
0
0
0
IC70: ADV7800BSTZ-80
10-bit, SDTV/HDTV 3D comb filter, video decoder and graphics digitizer
I J K
3.3
3.1
0
3.3
0
0
0
0.7
0 1.7
1.7 0
0 0
0 0.3
3.3
0 0.3
3.3 0.3
1.9 3.0
3.3 1.8 0.3
0 0.3
1.8
0 0.3
1.8
0 3.4
0
0
0
3.3 0.4 0
1.6 2.6 0.3
1.8
3.3 0
0
3.3
2.7
0 0.3
0 0.3
0 0.3
1.7 0.3
0 2.1
3.4 0
3.3
0
0 0.3
0 0.3
0 0.3
1.7 3.0
1.6 0.3
1.5 0.3
0.3
0.7
0 0.3
3.4 0
DDR/SDR-SDRAM INTERFACE
STANDARD DEFINITION PROCESSOR (SDP)
12 10 10
ANTIALIAS
CLAMP ADC DDR/SDR-SDRAM INTERFACE
FILTER
AIN1
TO 10 10
AIN12 ANTIALIAS 525p/625p MACROVISION STANDARD
CLAMP ADC 54
FILTER SUPPORT DETECTION AUTODECTION PIXEL DATA
CVBS
P0 TO P53
S-VIDEO
10 10
YPrPb ANTIALIAS
SCART- CLAMP ADC AV CODE
FILTER VERTICAL
(CBVS+RGB) 2D COMB
INSERTION
GRAPHICS RGB PEAKING
10 10
ANTIALIAS
CLAMP ADC
FILTER COLORSPACE
CONVERSION
FAST BLANK HORIZONTAL CS/HS
3D COMB PEAKING
OVETLAY
CONTROL
FB
VS
CTI
TBC FIELD/DE
LTI ITOP
CVBS OUT DAC
24
P30 TO P53
CORE
HS_IN2 SFL/SYNC_OUT
DIGITAL INPUT PORT CLK VBI DATA PROCESSOR (VDP)
VS_IN2
DVI OR HDMI COMPONENT PROCESSOR (CP)
CLK_IN
DE_IN
LLC
MACROVISION ACTIVE PEAK
SYNC PROCESSING AND
HS_IN DETECTION AND AGC
VS_IN CLOCK GENERATION
SOG
DIGITAL INT
SOY SSPD STDI COLORSPACE GAIN OFFSET AV CODE
FINE
CONVERSION CONTROL CONTROL INSERTION
CLAMP
SCLK
SCLK2
SERIAL INTERFACE
SDA
CONTROL AND VBI DATA
SDA2
ALSB
L M N
RX-V565/HTR-6250/AX-V565
IC76-78: SN74LVTH245APW
3.3 V ABT octal bus transceivers with 3-state outputs
DIR 1 20 Vcc
A1 2 19 OE
A2 3 18 B1
A3 4 17 B2
A4 5 16 B3
A5 6 15 B4
A6 7 14 B5
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
to DIGITAL 2/5
IC75: TC7WZ32FK (TE85L, F)
Dual 2-input OR gate
1A 1 8 Vcc
1B 2 7 1Y
2Y 3 6 2B
GND 4 5 2A
to DIGITAL 1/5 IC74: R1172H331D-T1-F
Voltage regulator
V DD 4 5 V OUT
Vref
Current Limit
CE 1 2 GND
Pin No. Symbol Description
1 CE Chip Enable Pin
2 GND Ground Pin
3 NC No Connection
4 V Input Pin
DD
5 V Output Pin of Voltage Regulator
OUT
IC73: R1172H181B-T1-F
Voltage regulator
V DD 4 5 V OUT
Vref
Current Limit
CE 1 2 GND
Pin No. Symbol Description
1 CE Chip Enable Pin
2 GND Ground Pin
3 NC No Connection
4 V DD Input Pin
5 V Output Pin of Voltage Regulator
OUT
IC71: ABT1012Q100
Advanced video processor device
ABT1012
Video Timing
27MHz
Generator
27MHz
150MHz
(optional) Video Clock Generation
output clock
Video Out Clk
HD Scaler 12
Sync Generator
Tri-Sync
Generator
Dynamic
Range
Expansion
12
12-bits in Y; 12 Scaler Bypass
12-bits in C
10
12
Video Input 12 Color Space
Conversion
CUE/
Sharpness/
12
YC Delay
Test Pattern
Generator
10
10
Picture Controls 3x3 Output
Matrix
3x3 Input matrix
Border Gen.
Masking Gen. 12
Panorama
12
Dynamic
Range
Input Format/ Compression
Color Space
Decoder 12
10-bits in Y; 10
10-bits in C
Input
Input Video 10 10
Bus
20 Mapping Output Output Video
Output Format
Bus
Converter Mapping
24
Processor
I2C Interface &
Control
Pin to Pin Bypass
Registers
117