Sharp MZ-80B Owner's Manual page 126

117
5.0 TIMING
5.1 OUTPUT MODE (MODE 0)
Figure 5.0-1 illustrates the timing associated with Mode 0 operation. An output cycle is always started by the
execution of an output instruction by the CPU. A WR *pulse is generated by the PIO during a CPU 1/0 write operation
and is used to latch the data from the CPU data bus into the addressed port's (A or B) output register. The rising edge
of the WR * pulse then raises the Ready flag after the next falling edge of <l > to indicate that data is available for the
peripheral device. In most systems the rising edge of the Ready signal can be used as a latching signal in the peripheral
device if desired . The Ready signal will remain active until :
(1)
a positive edge is received from the strobe line indicating
that the peripheral has taken the data, or (2) if already active, Ready will be forced low 1
~
<l > cycles after the leading
edge of IORQ if the port's output register is written into. Ready will return high on the first falling edge of <l > after the
trailing edge of IORQ. This guarantees that Ready is low when port data is changing. The Ready signal will not go
inactive until a falling edge occurs on the clock (<I>) line. The purpose of delaying the negative transition of the Ready
signal until after a negative clock transition is that it allows for a very simple generation scheme for the strobe pulse.
By merely connecting the Ready line to the Strobe line, a strobe with a duration of one clock period will be generated
with no other logic required. The positive edge of the strobe pulse automatically generates an INT request if the inter-
rupt enable flip flop has been set and this device is the highest priority device requesting an interrupt.
If the PIO is not in a reset state, the output register may be loaded before mode 0 is selected. This allows the port
output lines to become active in a user defined state .
WR
PORT OUTPUT
( S BITS)
---.J\..------,<'-----+---+-
FIGURE 5.0-1
READY
MODE 0 (OUTPUT) TIMING
INT
WR ~RD · CE·C / D · IORQ
5.2 INPUT MODE (MODE 1)
Figure 5.0-2 illustrates the timing of an input cycle. The peripheral initiates this cycle using the strobe line after
the CPU has performed a data read. A low level on this line loads data into the port input register and the rising edge of
the strobe line activates the interrupt request line (INT) if interrupt enable is set and this is the highest priority request-
ing device. The next falling edge of the clock line (<I>) will then reset the Ready line to an inactive state signifying
that the input register is full and further loading must be inhibited until the CPU reads the data. The CPU will, in the
course of its interrupt service routine, read the data from the interrupting port. When this occurs, the positive edge
of the CPU RD signal will raise the Ready line with the next low-going transition of <l>, indicating that new data can
be loaded into the PIO . If already active, Ready will be forced low one and one-half <l > periods following the leading
edge of IORQ during a read of a PIO port. If the user strobes data into the PIO only when Ready is high, the forced
state of Ready will prevent input register data from changing while the CPU is reading the PIO. Ready will go high again
after the trailing edge of the IORQ as previously described.
FIGURE 5.0-2
MODE 1 (INPUT) TIMING
RD ~ RD·CE · C / D · IORQ