Sharp MZ-80B Owner's Manual page 90

Any M Cycle
Bus Available States
BUSRQ
BUSAK
A0 - AI5
D0 - 07
MREQ .RD.
WR.IORQ.
RFSH
-
~
BUSRQ
Last T State
T x T x
~
~
~ ~
\
Sa~ple/
Sample---
\
- - -
r - - - - -
----
- - - - -
- - - -
- - - - -
Floating
BUS REQUEST/ACKNOWLEDGE CYCLE
FIGURE 3.0-4
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
Tx
T,
~ ~
I
r-------{
-----
,-{
r - - - - - K
81
Figure 3.0-5 illustrates the timing associated with an interrupt cycle. The interrupt signal (INT) is sampled by the
CPU with the rising edge of the last clock at the end of any instruction. The signal will not be accepted if the internal
CPU software controlled interrupt enable flip-flop is not set or if the BUSRQ signal is active. When the signal is
accepted a special Ml cycle is generated. During this special Ml cycle the IORQ signal becomes active (instead of the
normal MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. Notice that two wait
states are automatically added to this cycle . These states are added so that a ripple priority interrupt scheme can be
easily implemented. The two wait states allow sufficient time for the ripple signals to stabilize and identify which 1/0
device must insert the response vector. Refer to section 5.0 for details on how the interrupt response vector is utilized
by the CPU.
0
- - - '
--
-
AO - Al5
MREQ
IORQ
DATA BUS
--
WAIT
--
RD
L tMC I
as
yc e
of Ins true tion
Ml
Last T State T,
T 2
Tw
•
~
IL-----
~
IL----- ~
---:_1_
U"=----
- - - - - - - - - -
- - - - -
- - - ------ - - - - - ------
X
PC
\
\
- - - - - ----- - - - - - - - - - -
r - - - - - -
- - - - -
- - - - - - - - - - ------
- - - - -
INTERRUPT REQUEST/ACKNOWLEDGE CYCLE
FIGURE 3.0-5
Tw
*
T 3
~
~
- - - - -
- - - - -
- - - - - - - - - -
X
REFRESH
I
I
'iNh
L..:.:..:~
~___fC~
r------
- - - - -