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STA380BWTR
ST STA380BWTR Manuals
Manuals and User Guides for ST STA380BWTR. We have
1
ST STA380BWTR manual available for free PDF download: Manual
ST STA380BWTR Manual (162 pages)
Brand:
ST
| Category:
Stereo System
| Size: 5 MB
Table of Contents
Table 1. Device Summary
1
Table of Contents
2
Description
15
Block Diagram
16
Figure 1. Block Diagram
16
Pin Connections
17
Connection Diagram
17
Figure 2. Pin Connections VQFN48 (Top View)
17
Pin Description
18
Table 2. Pin List
18
Electrical Specifications
20
Absolute Maximum Ratings
20
Thermal Data
20
Table 3. Absolute Maximum Ratings
20
Table 4. Thermal Data
20
Recommended Operating Conditions
21
Electrical Specifications - Digital Section
21
Table 5. Recommended Operating Conditions
21
Table 6. Electrical Specifications - Digital Section
21
Electrical Specifications - Power Section
22
Table 7. Electrical Specifications - Power Section
22
Figure 3. Test Circuit
23
Power On/Off Sequence
24
Figure 4. Power-On Sequence
24
Figure 5. Power-Off Sequence for Pop-Free Turn-Off
24
Device Overview
25
Processing Data Path
25
Figure 6. Processing Path, First Part
25
Figure 7. Processing Path, Second Part: 2.1 Output with Individually Configurable Anticlipper/Drcs
26
Figure 9. Processing Path, Second Part: 2.1 Output Configuration with Stcompressor TM
27
Input Oversampling
28
Stcompressor TM
28
STC Block Diagram
29
Band Splitter
29
Figure 10. Stcompressor TM Block Diagram
29
Level Meter
30
Mapper
30
Table 8. Coefficients Extended-Range Configuration 0X74H
30
Figure 11. Band Splitter with 4Th Order Filtering
30
Figure 12. Stcompressor TM Behavior
31
Table 9. Compressor Ratio
32
Figure 13. Stcompressor TM Behavior as a Limiter
32
Attenuator
33
Dynamic Attack
33
Offset
34
Stereo Link
34
Figure 14. Offset Effect
34
Programming of Coefficients
35
Figure 15. Stereo Link Block Diagram
35
Table 10. Conversion Example
36
Memory Map
37
Table 11. STC Coefficients Memory Map
37
Table 12. STC Band Splitter Filters Memory Map
38
I 2 C Bus Specification
39
Communication Protocol
39
Data Transition or Change
39
Start Condition
39
Stop Condition
39
Data Input
39
Device Addressing
39
Write Operation
40
Byte Write
40
Multi-Byte Write
40
Read Operation
40
Current Address Byte Read
40
Current Address Multi-Byte Read
40
Random Address Byte Read
40
Random Address Multi-Byte Read
40
Write Mode Sequence
41
Read Mode Sequence
41
Figure 16. Write Mode Sequence
41
Figure 17. Read Mode Sequence
41
Register Description: New Map
42
Table 13. Default Register Map Table: NEW MAP
42
CLK Register (Addr 0X00)
45
STATUS Register (Addr 0X01)
45
Table 14. CLK Register
45
Table 15. STATUS Register
45
RESET Register (Addr 0X02)
46
Soft Volume Register (Addr 0X03)
46
Table 16. RESET Register
46
Table 17. Soft Volume Register
46
MVOL Register (Addr 0X04)
47
FINEVOL Register (Addr 0X05)
47
Table 18. Master Volume Register
47
Table 19. Fine Volume Register
47
CH1VOL Register (Addr 0X06)
48
CH2VOL Register (Addr 0X07)
48
Table 20. Channel 1 Volume Register
48
Table 22. Channel 2 Volume Register
48
POST Scaler Register (Addr 0X08)
49
OPER Register (Addr 0X09)
49
Table 23. OPER Register
49
Table 24. OPER Configuration Selection
49
Figure 18. OPER = 00 (Default Value)
50
Figure 19. OPER = 11
50
Figure 20. OPER = 10
50
Figure 21. OPER = 01
51
Figure 22. Output Mapping Scheme
51
Figure 23. 2.0 Channels (OPER = 00) PWM Slots
52
Figure 24. 2.1 Channels (OPER = 11) PWM Slots
53
Figure 25. 2.1 Channels (OPER = 10) PWM Slots
54
FUNCT Register (Addr 0X0A)
55
Dual-Band DRC
55
Table 25. FUNCT Register
55
Figure 26. B 2 DRC Scheme
55
Configuration Register a (Addr 0X11)
57
Master Clock Select
57
Table 26. Master Clock Select
57
Table 27. Input Sampling Rates
57
Interpolation Ratio Selection
58
Fault-Detect Recovery Bypass
58
Table 28. Internal Interpolation Ratio
58
Table 29. IR Bit Settings as a Function of the Input Sampling Rate
58
Table 30. Fault-Detect Recovery Bypass
58
Configuration Register B (Addr 0X12)
59
Serial Data Interface
59
Serial Data First Bit
59
Table 31. Serial Data First Bit
59
Table 32. Support Serial Audio Input Formats for MSB-First (SAIFB = 0)
59
Table 33. Supported Serial Audio Input Formats for LSB-First (SAIFB = 1)
60
Delay Serial Clock Enable
61
Channel Input Mapping
61
Configuration Register C (Addr 0X13)
61
FFX Compensating Pulse Size Register
61
Table 34. Delay Serial Clock Enable
61
Table 35. Channel Input Mapping
61
Table 36. FFX Compensating Pulse Size Bits
61
Configuration Register D (Addr 0X14)
62
DSP Bypass
62
Post-Scale Link
62
Biquad Coefficient Link
62
Table 37. Compensating Pulse Size
62
Table 38. DSP Bypass
62
Table 39. Post-Scale Link
62
Table 40. Biquad Coefficient Link
62
Zero-Detect Mute Enable
63
Submix Mode Enable
63
Configuration Register E (Addr 0X15)
63
Noise-Shaper Bandwidth Selection
63
AM Mode Enable
63
Table 41. Zero-Detect Mute Enable
63
Table 42. Submix Mode Enable
63
Table 43. Noise-Shaper Bandwidth Selection
63
Table 44. am Mode Enable
63
PWM Speed Mode
64
Zero-Crossing Enable
64
Configuration Register F (Addr 0X16)
64
Invalid Input Detect Mute Enable
64
Binary Output Mode Clock Loss Detection
64
Table 45. PWM Speed Mode
64
Table 46. Zero-Crossing Enable
64
Table 47. Invalid Input Detect Mute Enable
64
Table 48. Binary Output Mode Clock Loss Detection
64
LRCK Double Trigger Protection
65
Power-Down
65
External Amplifier Power-Down
65
Table 49. LRCK Double Trigger Protection
65
Table 50. IC Power-Down
65
Table 51. External Amplifier Power-Down
65
Volume Control Registers (Addr 0X17 - 0X1B)
66
Mute/Line Output Configuration Register (Addr 0X17)
66
Table 52. Line Output Configuration
66
Table 53. Mute Configuration
66
Channel 3 / Line Output Volume (Addr 0X1B)
67
Table 54. Channel 3 Volume as a Function of CH3VOL[7:0]
67
Audio Preset Registers (0X1D)
68
AM Interference Frequency Switching
68
Bass Management Crossover
68
Table 55. am Interference Frequency Switching Bits
68
Table 56. Audio Preset am Switching Frequency Selection
68
Table 57. Bass Management Crossover
68
Channel Configuration Registers (Addr 0X1F - 0X21)
69
Tone Control Bypass
69
Table 58. Bass Management Crossover Frequency
69
Table 59. Tone Control Bypass
69
EQ Bypass
70
Volume Bypass
70
Binary Output Enable Registers
70
Limiter Select
70
Table 60. EQ Bypass
70
Table 61. Volume Bypass Register
70
Table 62. Binary Output Enable Registers
70
Table 63. Channel Limiter Mapping as a Function of C3LS Bits
70
Output Mapping
71
Tone Control Register (Addr 0X22)
71
Tone Control
71
Table 64. Channel Output Mapping as a Function of C3OM Bits
71
Table 65. Tone Control Boost/Cut as a Function of BTC and TTC Bits
71
Dynamic Control Registers (Addr 0X23 - 0X26 / Addr 0X43 - 0X46)
72
Limiter 1 Attack/Release Rate (L1AR Addr 0X23)
72
Limiter 1 Attack/Release Threshold (L1ATRT Addr 0X24)
72
Limiter 2 Attack/Release Rate ( L2AR Addr 0X25)
72
Limiter 2 Attack/Release Threshold ( L2 ATRT Addr 0X26)
72
Table 66. Limiter Attack Rate as a Function of Lxa Bits
74
Table 67. Limiter Release Rate as a Function of Lxr Bits
74
Figure 27. Basic Limiter and Volume Flow Diagram
74
Table 68. Limiter Attack Threshold as a Function of Lxat Bits (AC Mode)
75
Table 69. Limiter Release Threshold as a Function of Lxrt Bits (AC Mode)
75
Limiter 1 Extended Attack Threshold (Addr 0X43)
76
Limiter 1 Extended Release Threshold (Addr 0X44)
76
Table 70. Limiter Attack Threshold as a Function of Lxat Bits (DRC Mode)
76
Table 71. Limiter Release Threshold as a Function of Lxrt Bits (DRC Mode)
76
Limiter 2 Extended Attack Threshold (Addr 0X45)
77
Limiter 2 Extended Release Threshold (Addr 0X46)
77
User-Defined Coefficient Control Registers (Addr 0X27 - 0X37)
77
Coefficient Address Register
77
Coefficient B1 Data Register Bits 23:16
77
Coefficient B1 Data Register Bits 15:8
77
Coefficient B1 Data Register Bits 7:0
77
Coefficient B2 Data Register Bits 23:16
78
Coefficient B2 Data Register Bits 15:8
78
Coefficient B2 Data Register Bits 7:0
78
Coefficient A1 Data Register Bits 23:16
78
Coefficient A1 Data Register Bits 15:8
78
Coefficient A1 Data Register Bits 7:0
78
Coefficient A2 Data Register Bits 23:16
78
Coefficient A2 Data Register Bits 15:8
79
Coefficient A2 Data Register Bits 7:0
79
Coefficient B0 Data Register Bits 23:16
79
Coefficient B0 Data Register Bits 15:8
79
Coefficient B0 Data Register Bits 7:0
79
Coefficient Write/Read Control Register
79
User-Defined EQ
82
Pre-Scale
82
Post-Scale
82
Table 72. RAM Block for Biquads, Mixing, Scaling and Bass Management
83
Fault-Detect Recovery Constant Registers (Addr 0X3C - 0X3D)
84
Extended Configuration Register (Addr 0X47)
84
Extended Post-Scale Range
84
Extended Attack Rate
84
Table 73. Extended Post-Scale Range
84
Table 74. Extended Attack Rate, Limiter 1
84
Extended Biquad Selector
85
Table 75. Extended Attack Rate, Limiter 2
85
Table 76. Extended Biquad Selector, Biquad 5
85
Table 77. Extended Biquad Selector, Biquad 6
85
Table 78. Extended Biquad Selector, Biquad 7
85
PLL Configuration Registers
86
0X56; 0X57)
86
Table 79. PLL Factors
86
Table 80. PLL Register 0X54 Bits
87
Table 81. PLL Register 0X55 Bits
87
Table 82. PLL Register 0X56 Bits
87
Short-Circuit Protection Mode Registers SHOK (Address 0X58)
88
Table 83. PLL Register 0X57 Bits
88
Extended Coefficient Range up to -4
89
Figure 28. Short-Circuit Detection Timing Diagram (no Short Detected)
89
Miscellaneous Registers (Address 0X5C, 0X5D)
90
Rate Power-Down Enable (RPDNEN) Bit
90
Bridge Immediately off (BRIDGOFF) Bit (Address 0X4B, Bit D5)
90
Table 84. Coefficients Extended Range Configuration
90
Channel PWM Enable (CPWMEN) Bit
91
External Amplifier Hardware Pin Enabler (LPDP, LPD LPDE) Bits
91
Power-Down Delay Selector (PNDLSL[2:0]) Bits
91
Table 85. External Amplifier Enabler Configuration Bits
91
Figure 29. Alternate Function for INTLINE Pin
91
Short-Circuit Check Enable Bit
92
Bad PWM Detection Registers (Address 0X5E, 0X5F, 0X60)
92
Table 86. PNDLSL Bits Configuration
92
Enhanced Zero-Detect Mute and Input Level Measurement
93
(Address 0X61-0X65, 0X3F, 0X40, 0X6F)
93
Table 87. Zero-Detect Threshold
93
Table 89. Manual Threshold Register 0X3F, 0X40 and 0X6F
94
Table 88. Zero-Detect Hysteresis
94
Stcompressor
95
Table 90. Register STCCFG0
95
Table 91. STCCFG0 Register
95
Table 92. Register STCCFG1
95
Table 93. STCCFG1 Register
95
Coefficient RAM CRC Protection (Address 0X71-0X7D)
96
MISC4 (Address 0X7E)
98
Table 94. Misc Register 4
98
Figure 30. Coefficients Direct Access Single-Write Operation
99
Figure 31. Coefficients Direct Access Multiple-Write Operation
99
Figure 32. Coefficients Direct Access Single-Read Operation
99
Register Description: Sound Terminal Compatibility
100
Table 95. I 2 C Registers Summary
101
Configuration Register a (Addr 0X00)
103
Master Clock Select
103
Table 96. Master Clock Select
103
Table 97. Input Sampling Rates
103
Interpolation Ratio Select
104
Fault-Detect Recovery Bypass
104
Table 98. Internal Interpolation Ratio
104
Table 99. IR Bit Settings as a Function of the Input Sampling Rate
104
Table 100. Fault-Detect Recovery Bypass
104
Configuration Register B (Addr 0X01)
105
Serial Data Interface
105
Serial Audio Input Interface Format
105
Serial Data First Bit
105
Table 101. Serial Audio Input Interface
105
Table 102. Serial Data First Bit
105
Table 103. Support Serial Audio Input Formats for MSB-First (SAIFB = 0)
106
Table 104. Supported Serial Audio Input Formats for LSB-First (SAIFB = 1)
107
Delay Serial Clock Enable
108
Channel Input Mapping
108
Table 105. Delay Serial Clock Enable
108
Table 106. Channel Input Mapping
108
Configuration Register C (Addr 0X02)
109
FFX Compensating Pulse Size Register
109
Configuration Register D (Addr 0X03)
109
DSP Bypass
109
Table 107. FFX Compensating Pulse Size Bits
109
Table 108. Compensating Pulse Size
109
Table 109. DSP Bypass
109
Post-Scale Link
110
Biquad Coefficient Link
110
Zero-Detect Mute Enable
110
Submix Mode Enable
110
Configuration Register E (Addr 0X04)
110
Table 110. Post-Scale Link
110
Table 111. Biquad Coefficient Link
110
Table 112. Zero-Detect Mute Enable
110
Table 113. Submix Mode Enable
110
Noise-Shaper Bandwidth Selection
111
AM Mode Enable
111
PWM Speed Mode
111
Zero-Crossing Enable
111
Soft Volume Update Enable
111
Table 114. Noise-Shaper Bandwidth Selection
111
Table 115. am Mode Enable
111
Table 116. PWM Speed Mode
111
Table 117. Zero-Crossing Enable
111
Table 118. Soft Volume Update Enable
111
Configuration Register F (Addr 0X05)
112
Output Configuration
112
Table 119. Output Configuration
112
Table 120. Output Configuration Engine Selection
112
Figure 33. OCFG = 00 (Default Value)
113
Figure 34. OCFG = 01
113
Figure 35. OCFG = 10
113
Figure 36. OCFG = 11
114
Figure 37. Output Mapping Scheme
114
Figure 38. 2.0 Channels (OCFG = 00) PWM Slots
115
Figure 39. 2.1 Channels (OCFG = 01) PWM Slots
116
Figure 40. 2.1 Channels (OCFG = 10) PWM Slots
117
Invalid Input Detect Mute Enable
118
Binary Output Mode Clock Loss Detection
118
LRCK Double Trigger Protection
118
IC Power-Down
118
External Amplifier Power-Down
118
Table 121. Invalid Input Detect Mute Enable
118
Table 122. Binary Output Mode Clock Loss Detection
118
Table 123. LRCK Double Trigger Protection
118
Table 124. IC Power-Down
118
Table 125. External Amplifier Power-Down
118
Volume Control Registers (Addr 0X06 - 0X0A)
119
Mute/Line Output Configuration Register
119
Table 126. Line Output Configuration
119
Table 127. Mute Configuration
119
Master Volume Register
120
Channel 1 Volume
120
Channel 2 Volume
120
Channel 3 / Line Output Volume
120
Table 128. Master Volume Offset as a Function of MVOL[7:0]
121
Table 129. Channel Volume as a Function of Cxvol[7:0]
121
Audio Preset Registers (Addr 0X0C)
122
Audio Preset Register (Addr 0X0C)
122
AM Interference Frequency Switching
122
Bass Management Crossover
122
Table 130. am Interference Frequency Switching Bits
122
Table 131. Audio Preset am Switching Frequency Selection
122
Table 132. Bass Management Crossover
122
Channel Configuration Registers (Addr 0X0E - 0X10)
123
Tone Control Bypass
123
Table 133. Bass Management Crossover Frequency
123
Table 134. Tone Control Bypass
123
EQ Bypass
124
Volume Bypass
124
Binary Output Enable Registers
124
Limiter Select
124
Table 135. EQ Bypass
124
Table 136. Volume Bypass Register
124
Table 137. Binary Output Enable Registers
124
Table 138. Channel Limiter Mapping as a Function of Cxls Bits
124
Output Mapping
125
Tone Control Register (Addr 0X11)
125
Tone Control
125
Table 139. Channel Output Mapping as a Function of Cxom Bits
125
Table 140. Tone Control Boost/Cut as a Function of BTC and TTC Bits
125
Dynamic Control Registers (Addr 0X12 - 0X15)
126
Limiter 1 Attack/Release Rate
126
Limiter 1 Attack/Release Threshold
126
Limiter 2 Attack/Release Rate
126
Limiter 2 Attack/Release Threshold
126
Table 141. Limiter Attack Rate as a Function of Lxa Bits
128
Table 142. Limiter Release Rate as a Function of Lxr Bits
128
Figure 41. Basic Limiter and Volume Flow Diagram
128
Table 143. Limiter Attack Threshold as a Function of Lxat Bits (AC Mode)
129
Table 144. Limiter Release Threshold as a Function of Lxrt Bits (AC Mode)
129
Limiter 1 Extended Attack Threshold (Addr 0X32)
130
Limiter 1 Extended Release Threshold (Addr 0X33)
130
Table 145. Limiter Attack Threshold as a Function of Lxat Bits (DRC Mode)
130
Table 146. Limiter Release Threshold as a Function of Lxrt Bits (DRC Mode)
130
Limiter 2 Extended Attack Threshold (Addr 0X34
131
Limiter 2 Extended Release Threshold (Addr 0X35)
131
User-Defined Coefficient Control Registers (Addr 0X16 - 0X26)
131
Coefficient Address Register
131
Coefficient B1 Data Register Bits 23:16
131
Coefficient B1 Data Register Bits 15:8
131
Coefficient B1 Data Register Bits 7:0
132
Coefficient B2 Data Register Bits 23:16
132
Coefficient B2 Data Register Bits 15:8
132
Coefficient B2 Data Register Bits 7:0
132
Coefficient A1 Data Register Bits 23:16
132
Coefficient A1 Data Register Bits 15:8
132
Coefficient A1 Data Register Bits 7:0
132
Coefficient A2 Data Register Bits 23:16
132
Coefficient A2 Data Register Bits 15:8
133
Coefficient A2 Data Register Bits 7:0
133
Coefficient B0 Data Register Bits 23:16
133
Coefficient B0 Data Register Bits 15:8
133
Coefficient B0 Data Register Bits 7:0
133
Coefficient Write/Read Control Register
133
User-Defined EQ
136
Pre-Scale
136
Post-Scale
136
Table 147. RAM Block for Biquads, Mixing, Scaling and Bass Management
137
Fault-Detect Recovery Constant Registers (Addr 0X2B - 0X2C)
138
Device Status Register (Addr 0X2D)
138
EQ Coefficients Configuration Register (Addr 0X31)
138
Table 148. Status Register Bits
138
Extended Configuration Register (Addr 0X36)
139
Dual-Band DRC
139
Figure 42. B 2 DRC Scheme
139
Extended Post-Scale Range
140
Table 149. Extended Post-Scale Range
140
Extended Attack Rate
141
Extended BIQUAD Selector
141
Table 150. Extended Attack Rate, Limiter 1
141
Table 151. Extended Attack Rate, Limiter 2
141
Table 152. Extended Biquad Selector, Biquad 5
141
Table 153. Extended Biquad Selector, Biquad 6
141
Table 154. Extended Biquad Selector, Biquad 7
141
EQ Soft Volume Configuration Registers (Addr 0X37 - 0X38)
142
Table 155. Soft Volume Update Enable, Increase
142
Table 156. Soft Volume Update Enable, Decrease
142
Extra Volume Resolution Configuration Registers (Address 0X3F; 0X40)
143
Table 157. Volume Fine-Tuning Steps
143
Figure 43. Extra Resolution Volume Scheme
143
PLL Configuration Registers
144
0X44; 0X45; 0X46)
144
Table 158. Extra Volume Resolution Enable
144
Table 159. PLL Factors
145
Table 160. PLL Register 0X43 Bits
145
Table 161. PLL Register 0X44 Bits
145
Short-Circuit Protection Mode Registers SHOK (Address 0X47)
146
Table 162. PLL Register 0X45 Bits
146
Table 163. PLL Register 0X46 Bits
146
Figure 44. Short-Circuit Detection Timing Diagram (no Short Detected)
147
Extended Coefficient Range up to -4
148
Miscellaneous Registers (Address 0X4B, 0X4C)
148
Rate Power-Down Enable (RPDNEN) Bit (Address 0X4B, Bit D7)
148
Table 164. Coefficients Extended Range Configuration
148
Bridge Immediately off (BRIDGOFF) Bit (Address 0X4B, Bit D5)
149
Channel PWM Enable (CPWMEN) Bit (Address 0X4B, Bit D2)
149
External Amplifier Hardware Pin Enabler (LPDP, LPD LPDE) Bits (Address 0X4C, Bit D7, D6, D5)
149
Table 165. External Amplifier Enabler Configuration Bits
149
Power-Down Delay Selector (PNDLSL[2:0]) Bits (Address 0X4C, Bit D4, D3, D2)
150
Short-Circuit Check Enable Bit (Address 0X4C, Bit D0)
150
Table 166. PNDLSL Bits Configuration
150
Figure 45. Alternate Function for INTLINE Pin
150
Bad PWM Detection Registers (Address 0X4D, 0X4E, 0X4F)
151
Enhanced Zero-Detect Mute and Input Level Measurement (Address 0X50-0X54, 0X2E, 0X2F and 0X5E)
152
Table 167. Zero-Detect Threshold
152
Table 169. Manual Threshold Register 0X2E, 0X2F and 0X5E
153
Table 168. Zero-Detect Hysteresis
153
Stcompressor
154
Table 170. Stcompressor TM Configuration Bits1
154
Table 171. Stcompressor TM Configuration Bits 2
154
Coefficient RAM CRC Protection (Address 0X60-0X6C)
155
MISC3 (Address 0X6E)
157
MISC4 (Address 0X7E)
157
Table 172. Misc Register 3
157
Table 173. MISC4
157
Applications
158
Typical Output Configuration
158
Figure 46. Output Configuration for Stereo BTL Mode in Filterlight Configuration
158
Package Information
159
Figure 47. VQFN48 (7 X 7 X 0.9 MM) Package Outline
159
Table 174. VQFN48 (7 X 7 X 0.9 MM) Package Dimensions
160
Revision History
161
Table 175. Document Revision History
161
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