ST STA380BW Manual
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ST STA380BW Manual

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VQFN48 (7 x 7 mm)
Features
 Wide-range supply voltage
– 4.5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
2
 I
C control with selectable device address
 Embedded full IC protection
– Manufacturing short-circuit protection (out
vs. gnd, out vs. vcc, out vs. out)
– Thermal protection
– Overcurrent protection
– Undervoltage protection
2
 I
S interface, sampling rate 32 kHz ~ 192 kHz,
with internal sampling frequency converter for
fixed processing frequency
 Three output power stage configurations
– 2.0 mode, L/R full bridges
– 2.1 mode, L/R two half-bridges, subwoofer
full bridge
– 2.1 mode, L/R full bridges, PWM output for
external subwoofer amplifier
 Driving load capabilities
– 2 x 20 W into 8  ternary modulation
– 2 x 9 W into 4 + 1 x 20 W into 8 
TM
 FFX
100 dB dynamic range
 Fixed output PWM frequency at any input
sampling frequency
 Embedded RMS meter for measuring real-time
loudness
 New fully programmable noise-gating function
April 2013
This is information on a product in full production.
2.1-channel high-efficiency digital audio system
DocID024543 Rev 1
 Up to 12 user-programmable biquads with
noise-shaping technology
 Direct access to coefficients through I
shadowing mechanism
 Fixed (88.2 kHz / 96 kHz) internal processing
sampling rate
 Two independent DRCs configurable as a
dual-band anticlipper or independent
limiters/compressors (B
 Digital gain/att +48 dB to -80 dB with
0.125 dB/step resolution
 Independent (fade-in, fade-out) soft volume
update with programmable rate 48 ~ 1.5 dB/ms
 Bass/treble tones control
 Audio presets: 15 crossover filters,
5 anticlipping modes, nighttime listening mode
TM
 STSpeakerSafe
– Pre
and post
processing DC blocking
-
-
filters
– Checksum engine for filter coefficients
– PWM fault self-diagnosis
TM
 STCompressor
dual-band DRC

Table 1. Device summary

Order code
Package
STA380BW
VQFN48
STA380BWTR
VQFN48
STA380BW
Sound Terminal
-
Datasheet
production data
2
C
2
DRC)
protection circuitry
Packing
Tray
Tape and Reel
www.st.com
®
1/162
162

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Summary of Contents for ST STA380BW

  • Page 1: Table 1. Device Summary

    STA380BW ® Sound Terminal 2.1-channel high-efficiency digital audio system Datasheet production data  Up to 12 user-programmable biquads with noise-shaping technology  Direct access to coefficients through I shadowing mechanism  Fixed (88.2 kHz / 96 kHz) internal processing VQFN48 (7 x 7 mm) sampling rate ...

  • Page 2: Table Of Contents

    Contents STA380BW Contents Description ..........15 Block diagram .
  • Page 3 STA380BW Contents 5.1.2 Start condition ..........39 5.1.3...
  • Page 4 Contents STA380BW 6.13.3 Delay serial clock enable ........61 6.13.4...
  • Page 5 STA380BW Contents 6.22 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46) ..72 6.22.1 Limiter 1 attack/release rate (L1AR addr 0x23) ....72 6.22.2...
  • Page 6 Contents STA380BW 6.27 Short-circuit protection mode registers SHOK (address 0x58) ..88 6.28 Extended coefficient range up to -4...4 (address 0x5A) ....89 6.29...
  • Page 7 STA380BW Contents 7.5.1 Noise-shaper bandwidth selection ......111 7.5.2 AM mode enable ......... 111 7.5.3...
  • Page 8 Contents STA380BW 7.11.5 Limiter 1 extended attack threshold (addr 0x32) ....130 7.11.6 Limiter 1 extended release threshold (addr 0x33) ....130 7.11.7...
  • Page 9 STA380BW Contents 7.19 PLL configuration registers (address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) ......... 144 7.20...
  • Page 10 List of tables STA380BW List of tables Table 1. Device summary ............1 Table 2.
  • Page 11 STA380BW List of tables Table 50. IC power-down ............65 Table 51.
  • Page 12 List of tables STA380BW Table 102. Serial data first bit ............105 Table 103.
  • Page 13 STA380BW List of tables Table 154. Extended biquad selector, biquad 7 ......... 141 Table 155.
  • Page 14 List of figures STA380BW List of figures Figure 1. Block diagram ............16 Figure 2.

  • Page 15: Description

    SW channel can also be driven through the PWM output. The STA380BW is able to deliver 2 x 20 W (ternary) into an 8  load at 18 V or 2 x 9 W (binary) into a 4  load, plus 1 x 20 W (ternary) into an 8  load at 18 V.

  • Page 16: Block Diagram

    Description STA380BW Block diagram Figure 1. Block diagram STA380BW 16/162 DocID024543 Rev 1...

  • Page 17: Pin Connections

    STA380BW Pin connections Pin connections Connection diagram Figure 2. Pin connections VQFN48 (top view) VCC_REG MCLK VSS_REG AGND_PLL OUT2B VREG_FILT GND2 TWARN/FFX4A VCC2 EAPD/FFX4B OUT2A FFX3B STA380BW OUT1B FFX3A VCC1 GND_DIG1 GND1 VDD_DIG1 OUT1A VDD_REG N.C. GND_REG DocID024543 Rev 1...

  • Page 18: Pin Description

    Pin connections STA380BW Pin description Table 2. Pin list VQFN 48-pin Name Type Description VCC_REG POWER VCC reg VSS_REG POWER Vss reg, VCC_REG-3.3 V OUT2B OUTPUT Half-bridge 2B output GND2 POWER Half-bridge 2A and 2B ground VCC2 POWER Half-bridge 2A and 2B supply...
  • Page 19 STA380BW Pin connections Table 2. Pin list (continued) VQFN 48-pin Name Type Description TEST_MODE INPUT This pin must be connected to ground (pull-down) GNDDIG2 POWER Digital I/O ground VDDDIG2 POWER Digital core LDO supply 16, 17, 20, 22, 25, 27...

  • Page 20: Electrical Specifications

    Electrical specifications STA380BW Electrical specifications Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Unit Power supply voltage (VCCxA, VCCxB) -0.3 31.5 VDD_DIG Digital supply voltage -0.3 Operating junction temperature °C Tstg Storage temperature °C Warning: Stresses beyond those listed in...

  • Page 21: Recommended Operating Conditions

    STA380BW Electrical specifications Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Unit Power supply voltage (VCCxA, VCCxB) VDD_DIG Digital supply voltage Tamb Ambient temperature °C Electrical specifications - digital section The specifications given in this section are valid for the operating conditions: VDD_DIG = 3.3 V, T...

  • Page 22: Electrical Specifications - Power Section

    Electrical specifications STA380BW Electrical specifications - power section The specifications given in this section are valid for the operating conditions: V = 24 V, = 8 , unless otherwise specified. f = 1 kHz, f = 384 kHz, T = 25° C and R Table 7.

  • Page 23: Figure 3. Test Circuit

    STA380BW Electrical specifications Figure 3. Test circuit DocID024543 Rev 1 23/162...

  • Page 24: Power On/Off Sequence

    Electrical specifications STA380BW Power on/off sequence Figure 4. Power-on sequence Note: no specific VCC and − VDD_DIG turn on sequence is required Don’t care Don’t care VDD_DIG XTI or BICKI Don’t care Don’t care Don’t care Don’t care Don’t care HW RESET Don’t care...

  • Page 25: Device Overview

    Section 6: Register description: New Map. Processing data path The whole STA380BW processing chain is composed of two consecutive sections. In the first one dual-channel processing is implemented (Figure 6) and then each channel is fed into the post-mixing block allowing to generate either a third channel (typically used in 2.1 output configurations together with crossover filters) or to have the channels processed by the dual-band DRC block (2.0 output configuration with crossover filters used to define the...

  • Page 26: Figure 7. Processing Path, Second Part: 2.1 Output With Individually Configurable Anticlipper/Drcs

    C1Mx1 Ch an n el ½ Biq uad #8 An ti-clipper Ch an n el 1 DC Cut -------------- Po st Scale Vo lume Filter Hi-p ass XO Filter C1Mx2 C2Mx1 Ch an n el ½ Biq uad #8...

  • Page 27: Figure 9. Processing Path, Second Part: 2.1 Output Configuration With Stcompressor Tm

    (User Defined If XO=0000)  2.1 output with STCompressor (Figure 9): the STA380BW embeds the latest, state- of-the-art multi-band dynamic, range compressor, called STCompressor . When using this configuration, up to 10 biquad filters are available for dedicated processing. Please refer to Section 4.3: STCompressor...

  • Page 28: Input Oversampling

    Device overview STA380BW Input oversampling Figure 6 shows the input oversampling block in front of the main processing. When 32 kHz Fs is used, the default x2 oversampling ratio can be increased to a x3. Activating this feature, it is possible to have a 384 kHz PWM switching frequency (instead of the default 256 kHz) when 32 kHz Fs is used.

  • Page 29: Stc Block Diagram

    STA380BW Device overview 4.3.1 STC block diagram Figure 10. STCompressor block diagram DRC 0 O ffset Ban d 0 (Lo w freq s) Level Map p er Atten uato r Meter O utp ut In p ut Ch 0 Ch 0...

  • Page 30: Level Meter

    Device overview STA380BW The band splitter filter coefficients have a user-selectable range [-1, 1), [-2, 2) and [-4, 4). The RAM coefficient 0x7 is responsible for these settings according to Table 8. The range default value is [-4, 4). Table 8. Coefficients extended-range configuration 0x74h...

  • Page 31: Figure 12. Stcompressor Tm Behavior

    STA380BW Device overview The STC reacts differently depending on these three parameters (Figure 12):  level meter output value < compressor threshold < limiter threshold: under these circumstances the signal level is small enough to not require any type of limiting/compressing action.

  • Page 32: Table 9. Compressor Ratio

    Device overview STA380BW Figure 13. STCompressor behavior as a limiter Linear Zone Limiting Zone L.T. L.T. [dB] INPUT Table 9. Compressor ratio Compressor ratio Ratio value 1:1.25 1:1.5 1:1.75 1:2.5 1:3.5 1:4.5 1:5.5 1:16 32/162 DocID024543 Rev 1...

  • Page 33: Attenuator

    STA380BW Device overview 4.3.5 Attenuator The attenuation is characterized by two different phases: attack and release. Given an input signal above the limiter threshold, during the attack phase the STC decreases the gain in order to reach the output level determined by the mapper. In this...

  • Page 34: Offset

    Device overview STA380BW 4.3.7 Offset The offset is a user-selectable gain or volume control. When using the STC it is advised to use the offset to tune the output volume instead of the regular volume controls. The offset is located before the attenuator block, ensuring that the output power limit (limiter threshold) is...

  • Page 35: Programming Of Coefficients

    STA380BW Device overview Figure 15. Stereo link block diagram Ch 0 – Band 0 From mapper Attenuator Attenuator Ch 0 – Band 0 Output Attenuation Ch 0 Band 0 From mapper Attenuator Attenuator Ch 0 – Band 1 Ch 0 – Band 1 Ch 1 –...

  • Page 36: Table 10. Conversion Example

    Device overview STA380BW Table 10. Conversion example Original value (dec) C value (hex) +48.00 0x600000 +24.00 0x300000 +16.00 0x200000 +12.00 0x180000 +06.00 0x0C0000 +02.00 0x040000 +01.00 0x020000 -01.00 0xFE0000 -02.00 0xFC0000 -06.00 0xF40000 -12.00 0xE80000 -24.00 0xD00000 -48.00 0xA00000 36/162...

  • Page 37: Memory Map

    STA380BW Device overview 4.3.10 Memory map All the control parameters listed in the previous paragraphs are stored in the internal device memory. Please refer to Table 11 Table 12 for a complete list of their addresses. For the programming procedure please refer to Section 6.23: User-defined coefficient...

  • Page 38: Table 12. Stc Band Splitter Filters Memory Map

    Device overview STA380BW Table 12. STC band splitter filters memory map Function Address Coefficient Range Default 0x40 B1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000 0x41 [-1, 1), [-2, 2), [-4, 4) 0x000000 0x42 -A1/2 [-1, 1), [-2, 2), [-4, 4)

  • Page 39: I 2 C Bus Specification

    SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1. The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and to 0 for write mode. After a START condition the STA380BW identifies on the bus the DocID024543 Rev 1...

  • Page 40: Write Operation

    Following the START condition, the master sends a device select code with the RW bit set to 0. The STA380BW acknowledges this and then waits for the byte of the internal address. After receiving the internal byte address the STA380BW again responds with an acknowledgement.

  • Page 41: Write Mode Sequence

    STA380BW C bus specification 5.4.5 Write mode sequence Figure 16. Write mode sequence BYTE BYTE DEV-ADDR DEV-ADDR SUB-ADDR SUB-ADDR DATA IN DATA IN WRITE WRITE START START STOP STOP MULTIBYTE MULTIBYTE DEV-ADDR DEV-ADDR SUB-ADDR SUB-ADDR DATA IN DATA IN DATA IN...

  • Page 42: Register Description: New Map

    STA380BW Register description: New Map Mapping of two registers is available on the STA380BW, the selection is done by setting register 0x7E bit D7. By default, 0x7E is set to 1 and refers to a map that is not compatible with previous Sound Terminal devices.
  • Page 43 STA380BW Register description: New Map Table 13. Default register map table: NEW MAP (continued) Addr Name 0x24 L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0 0x25 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0 0x26 L2ATRT L2AT3 L2AT2...
  • Page 44 Register description: New Map STA380BW Table 13. Default register map table: NEW MAP (continued) Addr Name 0x57 PLLSTATE PDSTATE OSCOK LOWCK BYPSTATE 0x58 SHOK GNDSH VCCSH OUTSH 0x5A CXT41 CEXT_B4[1:0] CEXT_B3[1:0] CEXT_B2[1:0] CEXT_B1[1:0] 0x5B CXT75 CEXT_B7[1:0] CEXT_B6[1:0] CEXT_B5[1:0] 0x5C MISC1...

  • Page 45: Clk Register (Addr 0X00)

    STA380BW Register description: New Map CLK register (addr 0x00) CLK_CFG[3:0] Reserved Reserved Reserved Table 14. CLK register Name Description 0000: 44.1/48 kHz BITCLK = 64 Fs 0001: 32 kHz BITCLK = 64 Fs CLK_CFG[3:0] 0010: 96 kHz BITCLK = 64 Fs 0011: 48/44.1/32 kHz MCK = 256 Fs...

  • Page 46: Reset Register (Addr 0X02)

    Register description: New Map STA380BW RESET register (addr 0x02) Reserved Reserved Reserved Reserved Reserved Reserved Reserved SRESET Table 16. RESET register Name Description ‘0’: normal operation SRESET ‘1’: reset the device After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit D7) is set to 1 instead of the 0 default value obtained after hardware reset.

  • Page 47: Mvol Register (Addr 0X04)

    STA380BW Register description: New Map MVOL register (addr 0x04) MVOL[7:0] Table 18. Master volume register Name Description 0x00: Hard mute (immediate switchoff) 0x01: Mute MVOL[7:0] 0x02: Mute (PWM on) 0x03: Mute (PWM on) others: volume = [(MVOL-255)/2] dB 1. If the volume is below -60 dB, the level will be approximated to 1 dB step.

  • Page 48: Ch1Vol Register (Addr 0X06)

    Register description: New Map STA380BW CH1VOL register (addr 0x06) CH1VOL[7:0] Table 20. Channel 1 volume register Table 21: Name Description 0x00: mute CH1VOL[7:0] others: volume = [(CH1VOL-159)/2] dB 1. If the volume is below -60 dB, the level will be approximated to 1 dB step.

  • Page 49: Post Scaler Register (Addr 0X08)

    STA380BW Register description: New Map POST scaler register (addr 0x08) POST[7:0] Post scaler is set to POST/128 for both CH1 and CH2. 6.10 OPER register (addr 0x09) Reserved Reserved Reserved Reserved Reserved Reserved OPER[1:0] Table 23. OPER register Name Description...

  • Page 50: Figure 18. Oper = 00 (Default Value)

    Register description: New Map STA380BW Figure 18. OPER = 00 (default value) OUT1A OUT1A Half Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A Half Half Bridge Bridge Channel 2 Channel 2 Half Half...

  • Page 51: Figure 21. Oper = 01

    OUT4B OUT4B The STA380BW can be configured to support different output configurations. For each PWM output channel, a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.

  • Page 52: Figure 23. 2.0 Channels (Oper = 00) Pwm Slots

    Register description: New Map STA380BW For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage. 2.0 channels, two full-bridges ( = 00) OPER  FFX1A -> OUT1A  FFX1B -> OUT1B ...

  • Page 53: Figure 24. 2.1 Channels (Oper = 11) Pwm Slots

    STA380BW Register description: New Map 2.1 channels, two half-bridges + one full-bridge ( = 11) OPER  FFX1A -> OUT1A  FFX2A -> OUT1B  FFX3A -> OUT2A  FFX3B -> OUT2B  FFX1A -> OUT3A  FFX1B -> OUT3B ...

  • Page 54: Figure 25. 2.1 Channels (Oper = 10) Pwm Slots

    Register description: New Map STA380BW 2.1 channels, two full-bridges + one external full-bridge ( = 10) OPER  FFX1A -> OUT1A  FFX1B -> OUT1B  FFX2A -> OUT2A  FFX2B -> OUT2B  FFX3A -> OUT3A  FFX3B -> OUT3B ...

  • Page 55: Funct Register (Addr 0X0A)

    ‘0’: DRC disabled ‘1’: DRC enabled 6.11.1 Dual-band DRC The STA380BW device provides a dual-band DRC (B DRC) on the left and right channels data path, as depicted in Figure 26. Dual-band DRC is activated by setting MDRCE = 1.
  • Page 56 Register description: New Map STA380BW with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the left/right high-frequency components, while limiter 2 (DRC2) is used to control the low-frequency components (see Section 6.22: Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46)).

  • Page 57: Configuration Register A (Addr 0X11)

    S sampling MCS1 frequency and the input clock. MCS2 The STA380BW supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is:  32.768 MHz for 32 kHz ...

  • Page 58: Interpolation Ratio Selection

    FDRB 1: fault-detect recovery disabled The on-chip STA380BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block...

  • Page 59: Configuration Register B (Addr 0X12)

    The STA380BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA380BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.

  • Page 60: Table 33. Supported Serial Audio Input Formats For Lsb-First (Saifb = 1)

    Right-justified 18-bit data 1110 Right-justified 16-bit data To make the STA380BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that:  the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on...

  • Page 61: Delay Serial Clock Enable

    STA380BW Register description: New Map happens. At the same time any processing related to the I C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again. Note: Any mute or volume change causes some delay in the completion of the I C operation due to the soft volume feature.

  • Page 62: Configuration Register D (Addr 0X14)

    Table 38. DSP bypass Name Description 0: Normal operation DSPB 1: Bypass of biquad and bass/treble functions Setting the DSPB bit bypasses the EQ function of the STA380BW. 6.15.2 Post-scale link Table 39. Post-scale link Name Description 0: Each channel uses individual post-scale values 1: Each channel uses channel 1 post-scale values Post-scale functionality can be used for power-supply error correction.

  • Page 63: Zero-Detect Mute Enable

    0: Normal FFX operation 1: AM reduction mode FFX operation The STA380BW features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner.

  • Page 64: Pwm Speed Mode

    Register description: New Map STA380BW 6.16.3 PWM speed mode Table 45. PWM speed mode Name Description 0: Normal speed (384 kHz) all channels PWMS 1: Odd speed (341.3 kHz) all channels. Not suitable for binary BTL mode. 6.16.4 Zero-crossing enable Table 46.

  • Page 65: Lrck Double Trigger Protection

    STA380BW Register description: New Map 6.17.3 LRCK double trigger protection Table 49. LRCK double trigger protection Name Description LDTE LRCLK double trigger protection enable This bit actively prevents double triggering of LRCLK. 6.17.4 Power-down Table 50. IC power-down Name Description...

  • Page 66: Volume Control Registers (Addr 0X17 - 0X1B)

    Register description: New Map STA380BW 6.18 Volume control registers (addr 0x17 - 0x1B) 6.18.1 Mute/line output configuration register (addr 0x17) LOC1 LOC0 Reserved Reserved MMUTE Table 52. Line output configuration LOC[1:0] Line output configuration Line output fixed - no volume, no EQ...

  • Page 67: Channel 3 / Line Output Volume (Addr 0X1B)

    Channel 3 / line output volume (addr 0x1B) CH3VOL The volume structure of the STA380BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB.

  • Page 68: Audio Preset Registers (0X1D)

    Register description: New Map STA380BW 6.19 Audio preset registers (0x1D) AMAM2 AMAM1 AMAM0 AMAME 6.19.1 AM interference frequency switching Table 55. AM interference frequency switching bits Name Description Audio preset AM enable AMAME 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings Table 56.

  • Page 69: Channel Configuration Registers (Addr 0X1F - 0X21)

    STA380BW Register description: New Map Table 58. Bass management crossover frequency XO[3:0] Crossover frequency Table 73.: RAM block for biquads, mixing, scaling and bass 0000 management 0001 80 Hz 0010 100 Hz 0011 120 Hz 0100 140 Hz 0101 160 Hz...

  • Page 70: Eq Bypass

    Register description: New Map STA380BW 6.20.2 EQ bypass EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel.

  • Page 71: Output Mapping

    STA380BW Register description: New Map 6.20.6 Output mapping Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.

  • Page 72: Dynamic Control Registers (Addr 0X23 - 0X26 / Addr 0X43 - 0X46)

    FFX amplifier. Since gain can be added digitally within the STA380BW it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter.
  • Page 73 STA380BW Register description: New Map ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register.

  • Page 74: Table 66. Limiter Attack Rate As A Function Of Lxa Bits

    Register description: New Map STA380BW Figure 27. Basic limiter and volume flow diagram Limiter Gain / Vo lume In p ut Outp ut Gain Atten uatio n Saturatio n Table 66. Limiter attack rate as a Table 67. Limiter release rate as a...

  • Page 75: Table 68. Limiter Attack Threshold As A Function Of Lxat Bits (Ac Mode)

    STA380BW Register description: New Map Anticlipping mode Table 68. Limiter attack threshold as a Table 69. Limiter release threshold as a function of LxAT bits (AC mode) function of LxRT bits (AC mode) LxAT[3:0] AC (dB relative to fs) LxRT[3:0]...

  • Page 76: Limiter 1 Extended Attack Threshold (Addr 0X43)

    Register description: New Map STA380BW Dynamic range compression mode Table 70. Limiter attack threshold as Table 71. Limiter release threshold as a function of LxAT bits (DRC mode) a function of LxRT bits (DRC mode) DRC (dB relative to volume +...

  • Page 77: Limiter 2 Extended Attack Threshold (Addr 0X45)

    STA380BW Register description: New Map 6.22.7 Limiter 2 extended attack threshold (addr 0x45) EATHEN2 EATH2[6] EATH2[5] EATH2[4] EATH2[3] EATH2[2] EATH2[1] EATH2[0] The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4 To enable this feature, the EATHEN2 bit must be set to 1.

  • Page 78: Coefficient B2 Data Register Bits 23:16

    Register description: New Map STA380BW 6.23.5 Coefficient b2 data register bits 23:16 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 6.23.6 Coefficient b2 data register bits 15:8 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 6.23.7 Coefficient b2 data register bits 7:0...

  • Page 79: Coefficient A2 Data Register Bits 15:8

    Reserved Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA380BW via RAM. Access to this RAM is available to the user via an I register interface. A collection of I C registers is dedicated to this function. One contains a...
  • Page 80 Register description: New Map STA380BW Reading a coefficient from RAM Write 6 bits of the address to I C register 0x27. Write 1 to the R1 bit in I C address 0x37. Read the top 8 bits of the coefficient in I C address 0x28.
  • Page 81 When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA380BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.

  • Page 82: User-Defined Eq

    STA380BW 6.23.18 User-defined EQ The STA380BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2 * (b / 2) * X[n] + 2 * (b...

  • Page 83: Table 72. Ram Block For Biquads, Mixing, Scaling And Bass Management

    STA380BW Register description: New Map default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4. Table 72. RAM block for biquads, mixing, scaling and bass management Index (decimal) Index (hex)

  • Page 84: Fault-Detect Recovery Constant Registers (Addr 0X3C - 0X3D)

    Register description: New Map STA380BW 6.24 Fault-detect recovery constant registers (addr 0x3C - 0x3D) FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant.

  • Page 85: Extended Biquad Selector

    STA380BW Register description: New Map Table 75. Extended attack rate, limiter 2 XAR2 Mode Limiter2 attack rate is configured using Table 67 Limiter2 attack rate is 8 dB/ms 6.25.3 Extended biquad selector Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.

  • Page 86: Pll Configuration Registers

    PDSTATE OSCOK LOWCK By default, the STA380BW is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’)

  • Page 87: Table 80. Pll Register 0X54 Bits

    STA380BW Register description: New Map Table 80. PLL register 0x54 bits Name Description “00”: PLL clock dithering disabled “01”: PLL clock dithering enabled (triangular) PLL_DITH[1:0] “10”: PLL clock dithering enabled (rectangular) “11”: reserved PLL_NDIV PLL loop divider Table 81. PLL register 0x55 bits...

  • Page 88: Short-Circuit Protection Mode Registers Shok (Address 0X58)

    Register description: New Map STA380BW Table 83. PLL register 0x57 bits Name Description BYPSTATE PLL bypass state PDSTATE PLL PD state OSCOK OSCI locked LOWCK Clock input low-frequency check 6.27 Short-circuit protection mode registers SHOK (address 0x58) reserved reserved reserved...

  • Page 89: Extended Coefficient Range Up To -4

    CEXT_B51] CEXT_B5[0] Biquads from 1 to 7 have in the STA380BW the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the use of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1.

  • Page 90: Miscellaneous Registers (Address 0X5C, 0X5D)

    6.29.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) A fade-out procedure is started in the STA380BW once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down (tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without waiting for the 13 million clock cycles.

  • Page 91: Channel Pwm Enable (Cpwmen) Bit

    STA380BW Register description: New Map 6.29.3 Channel PWM enable (CPWMEN) bit This bit, when set, activates a mute output in case the volume reaches a value lower than -76 dBFS. 6.29.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings can be reconfigured as a hardware pin enabler for an external headphone or line amplifier.

  • Page 92: Short-Circuit Check Enable Bit

    BPTIM[1] BPTIM[0] The STA380BW implements a detection on PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect the DC level in the PWM outputs. To be noted that the checks are performed on logic level PWM (i.e.

  • Page 93: Enhanced Zero-Detect Mute And Input Level Measurement

    RMS_CH1[7:0] RMS_CH1[15:8] The STA380BW implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground.

  • Page 94: Table 89. Manual Threshold Register 0X3F, 0X40 And 0X6F

    Register description: New Map STA380BW Table 88. Zero-detect hysteresis HSEL[1:0] Equivalent input level hysteresis(dB) The thresholds and hysteresis table above can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits. To activate the manual thresholds the FINETH bit has to be set to ‘1’.

  • Page 95: Stcompressor

    STA380BW Register description: New Map 6.32 STCompressor configuration register (address 0x6B; 0x6C) Table 90. Register STCCFG0 Reserved Reserved Reserved Reserved Reserved CRC_RES Reserved Reserved Table 91. STCCFG0 register Name Description ‘0’ = CRC comparison successful CRC_RES ‘1’ = CRC comparison error Table 92.

  • Page 96: Coefficient Ram Crc Protection (Address 0X71-0X7D)

    Register description: New Map STA380BW 6.33 Coefficient RAM CRC protection (address 0x71-0x7D) BQCKE[7] BQCKE[6] BQCKE[5] BQCKE[4] BQCKE[3] BQCKE[2] BQCKE[1] BQCKE[0] BQCKE[15] BQCKE[14] BQCKE[13] BQCKE[12] BQCKE[11] BQCKE[10] BQCKE[9] BQCKE[8] BQCKE[23] BQCKE[22] BQCKE[21] BQCKE[20] BQCKE[19] BQCKE[18] BQCKE[17] BQCKE[16] XCCKE[7] XCCKE[6] XCCKE[5] XCCKE[4]...
  • Page 97 Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA380BW, on each audio frame, and a reset event will be triggered in case of checksum mismatch.

  • Page 98: Misc4 (Address 0X7E)

    ‘0’ = normal operations CH12 ‘1’ = enables the RAM coefficients direct access The STA380BW allows direct access to the RAM coefficients bypassing the indirect access mechanism described in Section 6.23: User-defined coefficient control registers (addr 0x27 0x37). Direct access is implemented as follows.

  • Page 99: Figure 30. Coefficients Direct Access Single-Write Operation

    Figure Figure 32. Coefficients direct access single-read operation Please be aware that the STA380BW supports 24-bit coefficients, for this reason in the above figures Coeff_x(0) is always equal to 0x00 when either reading or writing. The multi- write procedure embeds a wrap-around mechanism: when trying to write into a location exceeding the maximum coefficient address, the multi-write procedure will start from location 0x00.

  • Page 100: Register Description: Sound Terminal Compatibility

    Register description: Sound Terminal compatibility STA380BW Register description: Sound Terminal compatibility To keep compatibility with previous Sound Terminal devices, the 0x7E bit D7 must be set to 0 after device turn-on and after any reset (via SW or via external pin).

  • Page 101: Table 95. I 2 C Registers Summary

    STA380BW Register description: Sound Terminal compatibility Table 95. I C registers summary (continued) A1CF3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0 A2CF1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16 A2CF2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8...
  • Page 102 Register description: Sound Terminal compatibility STA380BW Table 95. I C registers summary (continued) BRIDGOF MISC1 RPDNEN CPWMEN MISC2 LPDP LPDE PNDLSL[2:0] SHEN BPTH BPTH(5:0) BADPWM BP4B BP4A BP3B BP3A BP2B BP2A BP1B BP1A BPTIM BPTIM[7:0] ZCCFG0 WTHH WTHL FINETH HSEL[1:0]...

  • Page 103: Configuration Register A (Addr 0X00)

    S sampling MCS1 frequency and the input clock. MCS2 The STA380BW supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is:  32.768 MHz for 32 kHz ...

  • Page 104: Interpolation Ratio Select

    FDRB 1: fault-detect recovery disabled The on-chip STA380BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block...

  • Page 105: Configuration Register B (Addr 0X01)

    The STA380BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA380BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.

  • Page 106: Table 103. Support Serial Audio Input Formats For Msb-First (Saifb = 0)

    Register description: Sound Terminal compatibility STA380BW Table 103. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI SAI [3:0] SAIFB Interface format 0000 S 15-bit data 32 * fs 0001 Left/right-justified 16-bit data 0000 S 16- to 23-bit data...

  • Page 107: Table 104. Supported Serial Audio Input Formats For Lsb-First (Saifb = 1)

    Right-justified 18-bit data 1110 Right-justified 16-bit data To make the STA380BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock which means that:  the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on...

  • Page 108: Delay Serial Clock Enable

    Register description: Sound Terminal compatibility STA380BW happens. At the same time any processing related to the I C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again. Note: Any mute or volume change causes some delay in the completion of the I C operation due to the soft volume feature.

  • Page 109: Configuration Register C (Addr 0X02)

    Configuration register D (addr 0x03) Reserved DSPB Reserved Reserved 7.4.1 DSP bypass Table 109. DSP bypass Name Description 0: Normal operation DSPB 1: Bypass of biquad and bass/treble functions Setting the DSPB bit bypasses the EQ function of the STA380BW. DocID024543 Rev 1 109/162...

  • Page 110: Post-Scale Link

    Register description: Sound Terminal compatibility STA380BW 7.4.2 Post-scale link Table 110. Post-scale link Name Description 0: Each channel uses individual post-scale value 1: Each channel uses channel 1 post-scale value Post-scale functionality can be used for power supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster.

  • Page 111: Noise-Shaper Bandwidth Selection

    0: Normal FFX operation 1: AM reduction mode FFX operation The STA380BW features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner.

  • Page 112: Configuration Register F (Addr 0X05)

    Register description: Sound Terminal compatibility STA380BW Configuration register F (addr 0x05) EAPD PWDN Reserved LDTE BCLE OCFG1 OCFG0 7.6.1 Output configuration Table 119. Output configuration Name Description OCFG0 Selects the output configuration OCFG1 Table 120. Output configuration engine selection OCFG[1:0]...

  • Page 113: Figure 33. Ocfg = 00 (Default Value)

    STA380BW Register description: Sound Terminal compatibility Figure 33. OCFG = 00 (default value) OUT1A OUT1A Half Half Bridge Bridge Channel 1 Channel 1 Half Half Bridge Bridge OUT1B OUT1B OUT2A OUT2A Half Half Bridge Bridge Channel 2 Channel 2 Half...

  • Page 114: Figure 36. Ocfg = 11

    OUT4B OUT4B The STA380BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.

  • Page 115: Figure 38. 2.0 Channels (Ocfg = 00) Pwm Slots

    STA380BW Register description: Sound Terminal compatibility For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage: 2.0 channels, two full-bridges (OCFG = 00)  FFX1A -> OUT1A  FFX1B -> OUT1B ...

  • Page 116: Figure 39. 2.1 Channels (Ocfg = 01) Pwm Slots

    Register description: Sound Terminal compatibility STA380BW 2.1 channels, two half-bridges + one full-bridge (OCFG = 01)  FFX1A -> OUT1A  FFX2A -> OUT1B  FFX3A -> OUT2A  FFX3B -> OUT2B  FFX1A -> OUT3A  FFX1B -> OUT3B ...

  • Page 117: Figure 40. 2.1 Channels (Ocfg = 10) Pwm Slots

    STA380BW Register description: Sound Terminal compatibility 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10)  FFX1A -> OUT1A  FFX1B -> OUT1B  FFX2A -> OUT2A  FFX2B -> OUT2B  FFX3A -> OUT3A  FFX3B -> OUT3B ...

  • Page 118: Invalid Input Detect Mute Enable

    Register description: Sound Terminal compatibility STA380BW 7.6.2 Invalid input detect mute enable Table 121. Invalid input detect mute enable Name Description Setting of 1 enables the automatic invalid input detect mute Setting the IDE bit enables this function, which looks at the input I S data and automatically mutes if the signals are perceived as invalid.

  • Page 119: Volume Control Registers (Addr 0X06 - 0X0A)

    STA380BW Register description: Sound Terminal compatibility The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the EAPD/FFX4B output pin when OCFG = 10.

  • Page 120: Master Volume Register

    Channel 3 / line output volume CH3VOL[7:0] The volume structure of the STA380BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB.

  • Page 121: Table 128. Master Volume Offset As A Function Of Mvol[7:0]

    STA380BW Register description: Sound Terminal compatibility Table 128. Master volume offset as a function of MVOL[7:0] MVOL[7:0] Volume offset from channel value 00000000 (0x00) 0 dB 00000001 (0x01) -0.5 dB 00000010 (0x02) -1 dB … … 01001100 (0x4C) -38 dB …...

  • Page 122: Audio Preset Registers (Addr 0X0C)

    Register description: Sound Terminal compatibility STA380BW Audio preset registers (addr 0x0C) 7.8.1 Audio preset register (addr 0x0C) AMAM2 AMAM1 AMAM0 AMAME 7.8.2 AM interference frequency switching Table 130. AM interference frequency switching bits Name Description Audio preset AM enable AMAME...

  • Page 123: Channel Configuration Registers (Addr 0X0E - 0X10)

    STA380BW Register description: Sound Terminal compatibility Table 133. Bass management crossover frequency XO[3:0] Crossover frequency 0000 User-defined 0001 80 Hz 0010 100 Hz 0011 120 Hz 0100 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz...

  • Page 124: Eq Bypass

    Register description: Sound Terminal compatibility STA380BW 7.9.2 EQ bypass EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel.

  • Page 125: Output Mapping

    STA380BW Register description: Sound Terminal compatibility 7.9.6 Output mapping Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.

  • Page 126: Dynamic Control Registers (Addr 0X12 - 0X15)

    0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA380BW, it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain.
  • Page 127 STA380BW Register description: Sound Terminal compatibility automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register.

  • Page 128: Table 141. Limiter Attack Rate As A Function Of Lxa Bits

    Register description: Sound Terminal compatibility STA380BW Figure 41. Basic limiter and volume flow diagram Limiter Gain / Vo lume In p ut Outp ut Gain Atten uatio n Saturatio n Table 141. Limiter attack rate as a Table 142. Limiter release rate as a...

  • Page 129: Table 143. Limiter Attack Threshold As A Function Of Lxat Bits (Ac Mode)

    STA380BW Register description: Sound Terminal compatibility Anticlipping mode Table 143. Limiter attack threshold as Table 144. Limiter release threshold as a function of LxAT bits (AC mode) a function of LxRT bits (AC mode) LxAT[3:0] AC (dB relative to fs)

  • Page 130: Limiter 1 Extended Attack Threshold (Addr 0X32)

    Register description: Sound Terminal compatibility STA380BW Dynamic range compression mode Table 145. Limiter attack threshold Table 146. Limiter release threshold as a function of LxAT bits as a function of LxRT bits (DRC mode) (DRC mode) DRC (db relative to volume +...

  • Page 131: Limiter 2 Extended Attack Threshold (Addr 0X34

    STA380BW Register description: Sound Terminal compatibility To enable this feature, the ERTHEN2 bit must be set to 1. 7.11.7 Limiter 2 extended attack threshold (addr 0x34) EATHEN2 EATH2[6] EATH2[5] EATH2[4] EATH2[3] EATH2[2] EATH2[1] EATH2[0] The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4 To enable this feature, the EATHEN2 bit must be set to 1.

  • Page 132: Coefficient B1 Data Register Bits 7:0

    Register description: Sound Terminal compatibility STA380BW 7.12.4 Coefficient b1 data register bits 7:0 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0 7.12.5 Coefficient b2 data register bits 23:16 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 7.12.6 Coefficient b2 data register bits 15:8...

  • Page 133: Coefficient A2 Data Register Bits 15:8

    Coefficients for user-defined EQ, mixing, scaling, bass management and STCompressor (see Section 4.2) are handled internally in the STA380BW via RAM. Access to this RAM is available to the user via an I C register interface. A collection of I C registers are dedicated to this function.
  • Page 134 Register description: Sound Terminal compatibility STA380BW Reading a coefficient from RAM Write 6 bits of the address to I C register 0x16. Write 1 to the R1 bit in I C address 0x26. Read the top 8 bits of the coefficient in I C address 0x17.
  • Page 135 When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA380BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.

  • Page 136: User-Defined Eq

    STA380BW 7.12.18 User-defined EQ The STA380BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2 * (b / 2) * X[n] + 2 * (b...

  • Page 137: Table 147. Ram Block For Biquads, Mixing, Scaling And Bass Management

    STA380BW Register description: Sound Terminal compatibility default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4. Table 147. RAM block for biquads, mixing, scaling and bass management...

  • Page 138: Fault-Detect Recovery Constant Registers (Addr 0X2B - 0X2C)

    Register description: Sound Terminal compatibility STA380BW 7.13 Fault-detect recovery constant registers (addr 0x2B - 0x2C) FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant.

  • Page 139: Extended Configuration Register (Addr 0X36)

    The extended configuration register provides access to B DRC and biquad 5, 6 and 7. 7.16.1 Dual-band DRC The STA380BW device provides a dual-band DRC (B DRC) on the left and right channel data path, as depicted in Figure 42. The dual-band DRC is activated by setting MDRCE = 1.

  • Page 140: Extended Post-Scale Range

    Register description: Sound Terminal compatibility STA380BW Sub-band decomposition The sub-band decomposition for B DRC can be configured specifying the cutoff frequency. The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).

  • Page 141: Extended Attack Rate

    STA380BW Register description: Sound Terminal compatibility 7.16.3 Extended attack rate The attack rate shown in Table 142 can be extended to provide up to an 8 dB/ms attack rate on both limiters. Table 150. Extended attack rate, limiter 1 XAR1...

  • Page 142: Eq Soft Volume Configuration Registers (Addr 0X37 - 0X38)

    Register description: Sound Terminal compatibility STA380BW 7.17 EQ soft volume configuration registers (addr 0x37 - 0x38) Reserved Reserved SVUPE SVUP[4] SVUP[3] SVUP[2] SVUP[1] SVUP[0] Reserved Reserved SVDWE SVDW4] SVDW[3] SVDW[2] SVDW[1] SVDW[0] The soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to override the default behavior, allowing different volume change rates.

  • Page 143: Extra Volume Resolution Configuration Registers (Address 0X3F; 0X40)

    STA380BW Register description: Sound Terminal compatibility 7.18 Extra volume resolution configuration registers (address 0x3F; 0x40) VRESEN VRESTG C3VR[1] C3VR[0] C2VR[1] C2VR[0] C1VR[1] C1VR[0] reserved reserved reserved reserved reserved reserved MVR[1] MVR[0] Extra volume resolution allows fine volume tuning by steps of 0.125 dB.

  • Page 144: Pll Configuration Registers

    OSCOK LOWCK By default the STA380BW is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’).

  • Page 145: Table 159. Pll Factors

    STA380BW Register description: Sound Terminal compatibility The output PLL frequency formula is:   NDIV FRAC      -------------------------- - ---------------- -       IDIV 65536 where Fin is the input clock frequency from the pad.

  • Page 146: Short-Circuit Protection Mode Registers Shok (Address 0X47)

    Register description: Sound Terminal compatibility STA380BW Table 162. PLL register 0x45 bits Name Description ‘0’: PLL configuration is determined by MCS bits PLL_DIRP ‘1’: PLL configuration is determined by FRAC, IDIV and NDIV ‘0’: PLL normal behavior PLL_PWD ‘1’: PLL is in power-down mode ‘0’: sys clock is from PLL...

  • Page 147: Figure 44. Short-Circuit Detection Timing Diagram (No Short Detected)

    STA380BW Register description: Sound Terminal compatibility To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation cannot be detected.

  • Page 148: Extended Coefficient Range Up To -4

    CEXT_B51] CEXT_B5[0] Biquads from 1 to 7 have in the STA380BW the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the implementation of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1.

  • Page 149: Bridge Immediately Off (Bridgoff) Bit (Address 0X4B, Bit D5)

    7.22.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) A fade-out procedure is started in the STA380BW once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down (tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without waiting for the 13 million clock cycles.

  • Page 150: Power-Down Delay Selector (Pndlsl[2:0]) Bits (Address 0X4C, Bit D4, D3, D2)

    Register description: Sound Terminal compatibility STA380BW Figure 45. Alternate function for INTLINE pin Po w er B rid ge Fau lt ‘0 ’ IN T L IN E LPD E “is the d evice in p ow erd o w n ?”...

  • Page 151: Bad Pwm Detection Registers (Address 0X4D, 0X4E, 0X4F)

    BPTIM[1] BPTIM[0] The STA380BW implements a detection on the PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect DC levels in the PWM outputs. To be noted that the checks are performed on logic level PWM (i.e.

  • Page 152: Enhanced Zero-Detect Mute And Input Level Measurement (Address 0X50-0X54, 0X2E, 0X2F And 0X5E)

    RMS_CH1[7:0] RMS_CH1[15:8] The STA380BW implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground.

  • Page 153: Table 169. Manual Threshold Register 0X2E, 0X2F And 0X5E

    STA380BW Register description: Sound Terminal compatibility Table 168. Zero-detect hysteresis HSEL[1:0] Equivalent input level hysteresis (dB) The above thresholds and hysteresis table can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits. To activate the manual thresholds the FINETH bit has to be set to ‘1’.

  • Page 154: Stcompressor

    Register description: Sound Terminal compatibility STA380BW 7.25 STCompressor configuration register (address 0x5A; 0x5B) reserved LIM_BYP STC_BYP STC_ENA reserved NP_CRES reserved NP_CRC-GO reserved reserved reserved reserved reserved reserved STC_LNK BRC_EN Table 170. STCompressor configuration bits1 Name Description ‘0’: STCompressor DRC active LIM_BYP ‘1’: STCompressor...

  • Page 155: Coefficient Ram Crc Protection (Address 0X60-0X6C)

    STA380BW Register description: Sound Terminal compatibility 7.26 Coefficient RAM CRC protection (address 0x60-0x6C) BQCKE[7] BQCKE[6] BQCKE[5] BQCKE[4] BQCKE[3] BQCKE[2] BQCKE[1] BQCKE[0] BQCKE[15] BQCKE[14] BQCKE[13] BQCKE[12] BQCKE[11] BQCKE[10] BQCKE[9] BQCKE[8] BQCKE[23] BQCKE[22] BQCKE[21] BQCKE[20] BQCKE[19] BQCKE[18] BQCKE[17] BQCKE[16] XCCKE[7] XCCKE[6] XCCKE[5]...
  • Page 156 Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA380BW, on each audio frame, and the reset event will be triggered in case of checksum mismatch.

  • Page 157: Misc3 (Address 0X6E)

    STA380BW Register description: Sound Terminal compatibility 7.27 MISC3 (address 0x6E) reserved reserved reserved reserved reserved SRESET reserved reserved Table 172. Misc register 3 Name Description ‘0’: normal operation SRESET ‘1’: reset the device After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit D7) is set to1 instead of the 0 default value obtained after the hardware reset.

  • Page 158: Applications

    Applications STA380BW Applications Typical output configuration Figure 46 illustrates the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other schematics for the recommended output configuration. Figure 46. Output configuration for stereo BTL mode in filterlight configuration Note: For further information, please refer to application note AN3959, 2.0-channel demonstration...

  • Page 159: Package Information

    STA380BW Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.

  • Page 160: Table 174. Vqfn48 (7 X 7 X 0.9 Mm) Package Dimensions

    Package information STA380BW Table 174. VQFN48 (7 x 7 x 0.9 mm) package dimensions Reference Min. Typ. 0.80 0.90 1.00 0.05 6.90 7.00 7.10 5.65 5.70 5.75 6.90 7.00 7.10 5.65 5.70 5.75 0.25 0.30 0.35 0.20 0.25 0.30 e (pad pitch) 0.50...

  • Page 161: Revision History

    STA380BW Revision history Revision history Table 175. Document revision history Date Revision Changes 15-Apr-2013 Initial release DocID024543 Rev 1 161/162...
  • Page 162 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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