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Sound Termina STA382BWTR
User Manuals: ST Sound Termina STA382BWTR Audio System
Manuals and User Guides for ST Sound Termina STA382BWTR Audio System. We have
1
ST Sound Termina STA382BWTR Audio System manual available for free PDF download: Manual
ST Sound Termina STA382BWTR Manual (172 pages)
Brand:
ST
| Category:
Stereo System
| Size: 3 MB
Table of Contents
Table 1. Device Summary
1
Table of Contents
2
Description
17
Block Diagram
18
Figure 1. Block Diagram
18
Pin Connections
19
Connection Diagram
19
Figure 2. Pin Connections VQFN48 (Top View)
19
Pin Description
20
Table 2. Pin List
20
Electrical Specifications
22
Absolute Maximum Ratings
22
Thermal Data
22
Table 3. Absolute Maximum Ratings
22
Table 4. Thermal Data
22
Recommended Operating Conditions
23
Electrical Specifications for the Digital Section
23
Table 5. Recommended Operating Conditions
23
Table 6. Electrical Specifications - Digital Section
23
Electrical Specifications for the Power Section
24
Table 7. Electrical Specifications - Power Section
24
Electrical Specifications for the Analog Section
25
Table 8. Electrical Specifications for the Analog Section
25
Figure 3. Test Circuit
25
Device Overview
26
Processing Data Path
26
Figure 4. Processing Path, First Part
26
Figure 5. Processing Path, Second Part: 2.1 Output with Individually Configurable Anticlipper/Drcs
27
Figure 7. Processing Path, Second Part: 2.1 Output Configuration with Stcompressor TM
28
Input Oversampling
29
Stcompressor TM
29
STC Block Diagram
30
Band Splitter
30
Figure 8. Stcompressor TM Block Diagram
30
Level Meter
31
Mapper
31
Table 9. Coefficients Extended-Range Configuration 0X74H
31
Figure 9. Band Splitter with 4Th Order Filtering
31
Figure 10. Stcompressor TM Behavior
32
Table 10. Compressor Ratio
33
Figure 11. Stcompressor TM Behavior as a Limiter
33
Attenuator
34
Dynamic Attack
34
Offset
35
Stereo Link
35
Figure 12. Offset Effect
35
Programming of Coefficients
36
Figure 13. Stereo Link Block Diagram
36
Table 11. Conversion Example
37
Memory Map
38
Table 12. STC Coefficients Memory Map
38
Table 13. STC Band Splitter Filters Memory Map
39
I 2 C Bus Specification
40
Communication Protocol
40
Data Transition or Change
40
Start Condition
40
Stop Condition
40
Data Input
40
Device Addressing
40
Write Operation
41
Byte Write
41
Multi-Byte Write
41
Read Operation
41
Current Address Byte Read
41
Current Address Multi-Byte Read
41
Random Address Byte Read
41
Random Address Multi-Byte Read
41
Write Mode Sequence
42
Read Mode Sequence
42
Figure 14. Write Mode Sequence
42
Figure 15. Read Mode Sequence
42
Register Description: New Map
43
Table 14. Default Register Map Table: NEW MAP
43
CLK Register (Addr 0X00)
46
STATUS Register (Addr 0X01)
46
Table 15. CLK Register
46
Table 16. STATUS Register
46
RESET Register (Addr 0X02)
47
Soft Volume Register (Addr 0X03)
47
Table 17. RESET Register
47
Table 18. Soft Volume Register
47
MVOL Register (Addr 0X04)
48
FINEVOL Register (Addr 0X05)
48
Table 19. Master Volume Register
48
Table 20. Fine Volume Register
48
CH1VOL Register (Addr 0X06)
49
CH2VOL Register (Addr 0X07)
49
Table 21. Channel 1 Volume Register
49
Table 22. Channel 2 Volume Register
49
POST Scaler Register (Addr 0X08)
50
OPER Register (Addr 0X09)
50
Table 23. OPER Register
50
Table 24. OPER Configuration Selection
50
Figure 16. OPER = 00 (Default Value)
51
Figure 17. OPER = 11
51
Figure 18. OPER = 10
51
Figure 19. OPER = 01
52
Figure 20. Output Mapping Scheme
52
Figure 21. 2.0 Channels (OPER = 00) PWM Slots
53
Figure 22. 2.1 Channels (OPER = 11) PWM Slots
54
Figure 23. 2.1 Channels (OPER = 10) PWM Slots
55
FUNCT Register (Addr 0X0A)
56
Dual-Band DRC
56
Table 25. FUNCT Register
56
Figure 24. B 2 DRC Scheme
56
HPCFG Register (Addr 0X10)
58
Configuration Register a (Addr 0X11)
58
Master Clock Select
58
Table 26. HPCFG Register
58
Table 27. Master Clock Select
58
Interpolation Ratio Selection
59
Fault-Detect Recovery Bypass
59
Table 28. Input Sampling Rates
59
Table 29. Internal Interpolation Ratio
59
Table 30. IR Bit Settings as a Function of the Input Sampling Rate
59
Table 31. Fault-Detect Recovery Bypass
59
Configuration Register B (Addr 0X12)
60
Serial Data Interface
60
Serial Data First Bit
61
Table 32. Serial Data First Bit
61
Table 33. Support Serial Audio Input Formats for MSB-First (SAIFB = 0)
61
Table 34. Supported Serial Audio Input Formats for LSB-First (SAIFB = 1)
62
Delay Serial Clock Enable
63
Channel Input Mapping
63
Configuration Register C (Addr 0X13)
63
FFX Compensating Pulse Size Register
63
Table 35. Delay Serial Clock Enable
63
Table 36. Channel Input Mapping
63
Table 37. FFX Compensating Pulse Size Bits
63
Configuration Register D (Addr 0X14)
64
DSP Bypass
64
Post-Scale Link
64
Biquad Coefficient Link
64
Table 38. Compensating Pulse Size
64
Table 39. DSP Bypass
64
Table 40. Post-Scale Link
64
Table 41. Biquad Coefficient Link
64
Zero-Detect Mute Enable
65
Submix Mode Enable
65
Configuration Register E (Addr 0X15)
65
Noise-Shaper Bandwidth Selection
65
AM Mode Enable
65
Table 42. Zero-Detect Mute Enable
65
Table 43. Submix Mode Enable
65
Table 44. Noise-Shaper Bandwidth Selection
65
Table 45. am Mode Enable
65
PWM Speed Mode
66
Zero-Crossing Enable
66
Configuration Register F (Addr 0X16)
66
Invalid Input Detect Mute Enable
66
Binary Output Mode Clock Loss Detection
66
Table 46. PWM Speed Mode
66
Table 47. Zero-Crossing Enable
66
Table 48. Invalid Input Detect Mute Enable
66
Table 49. Binary Output Mode Clock Loss Detection
66
LRCK Double Trigger Protection
67
Auto EAPD on Clock Loss
67
Power-Down
67
External Amplifier Power-Down
67
Table 50. LRCK Double Trigger Protection
67
Table 51. Auto EAPD on Clock Loss
67
Table 52. IC Power-Down
67
Table 53. External Amplifier Power-Down
67
Volume Control Registers (Addr 0X17 - 0X1B)
68
Mute/Line Output Configuration Register (Addr 0X17)
68
Table 54. Line Output Configuration
68
Table 55. Mute Configuration
68
Channel 3 / Line Output Volume (Addr 0X1B)
69
Table 56. Channel 3 Volume as a Function of CH3VOL[7:0]
69
Audio Preset Registers (0X1D)
70
AM Interference Frequency Switching
70
Bass Management Crossover
70
Table 57. am Interference Frequency Switching Bits
70
Table 58. Audio Preset am Switching Frequency Selection
70
Table 59. Bass Management Crossover
70
Channel Configuration Registers (Addr 0X1F - 0X21)
71
Tone Control Bypass
71
Table 60. Bass Management Crossover Frequency
71
Table 61. Tone Control Bypass
71
EQ Bypass
72
Volume Bypass
72
Binary Output Enable Registers
72
Limiter Select
72
Table 62. EQ Bypass
72
Table 63. Volume Bypass Register
72
Table 64. Binary Output Enable Registers
72
Table 65. Channel Limiter Mapping as a Function of C3LS Bits
72
Output Mapping
73
Tone Control Register (Addr 0X22)
73
Tone Control
73
Table 66. Channel Output Mapping as a Function of C3OM Bits
73
Table 67. Tone Control Boost/Cut as a Function of BTC and TTC Bits
73
Dynamic Control Registers (Addr 0X23 - 0X26 / Addr 0X43 - 0X46)
74
Limiter 1 Attack/Release Rate (L1AR Addr 0X23)
74
Limiter 1 Attack/Release Threshold (L1ATRT Addr 0X24)
74
Limiter 2 Attack/Release Rate ( L2AR Addr 0X25)
74
Limiter 2 Attack/Release Threshold ( L2 ATRT Addr 0X26)
74
Table 68. Limiter Attack Rate as a Function of Lxa Bits
76
Table 69. Limiter Release Rate as a Function of Lxr Bits
76
Figure 25. Basic Limiter and Volume Flow Diagram
76
Table 70. Limiter Attack Threshold as a Function of Lxat Bits (AC Mode)
77
Table 71. Limiter Release Threshold as a Function of Lxrt Bits (AC Mode)
77
Limiter 1 Extended Attack Threshold (Addr 0X43)
78
Limiter 1 Extended Release Threshold (Addr 0X44)
78
Table 72. Limiter Attack Threshold as a Function of Lxat Bits (DRC Mode)
78
Table 73. Limiter Release Threshold as a Function of Lxrt Bits (DRC Mode)
78
Limiter 2 Extended Attack Threshold (Addr 0X45)
79
Limiter 2 Extended Release Threshold (Addr 0X46)
79
User-Defined Coefficient Control Registers (Addr 0X27 - 0X37)
79
Coefficient Address Register
79
Coefficient B1 Data Register Bits 23:16
79
Coefficient B1 Data Register Bits 15:8
79
Coefficient B1 Data Register Bits 7:0
79
Coefficient B2 Data Register Bits 23:16
80
Coefficient B2 Data Register Bits 15:8
80
Coefficient B2 Data Register Bits 7:0
80
Coefficient A1 Data Register Bits 23:16
80
Coefficient A1 Data Register Bits 15:8
80
Coefficient A1 Data Register Bits 7:0
80
Coefficient A2 Data Register Bits 23:16
80
Coefficient A2 Data Register Bits 15:8
81
Coefficient A2 Data Register Bits 7:0
81
Coefficient B0 Data Register Bits 23:16
81
Coefficient B0 Data Register Bits 15:8
81
Coefficient B0 Data Register Bits 7:0
81
Coefficient Write/Read Control Register
81
User-Defined EQ
84
Pre-Scale
84
Post-Scale
84
Table 74. RAM Block for Biquads, Mixing, Scaling and Bass Management
85
Fault-Detect Recovery Constant Registers (Addr 0X3C - 0X3D)
86
Extended Configuration Register (Addr 0X47)
86
Extended Post-Scale Range
86
Extended Attack Rate
86
Table 75. Extended Post-Scale Range
86
Table 76. Extended Attack Rate, Limiter 1
86
Extended Biquad Selector
87
Table 77. Extended Attack Rate, Limiter 2
87
Table 78. Extended Biquad Selector, Biquad 5
87
Table 79. Extended Biquad Selector, Biquad 6
87
Table 80. Extended Biquad Selector, Biquad 7
87
PLL Configuration Registers (Address 0X52; 0X53; 0X54; 0X55; 0X56; 0X57)
88
Table 81. PLL Factors
88
Table 82. PLL Register 0X54 Bits
89
Table 83. PLL Register 0X55 Bits
89
Table 84. PLL Register 0X56 Bits
89
Short-Circuit Protection Mode Registers SHOK (Address 0X58)
90
Table 85. PLL Register 0X57 Bits
90
Extended Coefficient Range up to -4
91
Figure 26. Short-Circuit Detection Timing Diagram (no Short Detected)
91
Miscellaneous Registers (Address 0X5C, 0X5D)
92
Rate Power-Down Enable (RPDNEN) Bit
92
Bridge Immediately off (BRIDGOFF) Bit (Address 0X4B, Bit D5)
92
Table 86. Coefficients Extended Range Configuration
92
Channel PWM Enable (CPWMEN) Bit
93
External Amplifier Hardware Pin Enabler (LPDP, LPD LPDE) Bits
93
Power-Down Delay Selector (PNDLSL[2:0]) Bits
93
Table 87. External Amplifier Enabler Configuration Bits
93
Figure 27. Alternate Function for INTLINE Pin
93
Short-Circuit Check Enable Bit
94
Bad PWM Detection Registers (Address 0X5E, 0X5F, 0X60)
94
Table 88. PNDLSL Bits Configuration
94
Enhanced Zero-Detect Mute and Input Level Measurement (Address 0X61-0X65, 0X3F, 0X40, 0X6F)
95
Table 89. Zero-Detect Threshold
95
Table 91. Manual Threshold Register 0X3F, 0X40 and 0X6F
96
Table 90. Zero-Detect Hysteresis
96
Headphone/Line out Configuration Register (Address 0X66)
97
Table 92. Headphone/Line out Configuration Bits
97
F3XCFG (Address 0X69; 0X6A)
98
Table 93. F3X Configuration Register 1
98
Table 94. F3X Configuration Register 2
98
Stcompressor
99
Charge Pump Synchronization (Address 0X70)
99
Table 95. Register STCCFG0
99
Table 96. STCCFG0 Register
99
Table 97. Register STCCFG1
99
Table 98. STCCFG1 Register
99
Table 99. Charge Pump Sync Configuration Bits
99
Coefficient RAM CRC Protection (Address 0X71-0X7D)
100
MISC4 (Address 0X7E)
102
Table 100. Misc Register 4
102
Figure 28. Coefficients Direct Access Single-Write Operation
103
Figure 29. Coefficients Direct Access Multiple-Write Operation
103
Figure 30. Coefficients Direct Access Single-Read Operation
103
Register Description: Sound Terminal Compatibility
104
Table 101. I 2 C Registers Summary
104
Configuration Register a (Addr 0X00)
107
Master Clock Select
107
Table 102. Master Clock Select
107
Table 103. Input Sampling Rates
107
Interpolation Ratio Select
108
Fault-Detect Recovery Bypass
108
Table 104. Internal Interpolation Ratio
108
Table 105. IR Bit Settings as a Function of the Input Sampling Rate
108
Table 106. Fault-Detect Recovery Bypass
108
Configuration Register B (Addr 0X01)
109
Serial Data Interface
109
Serial Audio Input Interface Format
109
Serial Data First Bit
109
Table 107. Serial Audio Input Interface
109
Table 108. Serial Data First Bit
109
Table 109. Support Serial Audio Input Formats for MSB-First (SAIFB = 0)
110
Table 110. Supported Serial Audio Input Formats for LSB-First (SAIFB = 1)
111
Delay Serial Clock Enable
112
Channel Input Mapping
112
Table 111. Delay Serial Clock Enable
112
Table 112. Channel Input Mapping
112
Configuration Register C (Addr 0X02)
113
FFX Compensating Pulse Size Register
113
Configuration Register D (Addr 0X03)
113
DSP Bypass
113
Table 113. FFX Compensating Pulse Size Bits
113
Table 114. Compensating Pulse Size
113
Table 115. DSP Bypass
113
Post-Scale Link
114
Biquad Coefficient Link
114
Zero-Detect Mute Enable
114
Submix Mode Enable
114
Configuration Register E (Addr 0X04)
114
Table 116. Post-Scale Link
114
Table 117. Biquad Coefficient Link
114
Table 118. Zero-Detect Mute Enable
114
Table 119. Submix Mode Enable
114
AM Mode Enable
115
Noise-Shaper Bandwidth Selection
115
PWM Speed Mode
115
Soft Volume Update Enable
115
Table 120. Noise-Shaper Bandwidth Selection
115
Table 121. am Mode Enable
115
Table 122. PWM Speed Mode
115
Table 123. Zero-Crossing Enable
115
Table 124. Soft Volume Update Enable
115
Zero-Crossing Enable
115
Configuration Register F (Addr 0X05)
116
Output Configuration
116
Table 125. Output Configuration
116
Table 126. Output Configuration Engine Selection
116
Figure 31. OCFG = 00 (Default Value)
117
Figure 32. OCFG = 01
117
Figure 33. OCFG = 10
117
Figure 34. OCFG = 11
118
Figure 35. Output Mapping Scheme
118
Figure 36. 2.0 Channels (OCFG = 00) PWM Slots
119
Figure 37. 2.1 Channels (OCFG = 01) PWM Slots
120
Figure 38. 2.1 Channels (OCFG = 10) PWM Slots
121
Invalid Input Detect Mute Enable
122
Binary Output Mode Clock Loss Detection
122
LRCK Double Trigger Protection
122
Auto EAPD on Clock Loss
122
IC Power-Down
122
Table 127. Invalid Input Detect Mute Enable
122
Table 128. Binary Output Mode Clock Loss Detection
122
Table 129. LRCK Double Trigger Protection
122
Table 130. Auto EAPD on Clock Loss
122
Table 131. IC Power-Down
122
External Amplifier Power-Down
123
Volume Control Registers (Addr 0X06 - 0X0A)
123
Mute/Line Output Configuration Register
123
Table 132. External Amplifier Power-Down
123
Table 133. Line Output Configuration
123
Master Volume Register
124
Channel 1 Volume
124
Channel 2 Volume
124
Channel 3 / Line Output Volume
124
Table 134. Mute Configuration
124
Table 135. Master Volume Offset as a Function of MVOL[7:0]
125
Table 136. Channel Volume as a Function of Cxvol[7:0]
125
Audio Preset Registers (Addr 0X0C)
126
Audio Preset Register (Addr 0X0C)
126
AM Interference Frequency Switching
126
Bass Management Crossover
126
Table 137. am Interference Frequency Switching Bits
126
Table 138. Audio Preset am Switching Frequency Selection
126
Table 139. Bass Management Crossover
126
Channel Configuration Registers (Addr 0X0E - 0X10)
127
Tone Control Bypass
127
Table 140. Bass Management Crossover Frequency
127
Table 141. Tone Control Bypass
127
EQ Bypass
128
Volume Bypass
128
Binary Output Enable Registers
128
Limiter Select
128
Table 142. EQ Bypass
128
Table 143. Volume Bypass Register
128
Table 144. Binary Output Enable Registers
128
Table 145. Channel Limiter Mapping as a Function of Cxls Bits
128
Output Mapping
129
Tone Control Register (Addr 0X11)
129
Tone Control
129
Table 146. Channel Output Mapping as a Function of Cxom Bits
129
Table 147. Tone Control Boost/Cut as a Function of BTC and TTC Bits
129
Dynamic Control Registers (Addr 0X12 - 0X15)
130
Limiter 1 Attack/Release Rate
130
Limiter 1 Attack/Release Threshold
130
Limiter 2 Attack/Release Rate
130
Limiter 2 Attack/Release Threshold
130
Table 148. Limiter Attack Rate as a Function of Lxa Bits
132
Table 149. Limiter Release Rate as a Function of Lxr Bits
132
Figure 39. Basic Limiter and Volume Flow Diagram
132
Table 150. Limiter Attack Threshold as a Function of Lxat Bits (AC Mode)
133
Table 151. Limiter Release Threshold as a Function of Lxrt Bits (AC Mode)
133
Limiter 1 Extended Attack Threshold (Addr 0X32)
134
Limiter 1 Extended Release Threshold (Addr 0X33)
134
Table 152. Limiter Attack Threshold as a Function of Lxat Bits (DRC Mode)
134
Table 153. Limiter Release Threshold as a Function of Lxrt Bits (DRC Mode)
134
Limiter 2 Extended Attack Threshold (Addr 0X34
135
Limiter 2 Extended Release Threshold (Addr 0X35)
135
User-Defined Coefficient Control Registers (Addr 0X16 - 0X26)
135
Coefficient Address Register
135
Coefficient B1 Data Register Bits 23:16
135
Coefficient B1 Data Register Bits 15:8
135
Coefficient B1 Data Register Bits 7:0
135
Coefficient B2 Data Register Bits 23:16
136
Coefficient B2 Data Register Bits 15:8
136
Coefficient B2 Data Register Bits 7:0
136
Coefficient A1 Data Register Bits 23:16
136
Coefficient A1 Data Register Bits 15:8
136
Coefficient A1 Data Register Bits 7:0
136
Coefficient A2 Data Register Bits 23:16
136
Coefficient A2 Data Register Bits 15:8
137
Coefficient A2 Data Register Bits 7:0
137
Coefficient B0 Data Register Bits 23:16
137
Coefficient B0 Data Register Bits 15:8
137
Coefficient B0 Data Register Bits 7:0
137
Coefficient Write/Read Control Register
137
User-Defined EQ
140
Pre-Scale
140
Post-Scale
140
Table 154. RAM Block for Biquads, Mixing, Scaling and Bass Management
141
Fault-Detect Recovery Constant Registers (Addr 0X2B - 0X2C)
142
Device Status Register (Addr 0X2D)
142
EQ Coefficients Configuration Register (Addr 0X31)
142
Table 155. Status Register Bits
142
Extended Configuration Register (Addr 0X36)
143
Dual-Band DRC
143
Figure 40. B 2 DRC Scheme
143
Extended Post-Scale Range
144
Table 156. Extended Post-Scale Range
144
Extended Attack Rate
145
Extended BIQUAD Selector
145
Table 157. Extended Attack Rate, Limiter 1
145
Table 158. Extended Attack Rate, Limiter 2
145
Table 159. Extended Biquad Selector, Biquad 5
145
Table 160. Extended Biquad Selector, Biquad 6
145
Table 161. Extended Biquad Selector, Biquad 7
145
EQ Soft Volume Configuration Registers (Addr 0X37 - 0X38)
146
Table 162. Soft Volume Update Enable, Increase
146
Table 163. Soft Volume Update Enable, Decrease
146
Extra Volume Resolution Configuration Registers (Address 0X3F; 0X40)
147
Table 164. Volume Fine-Tuning Steps
147
Figure 41. Extra Resolution Volume Scheme
147
PLL Configuration Registers (Address 0X41; 0X42; 0X43; 0X44; 0X45; 0X46)
148
Table 165. Extra Volume Resolution Enable
148
Table 166. PLL Factors
149
Table 167. PLL Register 0X43 Bits
149
Table 168. PLL Register 0X44 Bits
149
Short-Circuit Protection Mode Registers SHOK (Address 0X47)
150
Table 169. PLL Register 0X45 Bits
150
Table 170. PLL Register 0X46 Bits
150
Figure 42. Short-Circuit Detection Timing Diagram (no Short Detected)
151
Extended Coefficient Range up to -4
152
Miscellaneous Registers (Address 0X4B, 0X4C)
152
Rate Power-Down Enable (RPDNEN) Bit (Address 0X4B, Bit D7)
152
Table 171. Coefficients Extended Range Configuration
152
Bridge Immediately off (BRIDGOFF) Bit (Address 0X4B, Bit D5)
153
Channel PWM Enable (CPWMEN) Bit (Address 0X4B, Bit D2)
153
External Amplifier Hardware Pin Enabler (LPDP, LPD LPDE) Bits (Address 0X4C, Bit D7, D6, D5)
153
Table 172. External Amplifier Enabler Configuration Bits
153
Power-Down Delay Selector (PNDLSL[2:0]) Bits (Address 0X4C, Bit D4, D3, D2)
154
Short-Circuit Check Enable Bit (Address 0X4C, Bit D0)
154
Table 173. PNDLSL Bits Configuration
154
Figure 43. Alternate Function for INTLINE Pin
154
Bad PWM Detection Registers (Address 0X4D, 0X4E, 0X4F)
155
Enhanced Zero-Detect Mute and Input Level Measurement (Address 0X50-0X54, 0X2E, 0X2F and 0X5E)
156
Table 174. Zero-Detect Threshold
157
Table 175. Zero-Detect Hysteresis
157
Headphone/Line out Configuration Register (Address 0X55)
158
Table 176. Manual Threshold Register 0X2E, 0X2F and 0X5E
158
Table 177. Headphone/Line out Configuration Bits
158
F3XCFG (Address 0X58; 0X59)
159
Table 178. F3X Configuration Register 1
159
Table 179. F3X Configuration Register 2
159
Stcompressor TM Configuration Register (Address 0X5A; 0X5B)
160
Table 180. Stcompressor TM Configuration Bits1
160
Table 181. Stcompressor TM Configuration Bits 2
160
Charge Pump Synchronization (Address 0X5F)
161
Table 182. Charge Pump Sync Configuration Bits
161
Coefficient RAM CRC Protection (Address 0X60-0X6C)
162
MISC3 (Address 0X6E)
164
MISC4 (Address 0X7E)
164
Table 183. Misc Register 3
164
Table 184. MISC4
164
Applications
165
Application Schemes
165
Figure 44. External Audio Source to Line/Headphone out Application Scheme
165
Figure 45. F3X (from SAI) Source to Line/Headphone out Application Scheme
166
Headphone and 2 Vrms Line out
167
Figure 46. F3X Auxiliary Analog Output
167
Figure 47. Headphone and Line out Block Diagram
167
Typical Output Configuration
168
Figure 48. Output Configuration for Stereo BTL Mode in Filterlight Configuration
168
Package Information
169
Table 185. VQFN48 (7 X 7 X 0.9 MM) Package Dimensions
170
Table 186. Document Revision History
171
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