User Manuals: Scenix SX18AC Communications Controllers

Manuals and User Guides for Scenix SX18AC Communications Controllers. We have 2 Scenix SX18AC Communications Controllers manuals available for free PDF download: User Manual

Scenix SX18AC User Manual

Scenix SX18AC User Manual (174 pages)

Communications Controller

Brand: Scenix | Category: Controller | Size: 1 MB

Table of Contents

Table of Contents
5
Chapter 1 Overview

13
- Introduction
  13
- Key Features
  13
- Architecture
  15
- The Virtual Peripheral Concept
  15
- The Communications Controller
  16
- Programming and Debugging Support
  16
- Applications
  16
- Part Numbers and Pinout Diagrams
  17
- Figure 1-1 SX18/20/28 Pin Assignments
  17
- Figure 1-2 SX48/52BD Pin Assignments
  18
- Table 1-1 Device Package Names
  19
- Figure 1-3 Part Numbering Reference Guide
  20
- Pin Descriptions
  21
- Table 1-2 Pin Descriptions
  22
Chapter 2 Architecture

23
Chapter 3 Instruction Set

57
- Introduction
  57
- Instruction Operands
  57
- Instruction Types
  58
- Instruction Summary Tables
  61
- Table 3-1 Logic Instructions
  62
- Table 3-2 Arithmetic and Shift Instructions
  62
- Table 3-3 Bitwise Operation Instructions
  63
- Table 3-4 Data Movement Instructions
  63
- Table 3-5 Program Control Instructions
  65
- Table 3-6 System Control Instructions
  65
- Equivalent Assembler Mnemonics
  66
- Detailed Instruction Descriptions
  66
  - Table 3-7 Equivalent Assembler Mnemonics
    66
  - ADD Fr,W
    67
  - Table 3-8 Key to Abbreviations and Symbols
    68
  - ADD W,Fr
    70
  - AND Fr,Wand of Fr and W into Fr
    71
  - AND W,Fr and of W and Fr into W
    72
  - AND W,#Lit and of W and Literal into W
    73
  - BANK Addr8
    74
  - CALL Addr8
    76
- Clear Fr
  78
  - CLR W Clear W
    79
  - Clr !Wdt
    80
  - CLRB Fr.bit
    81
  - DEC Fr
    82
  - DECSZ Fr
    83
  - INC Fr
    84
  - INCSZ Fr
    85
  - Iread
    86
  - Figure 3-1 Program Counter Loading for Call Instruction
    86
  - JMP Addr9
    88
  - MOV Fr,W
    89
  - MOV M,#Lit
    90
  - MOV M,W Move W to MODE Register
    91
  - Mov !Option,W
    92
  - MOV !Rx,W Move Data between W and Control Register
    93
  - MOV W,Fr
    95
  - MOV W,/Fr Move Complement of Fr to W
    96
  - MOV W,/Fr
    96
- Move (Fr-1) to W
  98
  - MOV W,++Fr
    99
  - Figure 3-2 Rotate Fr Left through Carry into W
    100
  - Figure 3-3 Rotate Fr Right through Carry into W
    101
  - Mov W,M
    104
  - MOVSZ W, --Fr
    105
  - Move (Fr-1) to W and Skip if Zero
    105
  - MOVSZ W, ++Fr
    106
  - NOP no Operation
    107
  - NOT Fr
    108
  - OR Fr,W
    109
  - OR W,Fr
    110
  - OR W,#Lit
    111
  - RET Return from Subroutine
    113
  - Reti
    114
  - Retp
    116
  - RL Fr
    118
  - Figure 3-4 Rotate Fr Left through Carry
    118
  - RR Fr
    119
  - Figure 3-5 Rotate Fr Right through Carry
    119
  - SB Fr.bit
    120
  - SETB Fr.bit
    121
  - Sleep
    122
  - SNB Fr.bit
    123
  - SUB Fr,W
    124
  - SWAP Fr Swap High/Low Nibbles of Fr
    126
  - TEST Fr
    127
  - XOR Fr,W
    128
  - XOR W,Fr
    129
  - XOR W,#Lit
    130
Chapter 4 Clocking, Power Down, and Reset

131
Chapter 5 Input/Output Ports

145
- Introduction
  145
- Reading and Writing the Ports
  145
- Port Configuration
  146
Chapter 6 Timers and Interrupts

153
- Introduction
  153
- Real-Time Clock/Counter
  153
  - Prescaler Register
    154
  - Maximum Count
    154
  - Figure 6-1 RTCC Block Diagram
    154
  - RTCC Operation as a Real-Time Clock or Timer
    155
  - RTCC Operation as an Event Counter
    155
  - RTCC Overflow Interrupts
    155
- Watchdog Timer
  156
  - Watchdog Timeout Period
    156
  - Watchdog Operation in the Power down Mode
    157
- Interrupts
  157
  - Table 6-1 Watchdog Timeout Settings
    157
  - Interrupt Sequence
    158
  - Single-Level Interrupt Operation
    158
  - Figure 6-2 Interrupt Logic Block Diagram
    159
  - Device-Specific Interrupts
    160
  - Port B Interrupts
    160
  - RTCC Interrupts
    160
  - Interrupt Example
    161
  - Return-From-Interrupt Instructions
    161
Chapter 7 Analog Comparator

163
- Introduction
  163
- Comparator Enable/Status Register (CMP_B)
  163
  - Accessing the CMP_B Register
    164
- Comparator Operation
  164
- Figure 7-1 Comparator Block Diagram
  165
Chapter 8 Multi-Function Timers

167
- Introduction
  167
- Figure 8-1 Multi-Function Timer Block Diagram
  167
- Timer Operating Modes
  168
  - PWM Mode
    168
  - Software Timer Mode
    168
  - External Event Mode
    169
  - Capture/Compare Mode
    169
- Timer Pin Assignments
  170
- Timer Control Registers
  170

Advertisement

Scenix SX18AC User Manual

Scenix SX18AC User Manual (164 pages)

Brand: Scenix | Category: Microcontrollers | Size: 1 MB

Table of Contents

Table of Contents
4
Chapter 1 Overview

11
- Introduction
  11
- Key Features
  11
- CPU Features
  12
- I/O Features
  12
- Architecture
  12
- Programming and Debugging Support
  13
- Applications
  13
- Part Numbers and Pinout Diagrams
  14
- Figure 1-1 Device Pin Assignments
  14
- Table 1-1 Device Package Names
  15
- Figure 1-2 Part Numbering Reference Guide
  16
- Pin Descriptions
  17
- Table 1-2 Pin Descriptio N
  18
- Architecture
  19
- Introduction
  19
- Figure 2-1 SX28AC Block Diagram
  19
- Program Memory
  20
- Data Memory
  20
- Banks
  20
- Table 2-1 RAM Register Map
  21
- Special-Function Registers
  23
- Table 2-2 Register Summary
  23
- W (Working Register)
  24
- FSR (Indirect through FSR)
  24
- RTCC (Real-Time Clock/Counter)
  24
- PC (Program Counter)
  24
- STATUS (Status Register)
  25
- Table 2-3 STATUS Register Bits
  25
- FSR (File Select Register)
  26
- RA, RB, and RC (Port Data Registers)
  27
- Port Control Registers and MODE Register
  27
- OPTION (Device Option Register)
  27
- Table 2-4 MODE Register Settings
  28
- Table 2-5 Prescaler Divide-By Factors
  29
- Instruction Execution Pipeline
  30
- Clocking Modes
  30
- Table 2-6 Pipeline Execution Sequence
  30
- Pipeline Delays
  31
- Read-Modify-Write Considerations
  31
- Program Counter
  32
- Test and Skip
  32
- Jump Absolute
  32
- Jump Indirect and Jump Relative
  33
- Call
  34
- Figure 2-2 Program Counter Loading for Jump Instruction
  34
- Figure 2-3 Program Counter Loading for Call Instruction
  34
- Return
  35
- Stack
  36
- Table 2-7 Return-From-Subroutine/Interrupt Instructions
  36
- Figure 2-4 Stack Operation for a "Call" Instruction
  37
- Figure 2-5 Stack Operation for a "Return" Instruction
  37
- Device Configuration Options
  38
- Figure 2-6 Device Configuration Register Formats
  38
- Table 2-8 FUSE Word Register Configuration Bits
  39
- Table 2-9 FUSEX Word Register Configuration Bits
  40
- Table 2-10 DEVICE Word Register Configuration Bits (Read-Only)
  41
Chapter 3 Instruction Set

42
- Introduction
  42
- Registers
  42
- Addressing Modes
  43
- Immediate Addressing
  43
- Direct Addressing
  43
- Indirect Addressing
  44
- Instruction Types
  45
- Logic Instructions
  45
- Arithmetic and Shift Instructions
  45
- Bitwise Operation Instructions
  45
- Data Movement Instructions
  46
- Program Control Instructions
  46
- System Control Instructions
  47
- Instruction Summary Tables
  48
- Table 3-1 Logic Instructions
  49
- Table 3-2 Arithmetic and Shift Instructions (Sheet 1 of 2)
  49
- Table 3-3 Bitwise Operation Instructions
  50
- Table 3-4 Data Movement Instructions (Sheet 1 of 2)
  50
- Table 3-5 Program Control Instructions
  52
- Table 3-6 System Control Instructio N
  52
- Equivalent Assembler Mnemonics
  53
- Detailed Instruction Descriptions
  53
- Table 3-7 Equivalent Assembler Mnemonics
  53
- ADD Fr,W
  54
- Table 3-8 Key to Abbreviations and Symbols
  55
- ADD W,Fr
  57
- AND Fr,Wand of Fr and W into Fr
  58
- AND W,Fr and of W and Fr into W
  59
- AND W,#Lit and of W and Literal into W
  60
- BANK Addr8 Load Bank Number into FSR(7:5)
  61
- CALL Addr8 Call Subroutine
  62
- CLR Fr Clear Fr
  64
- CLR WCLR Clear WCLR
  65
- CLR !WDT Clear Watchdog Timer
  66
- 3.7.11 CLRB Fr,Bit
  67
- DEC Fr Decrement Fr
  68
- 3.7.13 DECSZ Fr
  69
- INC Fr Increment Fr
  70
- 3.7.15 INCSZ Fr
  71
- 3.7.16 Iread
  72
- Figure 3-1 Program Counter Loading for Call Instruction
  72
- 3.7.17 JMP Addr9
  74
- 3.7.18 MOV Fr,W
  75
- 3.7.19 MOV M,#Lit
  76
- MOV M,!OPTION,WMOV Move !OPTION,W to MODE Register
  77
- MOV !OPTION,W Move W to OPTION Register
  78
- MOV !Rx,W Move W to Port Rx Control Register
  79
- 3.7.23 MOV W,Fr
  81
- MOV W,/Fr Move Complement of Fr to W
  82
- MOV W,Fr-W Move (Fr-W) to W
  83
- 3.7.26 MOV W,--Fr
  84
- Move (Fr-1) to W
  84
- MOV W,++Fr Move (Fr+1) to W
  84
- MOV W,<<Fr Rotate Fr Left through Carry and Move to W
  86
- MOV W,>>Fr Rotate Fr Right through Carry and Move to W
  87
- MOV W,<>Fr Swap High/Low Nibbles of Fr and Move to W
  88
- 3.7.31 MOV W,#Lit
  89
- MOV W,M Move MODE Register to W
  90
- 3.7.33 MOVSZ W, --Fr
  91
- Move (Fr-1) to W and Skip if Zero
  91
- 3.7.34 MOVSZ W, ++Fr
  92
- NOP no Operation
  93
- NOT Fr Complement of Fr into Fr
  94
- 3.7.37 or Fr,W
  95
- OR W,Fr or of W and Fr into W
  96
- 3.7.39 or W,#Lit
  97
- PAGE Addr12 Load Page Number into STATUS(7:5)
  98
- RET Return from Subroutine
  99
- RETI Return from Interrupt
  100
- RETIW Return from Interrupt and Adjust RTCC with W
  101
- RETP Return from Subroutine Across Page Boundary
  102
- RETW Lit Return from Subroutine with Literal in W
  103
- 3.7.46 RL Fr
  104
- 3.7.47 RR Fr
  105
- 3.7.48 SB Fr,Bit
  106
- 3.7.49 SETB Fr,Bit
  107
- SLEEP Power down Mode
  108
- 3.7.51 SNB Fr,Bit
  109
- 3.7.52 SUB Fr,W
  110
- SWAP Swap High/Low Nibbles of Fr
  112
- TEST Fr Test Fr for Zero
  113
- XOR Fr,Wxor of Fr and W into Fr
  114
- 3.7.56 XOR W,Fr
  115
- XOR W,#Lit XOR of W and Literal into W
  116
Chapter 4 Clocking, Power Down, and Reset

117
- Introduction
  117
- Clocking Options
  117
- Clock/Instruction Rate Option (Compatible or Turbo Mode)
  117
- Internal RC Oscillator
  118
- External RC Oscillator
  118
- External Crystal/Resonator (XT, LP, or HS Mode)
  119
- Figure 4-1 External RC Oscillator Connections
  119
- Figure 4-2 Crystal or Ceramic Resonator Connections
  120
- Table 4-1 Clock Modes and Component Values (Murata Ceramic Resonators)
  121
- Table 4-2 Clock Modes and Component Values (Crystal Oscillators)
  121
- External Clock Signal
  122
- Power down Mode
  122
- Entering the Power down Mode
  122
- Figure 4-3 External Clock Signal Connection
  122
- Waking up from the Power down Mode
  123
- Multi-Input Wakeup/Interrupt
  123
- Port B Configuration for Multi-Input Wakeup/Interrupt
  123
- Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram
  124
- Reading the Wakeup Pending Bits
  125
- Reset
  125
- Register States Upon Reset
  126
- Figure 4-5 On-Chip Reset Circuit Block Diagram
  126
- Table 4-3 Register States Upon Reset
  127
- Power-On Reset
  128
- Figure 4-6 Power-On Reset Timing, Fast VDD Rise Time
  128
- Wakeup from the Power down Mode
  129
- Brown-Out Reset
  129
- Figure 4-7 Power-On Reset Timing, VDD Rise Time too Slow
  129
- Figure 4-8 External Power-On MCLR Signal
  129
- Figure 4-9 Power-On Reset Timing, Separate MCLR Signal
  129
- Watchdog Timeout
  130
- MCLR Input Signal (Master Clear Reset)
  130
- Input/Output Ports 5.1 Introduction
  131
- Reading and Writing the Ports
  131
- Port Configuration
  132
- Accessing the Port Control Registers
  132
- MODE Register
  133
- Table 5-1 MODE Register and Port Control Register Access
  133
- Port Configuration Example
  134
- Port Configuration Registers
  134
- Port Configuration Upon Power-Up
  135
- Port Block Diagram
  135
- Figure 5-1 Port B Pin Block Diagram
  136
- Timers and Interrupts 6.1 Introduction
  137
- Real-Time Clock/Counter
  137
- Prescaler Register
  137
- Maximum Count
  138
- Figure 6-1 RTCC Block Diagram
  138
- RTCC Operation as a Real-Time Clock or Timer
  139
- RTCC Operation as an Event Counter
  139
- RTCC Overflow Interrupts
  139
- Watchdog Timer
  140
- Watchdog Timeout Period
  140
- Watchdog Operation in the Power down Mode
  141
- Interrupts
  141
- Table 6-1 Watchdog Timeout Settings
  141
- Single-Level Interrupt Operation
  142
- Interrupt Sequence
  142
- RTCC Interrupts
  143
- Figure 6-2 Interrupt Logic Block Diagram
  143
- Port B Interrupts
  144
- Return-From-Interrupt Instructions
  144
- Interrupt Example
  145
- Analog Comparator 7.1 Introduction
  146
- Comparator Enable/Status Register (CMP_B)
  146
- Accessing the CMP_B Register
  147
- Comparator Operation
  147
- Figure 7-1 Comparator Block Diagram
  148
- Device Programming 8.1 Introduction
  149
- Erasure and Reprogramming
  149
- Standard and Custom Programming Tools
  149
- In-System and Parallel Programming Modes
  149
- In-System Programming (ISP) Mode
  150
- Scenix In-System Programming Implementation
  150
- Entering the ISP Mode
  151
- Figure 8-1 ISP Mode Entry with External Clocking
  151
- Figure 8-2 ISP Mode Entry with the Internal RC Oscillator
  152
- Programming in ISP Mode
  153
- Figure 8-3 ISP Frame
  153
- Figure 8-4 ISP Circuit Block Diagram
  154
- Table 8-1 ISP Commands
  155
- Exiting the ISP Mode
  158
- Parallel Programming Mode
  158
- Parallel Programming Operations
  158
- Commands
  159
- Table 8-2 ISP Commands
  159
- Erasing the Memory
  160
- Figure 8-5 Erase Timing in Parallel Mode
  160
- Figure
  160
- Figure 8-6 Read Timing in Parallel Mode
  161

Advertisement

Related Products

Scenix Categories

Motherboard Controller Microcontrollers

More Scenix Manuals