Page 3 No license of any kind is conveyed by Scenix Semiconductor with respect to its intellectual property or that of others. All information in this document is subject to change without notice.
Page 5 Rotate fr Right through Carry and Move to W . . 87 3.7.30 MOV W,<>fr Swap High/Low Nibbles of fr and Move to W . . 88 SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 8 In-System Programming (ISP) Mode ........150 8.2.1 Scenix In-System Programming Implementation ....150 8.2.2 Entering the ISP Mode .
Page 10 Register States Upon Reset ..................127 Table 5-1 MODE Register and Port Control Register Access ..........133 Table 6-1 Watchdog Timeout Settings ..................141 Table 8-1 ISP Commands ......................155 Table 8-2 ISP Commands ......................159 SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 11: Chapter 1 Overview
Overview Introduction The Scenix SX18AC, SX20AC, and SX28AC are members of the SX family of high-performance 8- bit microcontrollers fabricated with an advanced CMOS process technology. The advanced process, combined with a RISC-based architecture, allows high-speed computation, flexible I/O control, and efficient data manipulation.
Page 12: Cpu Features
The advantage of this architecture is that instruction fetch and memory transfers can be overlapped in a multi-stage pipeline, which means the next instruction can be fetched from program memory while the current instruction is being executed. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 13: Programming And Debugging Support
Multi-tasking, interrupts, and networking • Resonance loops • DRAM drivers • Music and voice synthesis • PPM/PWM output • Delta/Sigma ADC • DTMF generation/detection • PSK/FSK generation/detection SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 14: Part Numbers And Pinout Diagrams
Peripheral Interface Device (PID) and servo control • Video controller Part Numbers and Pinout Diagrams This user’s guide describes the Scenix SX18AC, SX20AC, and SX28AC microcontrollers, which are available in the four pin configurations shown in Figure 1-1. All of these devices are functionally the same, except that the 18-pin and 20-pin devices do not have the port pins RC0 through RC7.
Page 15: Table 1-1 Device Package Names
Figure 1-2. Throughout this manual, the term “SX” refers to all the devices listed in Table 1-1, except where indicated otherwise. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 16: Figure 1-2 Part Numbering Reference Guide
1k word 2k word Pin Count 4k word SceniX 8k word 16k word 24k word 32k word 48k word 64k word Figure 1-2 Part Numbering Reference Guide SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 17: Pin Descriptions
NA = not applicable • TTL = TTL input levels • CMOS = CMOS input levels • ST = Schmitt trigger input • MIWU = Multi-Input Wakeup SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 18: Table 1-2 Pin Descriptio N
Crystal Oscillator Input - External Clock Source Input OSC2/Out CMOS Crystal Oscillator Output – in R/C mode, internally pulled to Vdd through weak pullup Positive Supply Pin Ground Pin SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 19: Architecture
Time Clock/Counter, an analog comparator, power-on and brownout reset control, and Multi-Input Wakeup capability. Figure 2-1 is a block diagram of the device. The SX18AC and SX20AC have the same features, except that they have two rather than three I/O ports. RTCC...
Page 20: Program Memory
The 5-bit register addresses along the left side are shown as they are written in the syntax of the SX assembly language, using a dollar sign ($) indicating the beginning of a hexadecimal value. Inside the table, the register addresses are shown as 8-bit hexadecimal values. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 21: Table 2-1 Ram Register Map
Bank 6 Bank 7 INDF INDF INDF INDF INDF INDF INDF INDF RTCC RTCC RTCC RTCC RTCC RTCC RTCC RTCC Status Status Status Status Status Status Status Status SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 22 The total number of general-purpose registers is 24 in Bank 0 (from 08h to 1Fh) and 16 in each of the remaining seven banks (from 10h to 1Fh in each bank), for a total of 136 registers. In the SX18AC and SX20AC, an additional general-purpose register is available at address 08h because there is no Port C register occupying that address.
Page 23: Special-Function Registers
RC (07h) Port C Data Register. In the SX28AC, this register is used to control output sig- nals and read input signals on the RC0-RC7 I/O pins. In the SX18AC and SX20AC, the register at 07h is a general-purpose register.
Page 24: W (Working Register)
This regular sequence is altered in order to perform skips, jumps, and subroutine calls in the application program. For detailed information on program counter operation, see Section 2.6. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 25: Status (Status Register)
11-bit program counter for jump and call instructions. You can set them without affecting the other bits in the STATUS register by using the “page” instruction. For details, see Section 2.6. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 26: Fsr (File Select Register)
The FSR register (address 04h) is the File Select Register used to specify the 3-bit bank number for direct addressing of file registers, or the full 8-bit address for indirect addressing of file registers. The file registers are addressed as follows: SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 27: Ra, Rb, And Rc (Port Data Registers)
The OPTION register sets several device configuration options, mostly related to operation of the Real-Time Clock/Counter. The format of the register is shown below. Upon reset, all bits in this register are set to 1. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 28: Table 2-4 Mode Register Settings
RTCC bit specifies the type of signal edges detected on the RTCC pin. Clear RTE_ES to 0 to detect low-to-high transitions on the RTCC pin. Set RTE_ES to 1 to detect high-to-low transitions on the RTCC pin. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 29: Table 2-5 Prescaler Divide-By Factors
32 (timeout = 0.59 sec) 64 (timeout = 1.17 sec) 128 (timeout = 2.34 sec) For detailed information on the Real-Time Clock/Counter and Watchdog timer, see Chapter SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 30: Instruction Execution Pipeline
In the “compatible” mode, instructions are executed at the rate of one per four clock cycles, and four device clock cycles are required for each instruction cycle. For more information on these clocking modes, see Section 4.2.1. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 31: Pipeline Delays
To ensure predictable results, avoid using two successive read-modify-write instructions that access the same port data register. For example, you can insert a “nop” instruction between two such instructions in the program. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 32: Program Counter
“JMP addr9” instruction as 1E0h, and the upper two bits are obtained from the PA1 and PA0 bits (bits 6 and 5) in the STATUS register, both of which are set to 1 prior to the “jmp” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 33: Jump Indirect And Jump Relative
256-word segment in the program memory. This is because you can only modify the lower eight bits of the 11-bit program counter. To jump across a 256-word boundary, use the “PAGE addr12” and “JMP addr9” instructions. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 34: Call
Figure 2 -2 Program Counter Loading for Jump Instruction STATUS REGISTER 8-BIT VALUE IN CALL INSTRUCTION ZERO PROGRAM COUNTER BITS 10:8 OF PC (7:0) PROGRAM COUNTER Figure 2-3 Program Counter Loading for Call Instruction SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 36: Stack
Therefore, the program stack is not directly accessible to the program and is not used for any purpose other than to save and restore program memory addresses, which is done implicitly by “call” and “return” instructions. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 37: Figure 2-4 Stack Operation For A "Call" Instruction
The stack is not used for interrupt processing and is therefore not involved in the return-from-interrupt instructions (RETI and RETIW). For information on interrupt processing, see Chapter SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 38: Device Configuration Options
DEVICE Word (Hard-Wired Read-Only) Res. Res. Res. Res. Res. Res. Res. Res. RAM1 RAM0 MEM1 MEM0 Bit 11 Bit 0 Figure 2 -6 Device Configuration Register Formats SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 39: Table 2-8 Fuse Word Register Configuration Bits
00 = LP – low-power crystal 01 = HS – high-speed crystal 10 = XT – normal crystal 11 = RC network – OSC2 is weakly pulled high and no CLKOUT output SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 40: Table 2-9 Fusex Word Register Configuration Bits
To do so, use one the following MEM1:MEM0 settings: 00 = 1 page, 1 bank 01 = 1 page, 2 banks 10 = 4 pages, 4 banks 11 = 4 pages, 8 banks (default) SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 41: Table 2-10 Device Word Register Configuration Bits (Read-Only)
MEM0 program memory in the device: 00 = 512 words 01 = 1024 words 10 = 2048 words (actual setting for this device) 11 = 4096 words SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 42: Chapter 3 Instruction Set
Instruction Set Introduction The Scenix SX microcontrollers use a RISC (Reduced Instruction Set Computer) architecture. In this type of architecture, the instruction set is limited in complexity and diversity, but the instructions can be executed very fast, typically at a rate of one instruction per clock cycle. High performance is achieved by executing many simple instructions very fast.
Page 43: Addressing Modes
4 in FSR whenever you set it to select Bank 1 through Bank 7, so that FSR contains a valid register address (in the upper half of the bank). For example: SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 45: Instruction Types
3.4.3 Bitwise Operation Instructions There are four bitwise operation instructions: • “setb” sets a single bit to 1 in a data register without affecting other bits SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 46: Data Movement Instructions
;program execution continues here If the carry bit is set to 1, the “jmp” instruction is executed and program execution continues where the “do_carry” label appears in the program. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 47: System Control Instructions
All of these instructions take one clock cycle for execution, except in the case of the “iread” instruction in the “turbo” device clocking mode, which takes four clock cycles. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 48: Instruction Summary Tables
The detailed instruction descriptions in Section 3.6 fully explain the operation of each instruction, including the flags affected, the number of cycles required for execution, and usage examples. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 49: Table 3-1 Logic Instructions
Increment fr and Skip if 1 or 1 or none 0011 111f ffff Zero 2 (skip) 2 (skip) RL fr Rotate fr Left through Carry 0011 011f ffff SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 50: Table 3-3 Bitwise Operation Instructions
Move Complement 0010 010f ffff of fr to W MOV W,--fr Move (fr-1) to W 0000 110f ffff MOV W,++fr Move (fr+1) to W 0010 100f ffff SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 51 0000 0000 0fff Control Register MOV !OPTION, W Move W to none 0000 0000 0010 OPTION Register TEST fr Test fr for Zero 0010 001f ffff SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 52: Table 3-5 Program Control Instructions
Read Word from Instruc- none 0000 0100 0001 tion Memory PAGE addr12 Load Page Number into none 0000 0001 0nnn STATUS(7:5) SLEEP Power Down Mode TO, PD 0000 0000 0011 SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 53: Equivalent Assembler Mnemonics
Each description starts on a new page of the manual. The heading at the top of the page shows the syntax of the command and a brief description of what the command does. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 54: Add Fr,W
These additional assembler mnemonics are beyond the scope of this section. For more information, see the documentation provided with the assembler. Table 3-8 is a quick reference to the abbreviations and symbols used in the instruction descriptions. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 55: Table 3-8 Key To Abbreviations And Symbols
Logical AND <> Swap high and low nibbles (4-bit segments) << Rotate left through carry flag >> Rotate right through carry flag Decrement file register Increment file register SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 56 81h, into the file register; and clears the C and Z flags. It sets the DC flag because of the carry from bit 3 to bit 4. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 57: Add W,Fr
7, and clears the DC flag because there is no carry from bit 3 to bit 4. The Z flag is cleared because the result is nonzero. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 58: And Fr,Wand Of Fr And W Into Fr
13h. The instruction takes the logical AND of 0Fh and 13h and writes the result, 03h, into the same file register. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 59: And W,Fr And Of W And Fr Into W
13h. The instruction takes the logical AND of 0Fh and 13h and writes the result, 03h, into W. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 60: And W,#Lit And Of W And Literal Into W
For example, suppose that W contains the value 50h. The instruction takes the logical AND of this value with 0Fh and writes the result, 00h, into W. The result is zero, so the Z flag is set. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 61: Bank Addr8 Load Bank Number Into Fsr(7:5)
Cycles: Example: bank ;select bank 7 This example writes the three high-order bits of FSR with 111, which selects Bank 7 for subsequent data memory access instructions. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 62: Call Addr8 Call Subroutine
When the “ret” instruction is executed, the 11-bit program address saved on the stack is popped and restored to the program counter, which causes the program to continue with the instruction immediately following the “call” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 63 STATUS register must contain the two high-order bits of the subroutine address prior to the “call” instruction. This is the purpose of the “page” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 64: Clr Fr Clear Fr
This instruction clears the specified file register to zero. It also sets the Z flag un- conditionally. Cycles: Example: This example clears file register 0Ah to 00h and sets the Z flag. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 65: Clr Wclr Clear Wclr
Description: This instruction clears W, the working register. It also sets the Z flag. Cycles: Example: This example clears W to 00h and sets the Z flag. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 66: Clr !Wdt Clear Watchdog Timer
Watchdog reset. Cycles: Example: !WDT This example clears the Watchdog Timer counter and the Watchdog prescaler register to zero; and sets the Z, TO, and PD flags. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 67: 3.7.11 Clrb Fr,Bit
The file register address (00h through 1Fh) and the bit number (0 through 7) are the instruction operands. Cycles: Example: clrb $1F.7 This example clears the most significant bit of file register 1Fh. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 68: Dec Fr Decrement Fr
If the file register contains 01h, it is decremented to 00h and the Z flag is set. Otherwise, the flag is cleared. If the file register contains 00h, it is decremented to FFh. Cycles: Example: This example decrements file register 18h. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 69: 3.7.13 Decsz Fr
The “decsz” instruction decrements file register 18h. If the result is nonzero, execution proceeds normally with the “jmp” instruction. If the result is zero, the device skips the “jmp” instruction and proceeds with the “mov” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 70: Inc Fr Increment Fr
If the file register contains FFh and is incremented to 00h, the Z flag is set. Otherwise, the flag is cleared. Cycles: Example: This example increments file register 18h. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 71: 3.7.15 Incsz Fr
The “incsz” instruction increments file register 18h. If the result is nonzero, execution proceeds normally with the “jmp” instruction. If the result is zero, the device skips the “jmp” instruction and proceeds with the “mov” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 72: 3.7.16 Iread
Upper 3 bits Lower 8 bits MODE Program Register Memory Register Upper 4 bits Lower 8 bits Program Data Figure 3-1 Program Counter Loading for Call Instruction Cycles: SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 73 380h. The program then stores the lower eight bits of the result into file register 0Eh and the upper four bits of the result into file register 0Fh. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 74: 3.7.17 Jmp Addr9
The PA1:PA0 bits of the STATUS register must contain the two high-order bits (bits 10 and 9) of the “overflo” routine address prior to the “jump” instruction. This is the purpose of the “page” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 75: 3.7.18 Mov Fr,W
;select Bank 7 $10,W ;move W to reg. 10h in Bank 7 This example moves the contents of W into file register 10h in Bank 7. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 76: 3.7.19 Mov M,#Lit
;disable all pullups for B0-B7 W,#$00 ;W = 0000 0000 !RC,W ;enable all pullups for C0-C7 This example sets the pullup configuration for Ports A, B, and C. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 77: Mov M,!Option,Wmov Move !Option,W To Mode Register
;move value from file reg 0Bh to W ;move W into MODE register This example moves a value from file register 0Bh to W, and then from W into the MODE register. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 78: Mov !Option,W Move W To Option Register
RTCC interrupt enable, RTCC increment event control, and prescaler as- signment. Cycles: Example: W,#$3F ;load W with 3Fh !OPTION,W ;write value to OPTION register This example moves programs the OPTION register with the value 3Fh. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 79: Mov !Rx,W Move W To Port Rx Control Register
5 to operate as high-impedance inputs and pins 6 and 7 to operate as outputs. The last two instructions configure all Port C pins to operate as inputs. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 80 ;enables comparator and its output pin This example enables the comparator and its output pin. The “mov !RB,W” instruction does an exchange of data between the CMP_B register and W. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 81: 3.7.23 Mov W,Fr
This example moves the contents of file register 1Eh in Bank 1 into W. The Z flag is set if the value is zero or cleared if the value is nonzero. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 82: Mov W,/Fr Move Complement Of Fr To W
75h, the complement of this value, 8Ah, is loaded into W, and the Z flag is cleared. The file register still contains 75h after execution of the instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 83: Mov W,Fr-W Move (Fr-W) To W
06h from 35h and writes the result, 2Fh, into W. It also sets the C flag, clears the DC flag, and clears the Z flag. The file register still contains 35h after execution of the instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 84: 3.7.26 Mov W,--Fr
For example, if the file register contains 75h, the value 74h is loaded into W, and the Z flag is cleared. The file register still contains 75h after execution of the instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 85 For example, if the file register contains 75h, the value 76h is loaded into W, and the Z flag is cleared. The file register still contains 75h after execution of the instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 86: Mov W,<
W will contain 29h and the C flag will be cleared to 0. The file register will still contain 14h after execution of the instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.

Page 87: Mov W,>>Fr Rotate Fr Right Through Carry And Move To W
W will contain 89h and the C flag will be cleared to 0. The file register will still contain 12h after execution of the instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 88: Mov W,<>Fr Swap High/Low Nibbles Of Fr And Move To W
This example swaps the high-order and low-order nibbles of the value in file register 0Bh and move the result into W. For example, if the file register contains A5h, after executing this instruction, W will contain 5Ah. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 89: 3.7.31 Mov W,#Lit
This instruction loads an 8-bit literal value (a value specified within the instruction) into W. Cycles: Example: W,#$75 This example loads the immediate value 75h into W. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 90: Mov W,M Move Mode Register To W
$10,W ;save value to file register 10h This example moves the contents of the MODE register into W, and then stores that value into file register 10h. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 91: 3.7.33 Movsz W, --Fr
W. If the result is zero, the device skips the “ret” instruction and proceeds with the “nop” instruction. If the result is nonzero, the device executes the “ret” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 92: 3.7.34 Movsz W, ++Fr
W. If the result is zero, the device skips the “ret” instruction and proceeds with the “nop” instruction. If the result is nonzero, the device executes the “ret” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 93: Nop No Operation
This example shows how a “nop” instruction can be used as a one-cycle delay between two successive read-modify-write instructions that modify the same I/O port. This delay ensures reliable results at high clock rates. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 94: Not Fr Complement Of Fr Into Fr
Suppose that W contains the value 1Ch. This instruction takes the complement of 1Ch and writes the result, E3h, into the same register. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 95: 3.7.37 Or Fr,W
13h. The instruction takes the logical OR of 0Fh and 13h and writes the result, 1Fh, into the same file register. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 96: Or W,Fr Or Of W And Fr Into W
13h. The instruction takes the logical OR of 0Fh and 13h and writes the result, 1Fh, into W. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 97: 3.7.39 Or W,#Lit
For example, suppose that W contains the value 50h. The instruction takes the logical OR of this value with 0Fh and writes the result, 5Fh, into W. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 98: Page Addr12 Load Page Number Into Status(7:5)
This example sets the PA2:PA0 bits in the STATUS register to 010. This means that the subsequent “call” instruction calls a subroutine that starts in page 2 of program memory (somewhere in the address range of 400h to 5FFh). SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 99: Ret Return From Subroutine
When the “ret” instruction is executed, the saved program address is popped from the stack and restored to the 11-bit program counter, which causes the program to continue with the instruction immediately following the “call” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 100: Reti Return From Interrupt
The “reti” instruction restores the contents of the program counter and the W STATUS, and FSR registers. This causes the device to continue program execution at the point where the program was interrupted. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 101: Retiw Return From Interrupt And Adjust Rtcc With W
;interrupt service routine at address 000h ;check RTCC ;check interrupt pending bits ;perform interrupt service ;check RTCC ;put adjustment value into W retiw ;return from interrupt and adjust RTCC SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 102: Retp Return From Subroutine Across Page Boundary
PA1:PA0 bits are automatically returned to their original values (PA1:PA0 = 00), allowing a subsequent same-page call to be done without using the “page” instruction again. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 103: Retw Lit Return From Subroutine With Literal In W
0 to 7. The subroutine adds the contents of W to the program counter, which advances the program to the applicable “RETW lit” instruction. The “RETW lit” instruction returns from the subroutine with the appropriate result in W. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 104: 3.7.46 Rl Fr
This example multiplies file register 18h by 4. The initial “clrb” instruction clears the C flag, which ensures that 0 will be shifted into the least significant bit position. The two “rl” instructions perform two successive multiply-by-2 operations. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 105: 3.7.47 Rr Fr
This example divides file register 0Fh by 4. The “clrb” instructions ensure that 0 will be shifted into the most significant bit positions. The two “rr” instructions perform two divide-by-2 operations. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 106: 3.7.48 Sb Fr,Bit
This example tests the most significant bit of file register 1Fh. If that bit is 1, the “inc” instruction is skipped. Otherwise, program execution proceeds normally with the “inc” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 107: 3.7.49 Setb Fr,Bit
The file register address (00h through 1Fh) and the bit number (0 through 7) are the instruction operands. Cycles: Example: setb $1F,7 This example sets the most significant bit of file register 1Fh. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 108: Sleep Power Down Mode
Watchdog timer overflow, a transition on a Multi-Input Wakeup pin, or an external reset on the MCLR pin. Cycles: Example: sleep This example puts the device into the power down mode until a wakeup event occurs. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 109: 3.7.51 Snb Fr,Bit
This example tests bit number 5 of file register 1Fh. If that bit is 0, the “dec” instruction is skipped. Otherwise, program execution proceeds normally with the “dec” instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 110: 3.7.52 Sub Fr,W
;load W from 0Ah (low-order byte) sub $0C,W ;low-order subtraction, C=0 for borrow out mov W,$0B ;load W from 0Bh (high-order byte) sub $0D,W ;high-order subtraction, borrow in & out SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 112: Swap Swap High/Low Nibbles Of Fr
This example swaps the high-order and low-order nibbles of file register 0Bh. For example, if the register contains A5h, after executing this instruction, the register will contain 5Ah. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 113: Test Fr Test Fr For Zero
Z flag based on the contents of the file register. The “sb” instruction tests the Z flag. The “inc” instruction is executed if the file register contains zero or is skipped if the file register contains a nonzero value. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 114: Xor Fr,Wxor Of Fr And W Into Fr
13h. The instruction takes the logical XOR of 0Fh and 13h and writes the result, 1Ch, into the same file register. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 115: 3.7.56 Xor W,Fr
13h. The instruction takes the logical XOR of 0Fh and 13h and writes the result, 1Ch, into W. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 116: Xor W,#Lit Xor Of W And Literal Into W
For example, suppose that W contains the value 51h. The instruction takes the logical XOR of this value with 0Fh and writes the result, 5Eh, into W. The result is nonzero, so the Z flag is cleared. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 117: Chapter 4 Clocking, Power Down, And Reset
In the “compatible” mode, the instruction rate is one-fourth of the clock rate. In this configuration, you need to select a clock rate four times higher than the intended instruction rate. For example, if you want SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 118: Internal Rc Oscillator
Figure 4-1 shows how the resistor and capacitor are connected to the device. The operating frequency can be adjusted by choosing the values for R and C. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 119: External Crystal/Resonator (Xt, Lp, Or Hs Mode)
With the SX device configured in one of these modes, the crystal or ceramic resonator is connected to the OSC1 and OSC2 pins as shown in Figure 4-2. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 120: Figure 4-2 Crystal Or Ceramic Resonator Connections
Note that the LP (low-power) mode is not shown in the tables because it is used only at lower frequencies, in the range of 32 kHz to 100 kHz. For operation at these lower frequencies, contact Scenix Semiconductor for more information. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 121: Table 4-1 Clock Modes And Component Values (Murata Ceramic Resonators)
36 MHz 5 pF 15 pF 3.3 kΩ 40 MHz 5 pF 15 pF 3.3 kΩ 50 MHz 5 pF 10 pF 3.3 kΩ RS = 0 SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 122: External Clock Signal
If the Watchdog timer is enabled, the “sleep” instruction sets the TO (Watchdog Timeout) bit to 1 and clears the PD (Power Down) bit to 0 in the STATUS register. The Watchdog timer continues to operate SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 123: Waking Up From The Power Down Mode
RB Data Direction register • WKEN_B (Port B Wakeup Enable register) • WKED_B (Port B Wakeup Edge Select register) • WKPND_B (Port B Wakeup Pending Flag register) SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 124: Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram
You must explicitly enable any pins that you want to use as wakeup/interrupt pins. Here is an example of a program segment that configures the RB0, RB1, and RB2 pins to operate as Multi-Input Wakeup/Interrupt pins, sensitive to falling edges: SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 125: Reading The Wakeup Pending Bits
A reset operation puts the SX device into a known initial state. A reset occurs upon any one of the following conditions: • initial power-up • wakeup from the power down mode SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 126: Register States Upon Reset
Each entry in the table shows the state of the register just after the applicable reset operation. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 127: Table 4-3 Register States Upon Reset
1. Watchdog reset during SLEEP mode: 00 Watchdog reset during Active mode: 01 NOTE: 2. External reset during SLEEP mode: 10 External reset during Active mode: Unchang SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 128: Power-On Reset
The power-on timing with the external RC network is shown in Figure 4-9. In this case, the device comes out of reset about 72 msec after the MCLR input goes high. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 129: Wakeup From The Power Down Mode
When the supply voltage to the SX device drops below a specified value but remains above zero volts, it is called a “brown-out” condition. The SX device has a brown-out detection circuit that puts the SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 131: Input/Output Ports 5.1 Introduction
Schmitt-trigger input characteristics. The SX28AC has three ports, designated Port A, Port B, and Port C. The SX18AC and SX20AC have Port A and Port B, but no Port C. The three ports share many of the same features, but have some characteristics that vary from port to port: •...
Page 132: Port Configuration
You set the configuration of a port by writing to a set of control registers associated with the port. A special-purpose instruction is used to write these control registers: • mov !RA,W (move W to Port A control register) SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 133: Mode Register
MODE register again. For example, you can write the value 0Eh to the MODE register just once, and then write to each of the three pullup configuration registers using the three “mov !rx,W” instructions shown at the top of Table 5-1. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 134: Port Configuration Example
Each register bit determines whether the port input pin operates with a Schmitt trigger. Set the bit to 1 to disable Schmitt trigger operation and sense either TTL or CMOS voltage levels; or clear the bit to 0 to enable Schmitt trigger operation. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 135: Port Configuration Upon Power-Up
MODE register; while the RB Data register bit is accessed by ordinary file register instructions such as “mov fr,W”. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 136: Figure 5-1 Port B Pin Block Diagram
Port A and Port C, with one exception. Port A does not offer a Schmitt trigger input option, so it lacks the control register bit and logic associated with the Schmitt trigger buffer. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 137: Timers And Interrupts 6.1 Introduction
The 8-bit prescaler register is shared between the Watchdog timer and RTCC circuit. It can be configured to operate as a prescaler for the RTCC circuit or as a postscaler for the Watchdog timer, but SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 138: Maximum Count
To enable this interrupt, clear the RTE_IE bit in the OPTION register. You can have the interrupt service routine increment a file register (or a set of cascaded file registers), and thereby keep track of any number of instruction cycles or events. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 139: Rtcc Operation As A Real-Time Clock Or Timer
There is no interrupt pending flag associated with RTCC rollover interrupts like there is for each of the Multi-Input Wakeup interrupts. Therefore, the interrupt service routine should read the RTCC register SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 140: Watchdog Timer
Watchdog timeout period by a factor determined by the PS2:PS0 bits in the OPTION register. Table 6-1 lists the PS2:PS0 settings and the corresponding divide-by factors and timeout periods. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 141: Watchdog Operation In The Power Down Mode
Real-Time Clock/Counter (RTCC) • an interrupt signal received on a Port B input pin that has been configured for Multi-Input Wake- up/Interrupt operation SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 142: Single-Level Interrupt Operation
If an interrupt condition occurred during the service routine, it immediately triggers a new interrupt at this time. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 143: Rtcc Interrupts
You can configure the RTCC circuit to count instruction cycles or external events, and you can specify the number of cycles or events that cause the RTCC counter to be incremented. For details, see Section 6.2. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 144: Port B Interrupts
To use this feature, the interrupt service routine should check the RTCC register at the beginning of the routine and again at the end of the routine, and then put the adjustment value into W before executing the RETIW instruction. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 145: Interrupt Example
;RTCC interrupt service routine here reti ;return from interrupt rb0_i ;RB0 interrupt service routine here reti ;return from interrupt rb1_i ;RB1 interrupt service routine here reti ;return from interrupt SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 146: Analog Comparator 7.1 Introduction
A “1” indicates that the voltage on RB2 is greater than the voltage on RB1, and a “0” indicates the opposite. The comparator must be already enabled ( CMP_EN bit cleared to 0) in order to read a valid result. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 147: Accessing The Cmp_B Register
The comparator takes some time to respond after it is enabled and after a change in the analog input voltages. For details, see the comparator DC and AC specifications in Appendix C. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 148: Figure 7-1 Comparator Block Diagram
Chapter 7 Analog Comparator Internal Data Bus CMP_B CMP_EN CMP_OE MODE MODE = 08h CMP_RES Point to CMP_B Figure 7 -1 Comparator Block Diagram SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 149: Device Programming 8.1 Introduction
"parallel" mode. The In-System Programming mode uses just two device pins, OSC1, and OSC2, and writes the data to the device serially, one bit at a time. This mode lets you program devices that are SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 150: In-System Programming (Isp) Mode
8.2.1 Scenix In-System Programming Implementation The Scenix ISP method is a proprietary system that uses just two device pins: the clock input pin, OSC1, and the clock output pin, OSC2 (VDD, and GND, and MCLR pins should be connected properly). This system eliminates the need for dedicated programming pins, thus reducing the total device pin count.
Page 151: Entering The Isp Mode
Chapter 8 Device Programming www.scenix.com There are three stages to the Scenix ISP protocol: • Entering the ISP Mode • Programming in ISP Mode • Exiting the ISP Mode 8.2.2 Entering the ISP Mode For normal operation of the SX device, the OSC2 pin is either left unconnected, connected to passive components, or used as a clock output pin, depending on the chosen clock configuration.
Page 152: Figure 8-2 Isp Mode Entry With The Internal Rc Oscillator
3. Apply the VPP programming voltage to the OSC1 pin. The SX internal RC oscillator starts op- erating at 128 kHz. This clock drives the SX device during ISP mode programming. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 153: Programming In Isp Mode
4 ' h 7 s e e d 4 ' h e Figure 8 -3 ISP Frame Each of the 17 cycles consists of four internal clock periods. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 154: Figure 8-4 Isp Circuit Block Diagram
When the command is to read data from the program memory, the data bits are read from the EEPROM block and shifted out on the OSC2 pin during the data cycles. An open-drain transistor and a pullup SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 155: Table 8-1 Isp Commands
No repetition is necessary to read a register or to increment the memory address pointer. You can complete one of these operations in just a single frame. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 156 The programmer unit should always read the FUSEX word before erasure and restore the five highest- order bits of that register after erasure. These bits have factory-set values that must be maintained. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 157 FFFh (the FUSE word register), followed by 000h, 001h, 002h, and so on up to the top memory address, 7FFh. The programmer can skip over any number of memory locations by repeating the "Increment Address" command consecutively SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 158: Exiting The Isp Mode
After the device has been put in the parallel programming mode, you use the port pins to read and write data, the RTCC pin to control the timing of programming operations, and the OSC1 pin to increment the address pointer. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 159: Commands
To determine the minimum required time, look in the Electrical Characterization appendix and find the time requirement for that particular operation. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 160: Erasing The Memory
1. If the power is not already on, apply normal power to the Vdd pin while holding the MCLR pin low. 2. Apply a logic high signal to the RTCC pin. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 161: Figure 8-6 Read Timing In Parallel Mode
1. If the power is not already on, apply normal power to the Vdd pin while holding the MCLR pin low. 2. Apply a logic high signal to the RTCC pin. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 162 ≥ 100 ns ≥ 1 µ s Power on Reset ≥ 100 ms OSC1 RST (internal) Address FUSE word address FFF (internal) Figure 8-7 Program Timing in Parallel Mode SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 163 OSC1 signal. Because you access only one register with each command, you just leave the OSC1 pin low during the read or write procedure. SX User’s Manual Rev. 1.0 © 1998 Scenix Semiconductor, Inc. All rights reserved.
Page 164 (516) 543-0510 (516) 543-0758 (fax) For the latest contact and support information on SX devices, please visit the Scenix Semiconductor website at www.scenix.com. The site contains technical literature, local sales contacts, tech support and many other features. Scenix Semiconductor, Inc.

This manual is also suitable for:

Sx20ac Sx28ac

Scenix SX18AC User Manual

Chapter 1 Overview

Chapter 3 Instruction Set

Chapter 4 Clocking, Power Down, and Reset

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Scenix SX18AC

Summary of Contents for Scenix SX18AC