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Manuals and User Guides for Scenix SX28AC75. We have
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Scenix SX28AC75 manual available for free PDF download: User Manual
Scenix SX28AC75 User Manual (174 pages)
Communications Controller
Brand:
Scenix
| Category:
Controller
| Size: 1 MB
Table of Contents
Table of Contents
5
Chapter 1 Overview
13
Introduction
13
Key Features
13
Architecture
15
The Virtual Peripheral Concept
15
The Communications Controller
16
Programming and Debugging Support
16
Applications
16
Part Numbers and Pinout Diagrams
17
Figure 1-1 SX18/20/28 Pin Assignments
17
Figure 1-2 SX48/52BD Pin Assignments
18
Table 1-1 Device Package Names
19
Figure 1-3 Part Numbering Reference Guide
20
Pin Descriptions
21
Table 1-2 Pin Descriptions
22
Chapter 2 Architecture
23
Introduction
23
Figure 2-1 SX28AC Block Diagram
23
Program Memory
24
Data Memory
24
Banks
24
SX18/20/28AC and SX18/20/28AC75 Addressing Modes and FSR Register
25
Table 2-1 SX18/20/28AC and SX18/20/28AC75 RAM Register Map
26
SX48/52BD Addressing Modes and FSR Register
27
Figure 2-2 Register Access Modes
29
Register Access Examples
30
Special-Function Registers
31
Table 2-2 Register Summary
32
INDF (Indirect through FSR)
33
PC (Program Counter)
33
RTCC (Real-Time Clock/Counter)
33
W (Working Register)
33
STATUS (Status Register)
34
Table 2-3 STATUS Register Bits
34
FSR (File Select Register)
36
Port Control Registers and MODE Register
36
RA through RE (Port Data Registers)
36
Table 2-4 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75
37
Table 2-5 MODE Register Settings for SX48/52BD
38
OPTION (Device Option Register)
39
Table 2-6 Prescaler Divide-By Factors
40
Instruction Execution Pipeline
41
Clocking Modes
41
Table 2-7 Pipeline Execution Sequence
41
Pipeline Delays
42
Read-Modify-Write Considerations
42
Program Counter
43
Test and Skip
43
Jump Absolute
43
Jump Indirect and Jump Relative
44
Call
45
Figure 2-3 Program Counter Loading for Jump Instruction
45
Figure 2-4 Program Counter Loading for Call Instruction
45
Return
46
Stack
47
Table 2-8 Return-From-Subroutine/Interrupt Instructions
47
Figure 2-5 Stack Operation for a "Call" Instruction
48
Figure 2-6 Stack Operation for a "Return" Instruction
48
Device Configuration Options
49
Figure 2-7 Device Configuration Register Formats
50
Table 2-9 FUSE Word Register Configuration Bits for SX18/20/28AC
51
Table 2-10 FUSEX Word Register Configuration Bits for SX18/20/28AC & SX18/20/28AC75
53
Table 2-11 FUSE Word Configuration Bits for SX48/52BD
54
Table 2-12 FUSEX Word Register Configuration Bits for SX48/52BD
56
Chapter 3 Instruction Set
57
Introduction
57
Instruction Operands
57
Instruction Types
58
Logic Instructions
58
Arithmetic and Shift Instructions
58
Bitwise Operation Instructions
59
Data Movement Instructions
59
Program Control Instructions
59
System Control Instructions
61
Instruction Summary Tables
61
Table 3-1 Logic Instructions
62
Table 3-2 Arithmetic and Shift Instructions
62
Table 3-3 Bitwise Operation Instructions
63
Table 3-4 Data Movement Instructions
63
Table 3-5 Program Control Instructions
65
Table 3-6 System Control Instructions
65
Equivalent Assembler Mnemonics
66
Detailed Instruction Descriptions
66
Table 3-7 Equivalent Assembler Mnemonics
66
ADD Fr,W
67
Table 3-8 Key to Abbreviations and Symbols
68
ADD W,Fr
70
AND Fr,Wand of Fr and W into Fr
71
AND W,Fr and of W and Fr into W
72
AND W,#Lit and of W and Literal into W
73
BANK Addr8
74
CALL Addr8
76
Clear Fr
78
CLR W Clear W
79
Clr !Wdt
80
CLRB Fr.bit
81
DEC Fr
82
DECSZ Fr
83
INC Fr
84
INCSZ Fr
85
Iread
86
Figure 3-1 Program Counter Loading for Call Instruction
86
JMP Addr9
88
MOV Fr,W
89
MOV M,#Lit
90
MOV M,W Move W to MODE Register
91
Mov !Option,W
92
MOV !Rx,W Move Data between W and Control Register
93
MOV W,Fr
95
MOV W,/Fr Move Complement of Fr to W
96
MOV W,/Fr
96
Move (Fr-1) to W
98
MOV W,++Fr
99
Figure 3-2 Rotate Fr Left through Carry into W
100
Figure 3-3 Rotate Fr Right through Carry into W
101
Mov W,M
104
MOVSZ W, --Fr
105
Move (Fr-1) to W and Skip if Zero
105
MOVSZ W, ++Fr
106
NOP no Operation
107
NOT Fr
108
OR Fr,W
109
OR W,Fr
110
OR W,#Lit
111
RET Return from Subroutine
113
Reti
114
Retp
116
RL Fr
118
Figure 3-4 Rotate Fr Left through Carry
118
RR Fr
119
Figure 3-5 Rotate Fr Right through Carry
119
SB Fr.bit
120
SETB Fr.bit
121
Sleep
122
SNB Fr.bit
123
SUB Fr,W
124
SWAP Fr Swap High/Low Nibbles of Fr
126
TEST Fr
127
XOR Fr,W
128
XOR W,Fr
129
XOR W,#Lit
130
Chapter 4 Clocking, Power Down, and Reset
131
Introduction
131
Clocking Options
131
Clock/Instruction Rate Option (Compatible or Turbo Mode)
131
Internal RC Oscillator
132
External RC Oscillator
132
External Crystal/Resonator (XT, LP, or HS Mode)
133
Figure 4-1 External RC Oscillator Connections
133
External Clock Signal
134
Figure 4-2 Crystal or Ceramic Resonator Connections
134
Power down Mode
135
Entering the Power down Mode
135
Figure 4-3 External Clock Signal Connection
135
Waking up from the Power down Mode
136
Multi-Input Wakeup/Interrupt
136
Port B Configuration for Multi-Input Wakeup/Interrupt
136
Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram
137
Reading and Writing the Wakeup Pending Bits
139
Reset
140
Register States Upon Different Resets
140
Figure 4-5 On-Chip Reset Circuit Block Diagram
140
Table 4-1 Register States Upon Different Resets
141
Power-On Reset
142
Figure 4-6 Power-On Reset Timing, Fast VDD Rise Time
142
Wakeup from the Power down Mode
143
Figure 4-7 Power-On Reset Timing, VDD Rise Time too Slow
143
Figure 4-8 External Power-On MCLR Signal
143
Figure 4-9 Power-On Reset Timing, Separate MCLR Signal
143
Brown-Out Reset
144
Watchdog Timeout
144
MCLR Input Signal (Master Clear Reset)
144
Chapter 5 Input/Output Ports
145
Introduction
145
Reading and Writing the Ports
145
Port Configuration
146
Accessing the Port Control Registers
147
MODE Register
147
Table 5-1 MODE Register Settings for SX18/20/28AC and SX18/20/28AC75
148
Table 5-2 MODE Register Settings for SX48/52BD
148
Port Configuration Example
149
Port Configuration Registers
149
Port Configuration Upon Reset
151
Port Block Diagram
151
Figure 5-1 Port B Pin Block Diagram
152
Chapter 6 Timers and Interrupts
153
Introduction
153
Real-Time Clock/Counter
153
Prescaler Register
154
Maximum Count
154
Figure 6-1 RTCC Block Diagram
154
RTCC Operation as a Real-Time Clock or Timer
155
RTCC Operation as an Event Counter
155
RTCC Overflow Interrupts
155
Watchdog Timer
156
Watchdog Timeout Period
156
Watchdog Operation in the Power down Mode
157
Interrupts
157
Table 6-1 Watchdog Timeout Settings
157
Interrupt Sequence
158
Single-Level Interrupt Operation
158
Figure 6-2 Interrupt Logic Block Diagram
159
Device-Specific Interrupts
160
Port B Interrupts
160
RTCC Interrupts
160
Interrupt Example
161
Return-From-Interrupt Instructions
161
Chapter 7 Analog Comparator
163
Introduction
163
Comparator Enable/Status Register (CMP_B)
163
Accessing the CMP_B Register
164
Comparator Operation
164
Figure 7-1 Comparator Block Diagram
165
Chapter 8 Multi-Function Timers
167
Introduction
167
Figure 8-1 Multi-Function Timer Block Diagram
167
Timer Operating Modes
168
PWM Mode
168
Software Timer Mode
168
External Event Mode
169
Capture/Compare Mode
169
Timer Pin Assignments
170
Timer Control Registers
170
Table 8-1 Timer T1/T2 Pin Assignments
170
Table 8-2 T1CNTA Register Bits
171
Timer T1 Control a Register (T1CNTA)
171
Table 8-3 T1CNTB Register Bits
172
Timer T1 Control B Register (T1CNTB)
172
Table 8-4 T2CNTA Register Bits
173
Timer T2 Control a Register (T2CNTA)
173
Table 8-5 T2CNTB Register Bits
174
Timer T2 Control B Register (T2CNTB)
174
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