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Scenix SX Series User Manual

Communications controller
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Summary of Contents for Scenix SX Series

  • Page 2 Scenix ™ SX Family User’s Manual SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 3 No license of any kind is conveyed by Scenix Semiconductor with respect to its intellectual property or that of others. All information in this document is subject to change without notice.
  • Page 4 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 5: Table Of Contents

    Return ........... . 36 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 6 Move Literal to W ..... . . 101 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 7 Brown-Out Reset ......... . 142 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 8 Comparator Operation ..........162 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 9 Timer T2 Control B Register (T2CNTB) ..... . . 172 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 10 Multi-Function Timer Block Diagram ....... . 165 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 11 Timer T1/T2 Pin Assignments ..................168 Table 8-2 T1CNTA Register Bits .....................169 Table 8-3 T1CNTB Register Bits ....................170 Table 8-4 T2CNTA Register Bits .....................171 Table 8-5 T2CNTB Register Bits ....................172 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 12 Contents www.scenix.com SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 13: Chapter 1 Overview

    Chapter 1 Overview Introduction The Scenix SX family of configurable communications controllers are fabricated in an advanced CMOS process technology. The advanced process, combined with a RISC-based architecture, allows high-speed computation, flexible I/O control, and efficient data manipulation. Throughput is enhanced by operating the device at frequencies up to 100 MHz and by optimizing the instruction set to include mostly single-cycle instructions.
  • Page 14 • SX18/2028AC and SX18/20/28AC75: 18pin SO/DIP, 20-pin SSOP, 28-pin SO/DIP • SX48/52BD family: 48-pin Tiny PQFP, and 52-pin PQFP • SX52BD75: 52-pin PQFP • SX52BD100: 52-pin PQFP SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 15: Architecture

    The speed and flexibility of the Scenix architecture complemented with the availability of the Virtual Peripheral library, simultaneously address a wide range of engineering and product development con- cerns.

  • Page 16: The Communications Controller

    • FFT/DFT based algorithms The Communications Controller The combination of the Scenix hardware architecture and the Virtual Peripheral concept create a powerful, creative platform for the communications design communities: SX communications con- troller. Its high processing power, re-cofigurability, cost-effectiveness, and overall design freedom give the designer the power to build products for the future with the confidence of knowing that they can keep up with innovation in standards and other areas.

  • Page 17: Part Numbers And Pinout Diagrams

    Protocol stack, and communication interfaces, that allow design engineers to embed Internet connec- tivity into all of their products at extremely low cost and very little effort. Scenix’s complete network connectivity protocol stack implementation (SX-Stack), enables single- chip Web servers and E-mail appliances in embedded applications. The implementation includes the physical layer interface with the TCP/IP network connectivity protocols, enabling system designers to produce cost-effective embedded Internet devices without external physical access or a gateway PC.

  • Page 18: Figure 1-2 Sx48/52Bd Pin Assignments

    MCLR OSC1 OSC2 52 - PIN PQFP 14 15 16 17 18 19 20 21 22 23 24 25 26 Top View Figure 1-2 SX48/52BD Pin Assignments SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 19: Table 1-1 Device Package Names

    0°C to +70°C SX48BD/TQ 0°C to +70°C SX52BD/PQ 0°C to +70°C SX48BD-I/TQ -40°C to +85°C SX52BD-I/PQ -40°C to +85°C SX52BD75/PQ 0°C to +70°C SX52BD100/PQ 0°C to +70°C SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 20: Figure 1-3 Part Numbering Reference Guide

    4k word Figure 1-3 Part Numbering Reference Guide Throughout this manual, the term “SX” refers to all the devices listed in Table 1-1, except where indicated otherwise. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 21: Pin Descriptions

    NA = not applicable • TTL = TTL input levels • CMOS = CMOS input levels • ST = Schmitt trigger input • MIWU = Multi-Input Wakeup SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 22: Table 1-2 Pin Descriptions

    Crystal oscillator input - external clock source input OSC2/Out CMOS Crystal oscillator output – in R/C mode, internally pulled to Vdd through weak pullup Positive supply pins Ground pins SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 23: Chapter 2 Architecture

    O PT IO N W rite B ack M O D E W rite Data R ead D ata Instruction IR E AD Figure 2-1 SX28AC Block Diagram SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 24: Program Memory

    FSR register or use the “bank” instruction. The “bank” instruction writes the three high-order bits in the FSR register without affecting the other bits in the register. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 25: Sx18/20/28Ac And Sx18/20/28Ac75 Addressing Modes And Fsr Register

    The 5-bit register addresses along the left side are shown as they are written in the syntax of the SX assembly language, using a dollar sign ($) indicating the beginning of a hexadecimal value. Inside the table, the register addresses are shown as 8-bit hexadecimal values. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 26: Table 2-1 Sx18/20/28Ac And Sx18/20/28Ac75 Ram Register Map

    Bank 6 Bank 7 INDF INDF INDF INDF INDF INDF INDF INDF RTCC RTCC RTCC RTCC RTCC RTCC RTCC RTCC Status Status Status Status Status Status Status Status SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 27: Sx48/52Bd Addressing Modes And Fsr Register

    For indirect addressing (fr=00), the File Select Register (FSR) specifies the register to be accessed. FSR is an 8-bit, memory-mapped register (at address 04h) which serves as an 8-bit pointer into data SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 28 Thus, to change from one upper bank to another, only a single “bank” instruction is required. To change from one upper bank to a lower bank, the “bank” instruction must be followed by “setb FSR.7”. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 29: Figure 2-2 Register Access Modes

    FSR are ignored. All 256 registers in Bank 0 through Bank F are accessible. The global registers are not accessible. Semi-Direct Addressing Figure 2-2 Register Access Modes SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 30: Register Access Examples

    Another approach is to set bit 7 of the FSR register individually after the “bank” instruction to address an upper block bank. bank $80 ;set bits in 4, 5, and 6 FSR setb FSR.7 ;select Bank 8 in FSR SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 31: Special-Function Registers

    OPTION register. All of these registers are eight bits wide. Table 2-2 lists and briefly describes the dedicated file registers and non-memory-mapped registers that are accessible to SX instructions. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 32: Table 2-2 Register Summary

    MODE Register. This register controls access to the port control registers when you use the “mov !rx,W” instruction. OPTION Option Register. This register sets some device configuration options such as the Real-Time Clock/Counter incrementing mode. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 33: W (Working Register)

    4,096-word program memory. During regular program execution, the program counter is incremented automatically once per instruction cycle. This regular sequence is altered in order to perform skips, jumps, and subroutine calls in the application program. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 34: Status (Status Register)

    (clear bit) instructions to control the individual bits rather than “mov” (move) instructions to move whole register values. This is because the CPU often modifies the STATUS register bits, possibly resulting in register values that are different from what you expect. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 35 This option is controlled by the CF bit in the FUSEX Word (a word that is programmed at the same time as the program memory). An implicit addition of the C bit can be used to implement multiple-byte addition and subtraction algorithms. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 36: Fsr (File Select Register)

    On the SX18/20/28AC and SX18/20/28AC75 devices, the port control registers are write-only registers, and bit 4 of the MODE register is a “don’t care” bit. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 37: Table 2-4 Mode Register Settings For Sx18/20/28Ac And Sx18/20/28Ac75

    Reg. mov !RA,W mov !RB,W mov !RC,W Exchange CMP_B Exchange WKPND_B WKED_B WKEN_B ST_B ST_C LVL_A LVL_B LVL_C PLP_A PLP_B PLP_C RA Direction RB Direction RC Direction SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 38: Table 2-5 Mode Register Settings For Sx48/52Bd

    “mov !rx,W” instructions shown at the top of Table 2-4. For detailed information on configuring and using the I/O ports, see Chapter SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 39: Option (Device Option Register)

    RTCC bit specifies the type of signal edges detected on the RTCC pin. Set RTE_ES to 1 to detect high-to-low transitions on the RTCC pin. Clear RTE_ES to 0 to detect low-to-high transitions on the RTCC pin. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 40: Table 2-6 Prescaler Divide-By Factors

    32 (timeout = 0.5 sec) 64 (timeout = 1.0 sec) 128 (timeout = 2.0 sec) For detailed information on the Real-Time Clock/Counter and Watchdog timer, see Chapter SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 41: Instruction Execution Pipeline

    For more information on these clocking modes, see Section 4.2.1. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 42: Pipeline Delays

    To ensure predictable results, avoid using two successive read-modify-write instructions that access the same port data register. For example, you can insert a “nop” instruction between two such instructions in the program. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 43: Program Counter

    “JMP addr9” instruction as 1E0h, and the upper three bits are obtained from the PA2:PA0 bits (bits 7:5) in the STATUS register, which are set to 011 prior to the “jmp” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 44: Jump Indirect And Jump Relative

    A jump performed by modifying the PC register with a “mov” or “add” instruction takes four clock cycles in the “compatible” clocking mode (SX18/28/28AC and SX18/20/28AC75 devices only) or three clock cycles in the “turbo” clocking mode. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 45: Call

    Figure 2-3 Program Counter Loading for Jump Instruction STATUS REGISTER 8-BIT VALUE IN ZERO CALL INSTRUCTION PROGRAM COUNTER BITS 11:8 OF PC (7:0) PROGRAM COUNTER Figure 2-4 Program Counter Loading for Call Instruction SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 46: Return

    All of them are listed and described in Table 2-8. For more information on interrupts, see Chapter SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 47: Stack

    This option is controlled by the STACKX bit in the FUSEX word register (a register programmed at the same time as the program memory). SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 48: Figure 2-5 Stack Operation For A "Call" Instruction

    The bottom stack location is left unchanged. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 49: Device Configuration Options

    Table 2-9, Table 2-10, Table 2-11 Table 2-12. Note that the format of the FUSEX register depends on the SX device type (SX18/20/28AC and SX18/20/28AC75 or SX48/52BD). SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 50: Figure 2-7 Device Configuration Register Formats

    DEVICE Word (Hard-Wired Read-Only)- Part ID Part ID Code: FCEh for the SX18/20/28AC or 001h for the SX48/52BD Bit 11 Bit 0 Figure 2-7 Device Configuration Register Formats SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 51: Table 2-9 Fuse Word Register Configuration Bits For Sx18/20/28Ac

    Code Protection. Set to 1 for no code protection. Clear to 0 for code protection. With code protection, the program code and configuration registers read back as scrambled data. This prevents reverse-engineering of your proprietary code and configuration options. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 52 111 = External RC (OSC2 is pulled high with a weak pullup (no CLKOUT out- put) Note: The frequency ranges have not been characterized. These are target values. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 53: Table 2-10 Fusex Word Register Configuration Bits For Sx18/20/28Ac & Sx18/20/28Ac75

    To do so, use one the following BP1:BP0 settings: 00 = 1 page, 1 bank 01 = 1 page, 2 banks 10 = 4 pages, 4 banks 11 = 4 pages, 8 banks (default) SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 54: Table 2-11 Fuse Word Configuration Bits For Sx48/52Bd

    Code protect enable: 0 = enabled (FUSE, code, and ID memories read back as scrambled data) 1 = disabled (FUSE, code, and ID memories can be read normally) SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 55 110b = HS3 – high speed crystal (1MHz - 100MHz) 111b = RC network - OSC2 is pulled high by a weak pullup (no CLKOUT out- put) Note: The frequency ranges indicate target values. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 56: Table 2-12 Fusex Word Register Configuration Bits For Sx48/52Bd

    11b = maximum threshold voltage WDRT1: Delay Reset Timer (DRT) timeout period WDRT0 10b = 0.25 msec 11b = 18 msec 00b = 60 msec 01b = 1 sec SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 57: Chapter 3 Instruction Set

    Instruction Set Introduction The Scenix SX configurable communications controllers use a RISC (Reduced Instruction Set Computer) architecture. In this type of architecture, the instruction set is limited in complexity and diversity, but the instructions can be executed very fast, typically at a rate of one instruction per clock cycle.

  • Page 58: Instruction Types

    All of the arithmetic and shift instructions take one clock cycle for execution, except in the case of the test-and-skip instructions when the tested condition is true and a skip occurs. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 59: Bitwise Operation Instructions

    The “jmp” instruction has a single operand that specifies the new address at which to resume execution. The new address is typically specified as a label, as in the following example: SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 60 “compatible” mode is available only in the SX18/20/28AC and SX18/20/28AC75 devices. For the exact number of clock cycles required, see the instruction set summary tables or the detailed instruction descriptions. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 61: System Control Instructions

    The detailed instruction descriptions in Section 3.5 fully explain the operation of each instruction, including the Bits affected, the number of cycles required for execution, and usage examples. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 62: Table 3-1 Logic Instructions

    Increment fr and Skip if 1 or 1 or none 0011 111f ffff Zero 2 (skip) 2 (skip) RL fr Rotate fr Left through Carry 0011 011f ffff SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 63: Table 3-3 Bitwise Operation Instructions

    Move Complement 0010 010f ffff of fr to W MOV W,--fr Move (fr-1) to W 0000 110f ffff MOV W,++fr Move (fr+1) to W 0010 100f ffff SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 64 0000 0000 ffff Control Register MOV !OPTION, W Move W to none 0000 0000 0010 OPTION Register TEST fr Test fr for Zero 0010 001f ffff SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 65: Table 3-5 Program Control Instructions

    0000 0100 0001 tion Memory PAGE addr12 Load Page Number into PA2, 0000 0001 0nnn STATUS(7:5) PA1, SLEEP Power Down Mode TO, PD 0000 0000 0011 SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 66: Equivalent Assembler Mnemonics

    Each description starts on a new page of the manual. The heading at the top of the page shows the syntax of the command and a brief description of what the command does. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 67: Add Fr,W

    These additional assembler mnemonics are beyond the scope of this section. For more information, see the documentation provided with the assembler. Table 3-8 is a quick reference to the abbreviations and symbols used in the instruction descriptions. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 68: Table 3-8 Key To Abbreviations And Symbols

    Logical AND <> Swap high and low nibbles (4-bit segments) << Rotate left through carry bit >> Rotate right through carry bit Decrement file register Increment file register SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 69 81h, into the file register; and clears the C and Z bits. It sets the DC bit because of the carry from bit 3 to bit 4. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 70: Add W,Fr

    7, and clears the DC bit because there is no carry from bit 3 to bit 4. The Z bit is cleared because the result is nonzero. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 71: And Fr,Wand Of Fr And W Into Fr

    13h. The instruction takes the logical AND of 0Fh and 13h and writes the result, 03h, into the same file register. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 72: And W,Fr And Of W And Fr Into W

    13h. The instruction takes the logical AND of 0Fh and 13h and writes the result, 03h, into W. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 73: And W,#Lit And Of W And Literal Into W

    For example, suppose that W contains the value 50h. The instruction takes the logical AND of this value with 0Fh and writes the result, 00h, into W. The result is zero, so the Z bit is set. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 74: Bank Addr8

    Cycles: Example: SX18/20/28AC and SX18/20/28AC75: bank ;select highest bank This example writes the three high-order bits of FSR with 111 and selects Bank 7, the highest bank. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 75 This example wrires bits 4, 5, 6 of FSR with 111. The BANK instruction is imme- diately followed by “setb $04.7” to select the upper block of 8 banks. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 76: Call Addr8

    $0C,W” instruction) is pushed onto the stack and the program jumps to the “addxy” routine. When the “ret” instruction is executed, the 12-bit program address saved on the stack is popped and restored to the program counter, which causes the SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 77 STATUS register must contain the three high-order bits of the subroutine address prior to the “call” instruction. This is the purpose of the “page” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 78: Clear Fr

    This instruction clears the specified file register to zero. It also sets the Z bit uncon- ditionally. Cycles: Example: This example clears file register 0Ah to 00h and sets the Z bit. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 79: Clr W Clear W

    Description: This instruction clears W, the working register. It also sets the Z bit. Cycles: Example: This example clears W to 00h and sets the Z bit. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 80: Clr !Wdt

    Watchdog reset. Cycles: Example: !WDT This example clears the Watchdog Timer counter and the Watchdog prescaler register to zero; and sets the Z, TO, and PD bits. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 81: Clrb Fr.bit

    The file register address (00h through 1Fh) and the bit number (0 through 7) are the instruction operands. Cycles: Example: clrb $1F.7 This example clears the most significant bit of file register 1Fh. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 82: Dec Fr

    If the file register contains 01h, it is decremented to 00h and the Z bit is set. Otherwise, the bit is cleared. If the file register contains 00h, it is decremented to FFh. Cycles: Example: This example decrements file register 18h. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 83: Decsz Fr

    The “decsz” instruction decrements file register 18h. If the result is nonzero, execution proceeds normally with the “jmp” instruction. If the result is zero, the device skips the “jmp” instruction and proceeds with the “mov” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 84: Inc Fr

    If the file register contains FFh and is incremented to 00h, the Z bit is set. Otherwise, the bit is cleared. Cycles: Example: This example increments file register 18h. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 85: Incsz Fr

    The “incsz” instruction increments file register 18h. If the result is nonzero, execution proceeds normally with the “jmp” instruction. If the result is zero, the device skips the “jmp” instruction and proceeds with the “mov” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 86: Iread

    Program Data Hardwired to 0 for all devices Hardwired to 0 for SX28AC Programmable with MOV M, W for SX48/52BD Figure 3-1 Program Counter Loading for Call Instruction SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 87 380h. The program then stores the lower eight bits of the result into file register 0Eh and the upper four bits of the result into file register 0Fh. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 88: Jmp Addr9

    The PA2:PA0 bits of the STATUS register must contain the three high-order bits (bits 11:9) of the “overflo” routine address prior to the “jump” instruction. This is the purpose of the “page” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 89: Mov Fr,W

    ;move W to reg. 10h in bank This example moves the contents of W into file register 10h in Bank 7 (for the SX18/20/28AC) or Bank E (for the SX48/52BD). SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 90: Mov M,#Lit

    ( SX18/20/28AC and SX18/20/28AC75 devices) and the five lower bitsof the MODE register for the SX48/52BD devices. The two subsequent “mov M,#lit” instructions change the lower four bits of the MODE register. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 91: Mov M,W Move W To Mode Register

    ;move value from file reg 0Bh to W ;move W into MODE register This example moves a value from file register 0Bh to W, and then from W into the MODE register. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 92: Mov !Option,W

    For information on the format of the OPTION register, see Section 2.4.9. Cycles: Example: W,#$3F ;load W with 3Fh !OPTION,W ;write value to OPTION register This example moves programs the OPTION register with the value 3Fh. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 93: Mov !Rx,W Move Data Between W And Control Register

    5 to operate as high-impedance inputs and pins 6 and 7 to operate as outputs. The last two instructions configure all Port C pins to operate as inputs. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 94 “don’t care” bits, so the “mov M,#lit” instruction (which only affects the four lower bits of the MODE register) is sufficient to select access to the CMP_B register. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 95: Mov W,Fr

    This example moves the contents of a specific file register into W. The Z bit is set if the value is zero or cleared if the value is nonzero. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 96: Mov W,/Fr Move Complement Of Fr To W

    75h, the complement of this value, 8Ah, is loaded into W, and the Z bit is cleared. The file register is left unchanged. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 97 06h from 35h and writes the result, 2Fh, into W. It also sets the C bit, clears the DC bit, and clears the Z bit. The file register is left unchanged. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 98: Move (Fr-1) To W

    For example, if the file register contains 75h, the value 74h is loaded into W, and the Z bit is cleared. The file register still contains 75h after execution of the instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 99: Mov W,++Fr

    For example, if the file register contains 75h, the value 76h is loaded into W, and the Z bit is cleared. The file register still contains 75h after execution of the instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 100: Figure 3-2 Rotate Fr Left Through Carry Into W

    W will contain 29h and the C bit will be cleared to 0. The file register will still contain 14h after execution of the instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 101: Figure 3-3 Rotate Fr Right Through Carry Into W

    W will contain 89h and the C bit will be cleared to 0. The file register will still contain 12h after execution of the instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 102 This example swaps the high-order and low-order nibbles of the value in file register 0Bh and moves the result into W. For example, if the file register contains A5h, after executing this instruction, W will contain 5Ah. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 103 This instruction loads an 8-bit literal value (a value specified within the instruction) into W. Cycles: Example: W,#$75 This example loads the immediate value 75h into W. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 104: Mov W,M

    $10,W ;save value to file register 10h This example moves the contents of the MODE register into W, and then stores that value into file register 10h. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 105: Movsz W, --Fr

    W. If the result is zero, the device skips the “ret” instruction and proceeds with the “nop” instruction. If the result is nonzero, the device executes the “ret” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 106: Movsz W, ++Fr

    W. If the result is zero, the device skips the “ret” instruction and proceeds with the “nop” instruction. If the result is nonzero, the device executes the “ret” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 107: Nop No Operation

    This example shows how a “nop” instruction can be used as a one-cycle delay between two successive read-modify-write instructions that modify the same I/O port. This delay ensures reliable results at high clock rates. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 108: Not Fr

    Suppose that W contains the value 1Ch. This instruction takes the complement of 1Ch and writes the result, E3h, into the same register. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 109: Or Fr,W

    13h. The instruction takes the logical OR of 0Fh and 13h and writes the result, 1Fh, into the same file register. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 110: Or W,Fr

    13h. The instruction takes the logical OR of 0Fh and 13h and writes the result, 1Fh, into W. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 111: Or W,#Lit

    For example, suppose that W contains the value 50h. The instruction takes the logical OR of this value with 0Fh and writes the result, 5Fh, into W. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 112 “call” instruction calls a subroutine that starts in the bottom half of page 2 of program memory (somewhere in the address range of 400h to 4FFh). SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 113: Ret Return From Subroutine

    When the “ret” instruction is executed, the saved program address is popped from the stack and restored to the program counter, which causes the program to continue with the instruction immediately following the “call” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 114: Reti

    The “reti” instruction restores the contents of the program counter and the W, STATUS, and FSR registers. This causes the device to continue program execution at the point where the program was interrupted. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 115 ;interrupt service routine at address 000h ;check RTCC ;check interrupt pending bits ;perform interrupt service ;check RTCC ;put adjustment value into W retiw ;return from interrupt and adjust RTCC SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 116: Retp

    PA2:PA0 bits are automatically returned to their original values (PA2:PA0 = 00), allowing a subsequent same-page call to be done without using the “page” instruction again. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 117 (the PC register at address 02h), which advances the program to the applicable “RETW lit” instruction. The “RETW lit” instruction returns from the subroutine with the appropriate result in W. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 118: Rl Fr

    This example multiplies file register 18h by 4. The initial “clrb” instruction clears the C bit, which ensures that 0 will be shifted into the least significant bit position. The two “rl” instructions perform two successive multiply-by-2 operations. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 119: Rr Fr

    This example divides file register 0Fh by 4. The “clrb” instructions ensure that 0 will be shifted into the most significant bit positions. The two “rr” instructions perform two divide-by-2 operations. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 120: Sb Fr.bit

    This example tests the most significant bit of file register 1Fh. If that bit is 1, the “inc” instruction is skipped. Otherwise, program execution proceeds normally with the “inc” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 121: Setb Fr.bit

    The file register address (00h through 1Fh) and the bit number (0 through 7) are the instruction operands. Cycles: Example: setb $1F,7 This example sets the most significant bit of file register 1Fh. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 122: Sleep

    MCLR pin. For more information on the power down mode, Section 4.3. Cycles: Example: sleep This example puts the device into the power down mode until a wakeup event occurs. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 123: Snb Fr.bit

    This example tests bit number 5 of file register 1Fh. If that bit is 0, the “dec” instruction is skipped. Otherwise, program execution proceeds normally with the “dec” instruction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 124: Sub Fr,W

    ;load W from 0Ah (low-order byte) sub $0C,W ;low-order subtraction, C=0 for borrow out mov W,$0B ;load W from 0Bh (high-order byte) sub $0D,W ;high-order subtraction, borrow in & out SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 125 0Dh if the carry bit is 0, and then do the high-order subtraction. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 126: Swap Fr Swap High/Low Nibbles Of Fr

    This example swaps the high-order and low-order nibbles of file register 0Bh. For example, if the register contains A5h, after executing this instruction, the register will contain 5Ah. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 127: Test Fr

    Z bit based on the contents of the file register. The “sb” instruction tests the Z bit. The “inc” instruction is executed if the file register contains zero or is skipped if the file register contains a nonzero value. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 128: Xor Fr,W

    13h. The instruction takes the logical XOR of 0Fh and 13h and writes the result, 1Ch, into the same file register. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 129: Xor W,Fr

    13h. The instruction takes the logical XOR of 0Fh and 13h and writes the result, 1Ch, into W. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 130: Xor W,#Lit

    For example, suppose that W contains the value 51h. The instruction takes the logical XOR of this value with 0Fh and writes the result, 5Eh, into W. The result is nonzero, so the Z bit is cleared. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 131: Chapter 4 Clocking, Power Down, And Reset

    “compatible” mode and the “turbo” mode. The “compatible” mode is available only in the SX18/20/28AC and SX18/20/28AC75 devices. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 132: Internal Rc Oscillator

    Although the device will operate without a capacitor (C = 0 pF), a capacitor of at least 20 pF is recommended for noise immunity and stability. For capacitance values lower than this, the oscillator SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 133: External Crystal/Resonator (Xt, Lp, Or Hs Mode)

    HS1 – high-speed crystal/resonator (1 MHZ to 32 MHz) • HS2 – high-speed crystal/resonator (1 MHZ to 50 MHz) • HS3 – high-speed crystal/resonator (1 MHZ to 50 MHz) SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 134: External Clock Signal

    SX device. The clock signal must meet the clock specifications of the SX device, including the duty cycle, rise time, fall time, and voltage levels. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 135: Power Down Mode

    PD (Power Down) bit to 0 in the STATUS register. The Watchdog timer continues to operate while the device is powered down. A Watchdog timeout will then wake up the device from the power down state. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 136: Waking Up From The Power Down Mode

    Port B pins can be individually configured for this purpose. You control the port configuration by writing to its configuration registers using the “MOV !RB,W” instruction. Selection of those registers is controlled by the MODE register. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 137: Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram

    Port B Configured as Input WKED_B WKPND_B MODE MODE = 09 Wake-up: Exit Power Down WKEN_B 0 = Enable 1 = Disable Figure 4-4 Multi-Input Wakeup/Interrupt Block Diagram SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 138 Upon reset, the WKEN_B register is set to FFh. This disables the wakeup interrupts by default. You must explicitly enable any pins that you want to use as wakeup/interrupt pins. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 139: Reading And Writing The Wakeup Pending Bits

    W to determine which Port B pin caused the wakeup or interrupt event. Clearing the WKPND_B register is necessary to enable detection of any subsequent wakeup or interrupt events on the Port B pins. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 140: Reset

    SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 141: Table 4-1 Register States Upon Different Resets

    1. Watchdog reset during power down mode: 00 (bits TO, PD); Watchdog reset during Active mode: 01 (bits TO, PD) NOTE: 2. External reset during power down mode: 10 (bits TO, PD); External reset during Active mode: Un- changed (bits TO, PD) SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 142: Power-On Reset

    The power-on timing with the external RC network is shown in Figure 4-9. In this case, the device comes out of reset about 72 msec after the MCLR input goes high. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 143: Wakeup From The Power Down Mode

    For fast start-up from the power down mode, clear the SLEEPCLK bit and set the WDRT1:WDRT0 field to 10. This will keep the clock operating during the power down mode and allow a 0.06 msec start-up delay. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 144: Brown-Out Reset

    (the highest memory address). If you do not intend to use the MCLR pin as a hardware reset input, you should connect it together with the power supply pin (Vdd) or to a power-on RC network, as described in Section 4.5.2. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 145: Chapter 5 Input/Output Ports

    W,#$03 ;load W with the value 03h (bits 0 and 1 high) $05,W ;write 03h to Port A data register SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 146: Port Configuration

    2.5.3. Port Configuration Each port pin offers the following configuration options: • data direction • input voltage levels (TTL or CMOS) • pullup type (enable or disable) SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 147: Accessing The Port Control Registers

    MODE register again. For example, you can write the value 1Eh to the MODE register just once, and then write to each of the pullup configuration registers using the instructions “mov !RA,W,” “mov !RB,W,” and so on. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 148: Table 5-1 Mode Register Settings For Sx18/20/28Ac And Sx18/20/28Ac75

    Clear Timer T2 Write T1R2CML Write T2R2CML Write T1R2CMH Write T2R2CMH Write T1R1CML Write T2R1CML Write T1R1CMH Write T2R1CMH Write T1CNTB Write T2CNTB Write T1CNTA Write T2CNTA Exchange CMP_B SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 149: Port Configuration Example

    Each register bit sets the data direction for one port pin. Set the bit to 1 to make the pin operate as a high-impedance input. Clear the bit to 0 to make the pin operate as an output. The bit is set to 1 after all resets. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 150 MIWU pin, triggering a wakeup or interrupt. A bit set to 0 indicates that no valid edge has occurred on the MIWU pin. The WKPND_B register comes up with undefine value upon reset. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 151: Port Configuration Upon Reset

    (in the default operating mode), even when the pin is configured to operate as an output. The PLP_B bit either connects or disconnects the internal pullup resistor. If the pullup resistor is disconnected, an external pullup will be required. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 152: Figure 5-1 Port B Pin Block Diagram

    Port A does not offer a Schmitt trigger input option, so it lacks the control register bit and logic associated with the Schmitt trigger buffer. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 153: Chapter 6 Timers And Interrupts

    Clear the bit to 0 to sense rising edges (low-to-high transitions) or set the bit to 1 to sense falling edges (high-to-low transitions) on the RTCC pin. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 154: Prescaler Register

    To enable this interrupt, clear the RTE_IE bit in the OPTION register. You can have the interrupt service routine increment a file register (or a set of cascaded file registers), and thereby keep track of any number of instruction cycles or events. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 155: Rtcc Operation As A Real-Time Clock Or Timer

    RTCCOV (RTCC Overflow), which is bit 7 in the T1CNTB register. The interrupt service routine can check this bit to determine whether an RTCC overflow caused the interrupt. The SX18/20/28 has no SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 156: Watchdog Timer

    8-bit Watchdog register overflows a certain number of times. This increases the Watchdog timeout period by a factor determined by the PS2:PS0 bits in the OPTION SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 157: Watchdog Operation In The Power Down Mode

    In the SX18/20/28AC and SX18/20/28AC75 devices, there are two possible causes of an interrupt: • a rollover of the Real-Time Clock/Counter (RTCC) SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 158: Single-Level Interrupt Operation

    4. If the device is configured to accept different interrupts, the interrupt service routine should read the applicable registers (such as WKPND_B and T1CNTB) to determine the cause of the inter- rupt. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 159: Figure 6-2 Interrupt Logic Block Diagram

    1 = Ext. Interrupt through Port B PD Flag 0 = Power Down Mode, no Ext. Interrupt RTE_IE OPTION WKEN_B Device-Specific Interrupt Sources (e.g. Timer T1) Figure 6-2 Interrupt Logic Block Diagram SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 160: Rtcc Interrupts

    RTCC and Multi-Input Wakeup interrupts. They have their own interrupt configuration and enable bits. For more information on using the interrupts associated with Timer T1 and Timer T2, see Chapter SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 161: Return-From-Interrupt Instructions

    ;RTCC interrupt service routine here reti ;return from interrupt rb0_i ;RB0 interrupt service routine here reti ;return from interrupt rb1_i ;RB1 interrupt service routine here reti ;return from interrupt SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 162 Chapter 6 Timers and Interrupts www.scenix.com SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 163: Introduction

    RB2 and RB1 to operate as inputs by setting bit 2 and bit 1 in the RB Data Direction register. • CMP_OE (Comparator Output Enable). Using the RB0 pin as a comparator output is optional. To do this, clear this bit to 0. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 164: Accessing The Cmp_B Register

    The comparator result appears in the CMP_RES bit position, whether or not the RB0 output pin is used with the comparator. Read/write access to the CMP_B register is enabled when the MODE register contains 08h or 18h. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 165: Figure 7-1 Comparator Block Diagram

    The comparator takes some time to respond after it is enabled and after a change in the analog input voltages. For details, see the comparator DC and AC specifications in the device data sheet. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.
  • Page 166 Chapter 7 Analog Comparator www.scenix.com SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 167: Introduction

    16-Bit Capture Register (2) System 3-bit Divide-by 16-Bit Comparator Clock Factor Ext. Clock 16-Bit Free-Running Timer/Counter Capture Interrupt Capture 1 16-Bit Capture Register (1) Figure 8-1 Multi-Function Timer Block Diagram SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 168: Timer Operating Modes

    The software can determine the cause of each interrupt by checking the timer interrupt pending flags. There is a different flag bit associated with each type of event (R1 match, R2 match, or overflow). SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 169: External Event Mode

    In cases where the time between successive capture events might exceed 65,536 counts of the timer, the software should keep track of the number of overflows between successive events in order to determine the true amount of time between such events. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 170: Timer Pin Assignments

    Each Control B register also contains one device configuration bit not related to operation of the multi-function timers. The register formats are shown in the following tables. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 171: Timer T1 Control A Register (T1Cnta)

    Timer T1 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T1. In that case, an interrupt will occur each time Timer T1 overflows. Clear this bit to 0 to disable overflow interrupts. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 172: Timer T1 Control B Register (T1Cntb)

    Timer T1 Mode Control field. This 2-bit field specifies the Timer T1 operating mode as follows: 00 = Software Timer mode 01 = PWM mode 10 = Capture/Compare mode 11 = External Event mode SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 173: Timer T2 Control A Register (T2Cnta)

    Timer T2 Overflow Interrupt Enable. Set this bit to 1 to enable overflow interrupts for Timer T2. In that case, an interrupt will occur each time Timer T2 overflows. Clear this bit to 0 to disable overflow interrupts. SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

  • Page 174: Timer T2 Control B Register (T2Cntb)

    Timer T2 Mode Control field. This 2-bit field specifies the Timer T2 operating mode as follows: 00 = Software Timer mode 01 = PWM mode 10 = Capture/Compare mode 11 = External Event mode SX User’s Manual Rev. 3.1 © 2000 Scenix Semiconductor, Inc. All rights reserved.

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