Renesas IDT PCI Express 89HPES6T5 Manuals

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Renesas IDT PCI Express 89HPES6T5 User Manual (165 pages)

Brand: Renesas | Category: Switch | Size: 2 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
7
Table of Contents
9
List of Figures
15
PES6T5 Device Overview
21
Introduction
21
List of Features
21
System Diagrams
23
Logic Diagram
24
Ssid/Ssvid
24
Device Serial Number Enhanced Capability
25
Pin Description
25
Signal Type
25
Table 1.3 General Purpose I/O Pins
26
Table 1.4 System Pins
27
Table 1.5 Test Pins
28
Table 1.6 Power and Ground Pins
28
Pin Characteristics
29
Table 1.7 Pin Characteristics
29
System Identification
31
Vendor ID
31
Device ID
31
Revision ID
31
Jtag ID
31
Port Configuration
31
Table 1.8 PES6T5 Device ID
31
Table 1.9 PES6T5 Revision ID
31
Figure 1.3 PES6T5 Port Configuration
32
Introduction
33
Clock Operation
33
Figure 2.1 Common Clock on Upstream and Downstream
33
Clocking, Reset, and Initialization
33
Table 2.1 Reference Clock Mode Encoding
33
Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream
34
Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream
34
Figure 2.4 Non-Common Clock on Upstream and Downstream
35
Table 2.2 Boot Configuration Vector Signals
36
Reset
37
Fundamental Reset
37
Figure 2.5 Fundamental Reset with Serial EEPROM Initialization
38
Hot Reset
39
Upstream Secondary Bus Reset
39
Downstream Secondary Bus Reset
40
Downstream Port Reset Outputs
40
Power Enable Controlled Reset Output
41
Power Good Controlled Reset Output
41
Figure 2.6 Power Enable Controlled Reset Output Mode Operation
41
Figure 2.7 Power Good Controlled Reset Output Mode Operation
41
Hot Reset Controlled Reset Output
42
Theory of Operation
43
Port Interrupts
43
Legacy Interrupt Emulation
43
Table 3.1 Downstream Port Interrupts
43
Table 3.2 PES6T5 Downstream to Upstream Port Interrupt Routing
44
Link Operation
45
Introduction
45
Notes
45
Polarity Inversion
45
Link Width Negotiation
45
Lane Reversal
45
Figure 4.1 Upstream Port (X2 Lane Width) Lane Reversal
45
Link Retraining
46
Link down
46
Slot Power Limit Support
46
Upstream Port
46
Downstream Port
46
Link States
46
Active State Power Management
47
Figure 4.2 PES6T5 ASPM Link Sate Transitions
47
Link Status
48
General Purpose Inputs/Outputs
49
Introduction
49
GPIO Configuration
49
Table 5.1 General Purpose I/O Pin Alternate Function
49
Table 5.2 GPIO Pin Configuration
49
GPIO Pin Configured as an Input
50
GPIO Pin Configured as an Output
50
GPIO Pin Configured as an Alternate Function
50
Smbus Interfaces
55
Introduction
55
Figure 6.1 Smbus Interface Configuration Examples
55
Master Smbus Interface
56
Initialization
56
Serial EEPROM
56
Table 6.1 Serial EEPROM Smbus Address
56
Table 6.2 PES6T5 Compatible Serial Eeproms
57
Figure 6.2 Single Double Word Initialization Sequence Format
57
Figure 6.3 Sequential Double Word Initialization Sequence Format
58
Figure 6.4 Configuration Done Sequence Format
58
Table 6.3 Serial EEPROM Initialization Errors
59
I/O Expanders
60
Table 6.4 I/O Expander Function Allocation
60
Table 6.5 I/O Expander Default Output Signal Value
61
Table 6.6 I/O Expander 0 Signals
63
Table 6.7 I/O Expander 1 Signals
64
Table 6.8 I/O Expander 2 Signals
64
Table 6.9 I/O Expander 4 Signals
65
Slave Smbus Interface
66
Initialization
66
Smbus Transactions
66
Table 6.10 Slave Smbus Address When a Static Address Is Selected
66
Figure 6.5 Slave Smbus Command Code Format
66
Table 6.11 Slave Smbus Command Code Fields
67
Table 6.12 CSR Register Read or Write Operation Byte Sequence
67
Table 6.13 CSR Register Read or Write CMD Field Description
68
Figure 6.6 CSR Register Read or Write CMD Field Format
68
Table 6.14 Serial EEPROM Read or Write Operation Byte Sequence
69
Figure 6.7 Serial EEPROM Read or Write CMD Field Format
69
Table 6.15 Serial EEPROM Read or Write CMD Field Description
70
Figure 6.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC
70
Figure 6.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
71
Figure 6.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
71
Figure 6.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
71
Figure 6.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
71
Figure 6.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
72
Power Management
73
Introduction
73
Figure 7.1 PES6T5 Power Management State Transition Diagram
73
PME Messages
74
Table 7.1 PES6T5 Power Management State Transition Diagram
74
Power Express Power Management Fence Protocol
75
Power Budgeting Capability
75
Wakeup Protocol
76
WAKEN Signal as an Input
77
WAKEN Signal as an Output
77
WAKEN and Beacon Disabled
77
Auxiliary Power Implementation
77
Switch System States
77
Figure 7.2 PES6T5 System States
77
Auxiliary Power Control
78
Figure 7.3 L2 Mode Enable/Disable and Frsticky Bit Initialization
79
PES6T5 Auxiliary Power Usage
80
Figure 7.4 Vaux Usage Model
80
Table 7.2 Auxiliary Power Enabled (Beacon OFF)
81
Table 7.3 Auxiliary Power Enabled (Serdes OFF, Only WAKEN Enabled)
81
Figure 7.5 Conceptual Diagram of the PES6T5 Auxiliary Power Connection
82
Hot-Plug and Hot-Swap
83
Introduction
83
Figure 8.1 Hot-Plug on Switch Downstream Slots Application
83
Figure 8.2 Hot-Plug with Switch on Add-In Card Application
84
Figure 8.3 Hot-Plug with Carrier Card Application
84
Hot-Plug I/O Expander
86
Hot-Plug Interrupts and Wake-Up
86
Legacy System Hot-Plug Support
86
Figure 8.4 PES6T5 Hot-Plug Event Signalling
87
Hot-Swap
88
Configuration Registers
89
Configuration Space Organization
89
Table 9.1 Base Addresses for Port Configuration Space Registers
89
Figure 9.1 Port Configuration Space Organization
90
Register Definition
91
Table 9.2 Upstream Port 0 Configuration Space Registers
91
Downstream Ports (Ports 2 through 5)
95
Table 9.3 Downstream Ports 2 through 5 Configuration Space Registers
95
Register Definitions
99
Type 1 Configuration Header Registers
99
PCI Express Capability Structure
109
Power Management Capability Structure
120
Message Signaled Interrupt Capability Structure
122
Subsystem ID and Subsystem Vendor ID
123
Extended Configuration Space Access Registers
124
Advanced Error Reporting (AER) Enhanced Capability
125
Device Serial Number Enhanced Capability
131
PCI Express Virtual Channel Capability
131
Power Budgeting Enhanced Capability
137
Switch Control and Status Registers
139
Internal Switch Error Control and Status Registers
149
Wakeup Protocol Registers
152
JTAG Boundary Scan
155
Introduction
155
Test Access Point
155
Signal Definitions
155
Figure 10.1 Diagram of the JTAG Logic
155
Table 10.1 JTAG Pin Descriptions
156
Figure 10.2 State Diagram of Pes6T5'S TAP Controller
156
Boundary Scan Chain
157
Table 10.2 Boundary Scan Chain
157
Test Data Register (DR)
158
Boundary Scan Registers
158
Figure 10.3 Diagram of Observe-Only Input Cell
159
Figure 10.4 Diagram of Output Cell
159
Instruction Register (IR)
160
Figure 10.5 Diagram of Bidirectional Cell
160
Extest
161
Sample/Preload
161
Bypass
161
Table 10.3 Instructions Supported by Pes6T5'S JTAG Boundary Scan
161
Clamp
162
Idcode
162
Validate
162
Reserved
162
Table 10.4 System Controller Device Identification Register
162
Figure 10.6 Device ID Register Format
162
Usage Considerations
163
Corporate Headquarters
165
Contact Information
165

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Renesas IDT PCI Express 89HPES6T5 User Manual (165 pages)

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