Renesas IDT 89HPES12T3G2ZBBCI Manuals

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Renesas IDT 89HPES12T3G2ZBBCI User Manual (147 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 1 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
3
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
6
Reference Documents
6
Revision History
6
Table of Contents
7
PES12T3G2 Device Overview
19
Introduction
19
Features
19
System Diagram
20
Table 1.1 Table
20
Logic Diagram
21
System Identification
22
Vendor ID
22
Device ID
22
Revision ID
22
Jtag ID
22
Pin Description
22
PES12T3G2 Device ID
22
Table 1.3 PCI Express Interface Pins
22
Table 1.4 Smbus Interface Pins
23
Table 1.5 General Purpose I/O Pins
24
Table 1.6 System Pins
25
Table 1.7 Test Pins
25
Table 1.8 Power, Ground, and Serdes Resistor Pins
26
Pin Characteristics
27
Table 1.9 Pin Characteristics
27
Port Configuration
28
Figure 1.3 PES12T3G2 Port & Device Numbering
28
Clocking, Reset and Initialization
29
Clocking
29
Table 2.1 Reference Clock Mode Encoding
29
Reset
30
Table 2.2 Boot Configuration Vector Signals
30
Fundamental Reset
31
Figure 2.1 Fundamental Reset with Serial EEPROM Initialization
32
Hot Reset
33
Figure 2.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
33
Upstream Secondary Bus Reset
34
Downstream Secondary Bus Reset
34
Downstream Port Reset Outputs
35
Power Enable Controlled Reset Output
35
Figure 2.3 Power Enable Controlled Reset Output Mode Operation
35
Power Good Controlled Reset Output
36
Figure 2.4 Power Good Controlled Reset Output Mode Operation
36
Link Operation
37
Introduction
37
Polarity Inversion
37
Lane Reversal
37
Figure 3.1 Port Lane Reversal for Maximum Link Width of X4 (Maxlnkwdth=0X4)
37
Link Width Negotiation
38
Dynamic Link Width Re-Configuration
38
Background
38
Figure 3.2 Port Lane Reversal for Maximum Link Width of X2 (Maxlnkwdth=0X2)
38
Dynamic Link Width Re-Configuration Support in the PES12T3G2
39
Link Speed Negotiation
39
Background
39
Link Speed Negotiation in the PES12T3G2
40
Software Management of Link Speed
41
Link Retraining
42
Slot Power Limit Support
42
Upstream Port
42
Downstream Port
43
Link States
43
Figure 3.3 PES12T3G2 ASPM Link Sate Transitions
43
Active State Power Management
44
Link Status
44
De-Emphasis Negotiation
44
Low-Swing Transmitter Voltage Mode
45
General Purpose I/O
47
Introduction
47
GPIO Configuration
47
GPIO Pin Configured as an Input
47
Table 4.1 General Purpose I/O Pin Alternate Function
47
Table 4.2 GPIO Pin Configuration
47
GPIO Pin Configured as an Output
48
GPIO Pin Configured as an Alternate Function
48
Smbus Interfaces
49
Introduction
49
Figure 5.1 Smbus Interface Configuration Examples
49
Master Smbus Interface
50
Initialization
50
Serial EEPROM
50
Table 5.1 Serial EEPROM Smbus Address
50
Table 5.2 PES12T3G2 Compatible Serial Eeproms
51
Figure 5.2 Single Double Word Initialization Sequence Format
51
Figure 5.3 Sequential Double Word Initialization Sequence Format
52
Figure 5.4 Configuration Done Sequence Format
52
Table 5.3 Serial EEPROM Initialization Errors
53
I/O Expanders
54
Table 5.4 I/O Expander Function Allocation
54
Table 5.5 I/O Expander Default Output Signal Value
55
Table 5.6 I/O Expander 0 Signals
57
Table 5.7 I/O Expander 2 Signals
58
Table 5.8 I/O Expander 4 Signals
58
Slave Smbus Interface
59
Initialization
59
Table 5.9 Slave Smbus Address When a Static Address Is Selected
59
Smbus Transactions
60
Table 5.10 Slave Smbus Command Code Fields
60
Figure 5.5 Slave Smbus Command Code Format
60
Table 5.11 CSR Register Read or Write Operation Byte Sequence
61
Figure 5.6 CSR Register Read or Write CMD Field Format
61
Table 5.12 CSR Register Read or Write CMD Field Description
62
Table 5.13 Serial EEPROM Read or Write Operation Byte Sequence
62
Table 5.14 Serial EEPROM Read or Write CMD Field Description
63
Figure 5.7 Serial EEPROM Read or Write CMD Field Format
63
Figure 5.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC
64
Figure 5.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
64
Figure 5.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
64
Figure 5.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
65
Figure 5.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
65
Figure 5.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
65
Power Management
67
Introduction
67
Figure 6.1 PES12T3G2 Power Management State Transition Diagram
67
PME Messages
68
PCI-Express Power Management Fence Protocol
68
Table 6.1 PES12T3G2 Power Management State Transition Diagram
68
Power Budgeting Capability
69
Hot-Plug and Hot-Swap
71
Hot-Plug
71
Figure 7.1 Hot-Plug on Switch Downstream Slots Application
71
Figure 7.2 Hot-Plug with Switch on Add-In Card Application
72
Figure 7.3 Hot-Plug with Carrier Card Application
72
Table 7.1 Downstream Port Hot Plug Signals
73
Hot-Plug I/O Expander
74
Hot-Plug Interrupts and Wake-Up
74
Legacy System Hot-Plug Support
74
Figure 7.4 PES12T3G2 Hot-Plug Event Signalling
75
Hot-Swap
76
Configuration Registers
77
Configuration Space Organization
77
Table 8.1 Base Addresses for Port Configuration Space Registers
77
Figure 8.1 Port Configuration Space Organization
78
Upstream Port (Port 0)
79
Table 8.2 Upstream Port 0 Configuration Space Registers
79
Downstream Ports
82
Table 8.3 Downstream Ports 2, 4, 6 Configuration Space Registers
82
Register Definitions
86
Type 1 Configuration Header Registers
86
PCI Express Capability Structure
95
Power Management Capability Structure
110
Message Signaled Interrupt Capability Structure
112
Subsystem ID and Subsystem Vendor ID
113
Extended Configuration Space Access Registers
114
Advanced Error Reporting (AER) Enhanced Capability
115
Device Serial Number Enhanced Capability
121
PCI Express Virtual Channel Capability
122
Power Budgeting Enhanced Capability
128
Switch Status and Control Registers
129
Physical Layer Control and Status Registers
136
Power Management Control and Status Registers
137
JTAG Boundary Scan
139
Introduction
139
Test Access Point
139
Signal Definitions
139
Figure 9.1 Diagram of the JTAG Logic
139
Table 9.1 JTAG Pin Descriptions
140
Figure 9.2 State Diagram of Pes12T3G2'S TAP Controller
140
Boundary Scan Chain
141
Test Data Register (DR)
141
Table 9.2 Boundary Scan Chain
141
Boundary Scan Registers
142
Figure 9.3 Diagram of Observe-Only Input Cell
142
Figure 9.4 Diagram of Output Cell
142
Instruction Register (IR)
143
Figure 9.5 Diagram of Bidirectional Cell
143
Extest
144
Sample/Preload
144
Bypass
144
Table 9.3 Instructions Supported by Pes12T3G2'S JTAG Boundary Scan
144
Clamp
145
Idcode
145
Validate
145
Reserved
145
Usage Considerations
145
Table 9.4 System Controller Device Identification Register
145
Figure 9.6 Device ID Register Format
145

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Renesas IDT 89HPES12T3G2ZBBCI Manuals

Renesas IDT 89HPES12T3G2ZBBCI User Manual (147 pages)

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