Renesas IDT 89HPES64H16AG2 Manuals

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Renesas IDT 89HPES64H16AG2 User Manual (321 pages)

PCI Express Switch

Brand: Renesas | Category: Switch | Size: 4 MB

About this Manual
3
Content Summary
3
Signal Nomenclature
4
Numeric Representations
4
Data Units
4
Register Terminology
5
Use of Hypertext
7
Reference Documents
7
Revision History
7
Table of Contents
11
List of Figures
19
PES64H16AG2 Device Overview
25
Introduction
25
Features
25
Logic Diagram
29
System Identification
30
Vendor ID
30
Device ID
30
Revision ID
30
Jtag ID
30
Ssid/Ssvid
30
Device Serial Number Enhanced Capability
30
PES64H16AG2 Device Ids
30
Table 1.3 PES64H16AG2 Revision ID
30
Pin Description
31
Table 1.4 PCI Express Interface Pins
31
Table 1.5 Reference Clock Pins
33
Table 1.6 Smbus Interface Pins
33
Table 1.7 General Purpose I/O Pins
33
Table 1.8 System Pins
33
Signal Type
35
Table 1.9 Test Pins
35
Table 1.10 Power, Ground, and Serdes Resistor Pins
36
Pin Characteristics
38
Table 1.11 Pin Characteristics
38
Architectural Overview
43
Introduction
43
Switch Partitioning
44
Dynamic Reconfiguration
45
Switch Core
47
Introduction
47
Switch Core Architecture
47
Ingress Buffer
47
Table 3.1 IFB Buffer Sizes
47
Egress Buffer
48
Table 3.2 EFB Buffer Sizes
48
Crossbar Interconnect
49
Datapaths
49
Table 3.3 Replay Buffer Storage Limit
49
Packet Ordering
50
Arbitration
51
Table 3.4 Packet Ordering Rules in the PES64H16AG2
51
Port Arbitration
52
Cut-Through Routing
52
Table 3.5 Conditions for Cut-Through Transfers
53
Request Metering
54
Operation
56
Table 1.1 Table
56
Table 3.6 Request Metering Decrement Value
57
Completion Size Estimation
58
Internal Errors
59
Switch Time-Outs
60
Memory SECDED ECC Protection
60
End-To-End Data Path Parity Protection
60
Clocking
63
Port Clocking Modes
64
Spread Spectrum Clocking (SSC) Support
64
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State
64
Table 4.2 GCLK and Pxclk Frequencies When Pxclk Has SSC
65
Table 4.3 Port Clocking Mode Requirements
65
Table 4.4 Valid PES64H16AG2 System Clocking Configurations
65
Global Clocked Mode
66
Local Port Clocked Mode
67
Modification of a Port's Clock Mode
68
Table 4.5 Clock Frequency Limitations When Modifying a Port's Clock Mode
68
Reset and Initialization
69
Introduction
69
Table 5.1 PES64H16AG2 Reset Precedence
69
Boot Configuration Vector
70
Table 5.2 Boot Configuration Vector Signals
70
Switch Fundamental Reset
71
Switch Mode Dependent Initialization
74
Single Partition Mode
74
Table 5.3 Switch Mode Dependent Register Initialization
74
Port Merging
75
Partition Resets
76
Partition Fundamental Reset
76
Partition Hot Reset
77
Partition Upstream Secondary Bus Reset
77
Partition Downstream Secondary Bus Reset
78
Port Mode Change Reset
78
Switch Partitions
79
Introduction
79
Partition Configuration
79
Partition State
80
Fundamental Reset
80
Partition State Change
81
Switch Ports
82
Switch Port Mode
82
Downstream Switch Port
85
Port Operating Mode Change
85
Common Operating Mode Change Behavior
87
No Action Mode Change Behavior
92
Reset Mode Change Behavior
92
Hot Reset Mode Change Behavior
93
Partition and Port Configuration
93
Static Reconfiguration
93
Dynamic Reconfiguration
94
Link Operation
97
Introduction
97
Polarity Inversion
97
Lane Reversal
97
Link Width Negotiation
101
Link Width Negotiation in the Presence of Bad Lanes
102
Dynamic Link Width Reconfiguration
102
Link Speed Negotiation
102
Link Speed Negotiation in the PES64H16AG2
103
Software Management of Link Speed
104
Link Retraining
105
Link down
106
Slot Power Limit Support
106
Upstream Port
106
Downstream Port
106
Link States
107
Active State Power Management
107
L0S ASPM
108
L1 Aspm
108
L1 ASPM Entry Rejection Timer
109
Link Status
110
De-Emphasis Negotiation
110
Crosslink
111
Table 7.1 Crosslink Port Groups
111
Hot Reset Operation on a Crosslink
112
Link Disable Operation on a Crosslink
112
Gen1 Compatibility Mode
112
Table 7.2 Gen1 Compatibility Mode: Bits Cleared in Training Sets
113
Theory of Operation
115
Introduction
115
Transaction Routing
115
Interrupts
115
Table 8.1 Switch Routing Methods
115
Downstream Port Interrupts
116
Legacy Interrupt Emulation
116
Table 8.2 Downstream Port Interrupts
116
Access Control Services
117
Table 8.3 Downstream to Upstream Port Interrupt Routing Based on Device Number
117
Table 8.4 Prioritization of ACS Checks for Request Tlps
119
Error Detection and Handling
120
Table 8.5 Prioritization of ACS Checks for Completion Tlps
120
Table 8.6 TLP Types Affected by ACS Checks
120
Physical Layer Errors
121
Data Link Layer Errors
121
Table 8.7 Physical Layer Errors
121
Table 8.8 Data Link Layer Errors
121
Transaction Layer Errors
122
Table 8.9 Transaction Layer Errors Associated with the PCI-To-PCI Bridge Function
123
Table 8.10 Conditions Handled as Unsupported Requests (UR) by the PCI-To-PCI Bridge Function
125
Error Check
125
Table 8.11 Ingress TLP Formation Checks Associated with the PCI-To-PCI Bridge Function
125
Table 8.12 Egress Malformed TLP Error Checks
126
Table 8.13 ACS Violations for Ports Operating in Downstream Switch Port Mode
127
Table 8.14 Prioritization of Transaction Layer Errors
128
Table 10.1 Table
129
Routing Errors
130
Bus Locking
131
Introduction
135
Serdes Numbering and Port Association
135
Serdes Transmitter Controls
135
Driver Voltage Level and Amplitude Boost
135
De-Emphasis
136
Slew Rate
136
PCI Express Low-Swing Mode
136
Receiver Equalization
137
Programming of Serdes Controls
137
Programmable Voltage Margining and De-Emphasis
137
Serdes Transmitter Control Registers
138
Table 9.1 Serdes Transmit Level Controls in the S[X]Txlctl0 and S[X]Txlctl1 Registers
139
Table 9.2 Serdes Transmit Driver Settings in Gen1 Mode
140
Table 9.3 Serdes Transmit Driver Settings in Gen2 Mode with -3.5Db De-Emphasis
141
Table 9.4 Serdes Transmit Driver Settings in Gen2 Mode with -6.0Db De-Emphasis
142
Table 9.5 Transmitter Slew Rate Settings
145
Transmit Margining Using the PCI Express Link Control 2 Register
146
Table 9.6 PCI Express Transmit Margining Levels Supported by the PES64H16AG2
146
Low-Swing Transmitter Voltage Mode
147
Table 9.7 Serdes Transmit Drive Swing in Low Swing Mode at Gen1 Speed
147
Receiver Equalization Controls
148
Table 9.8 Serdes Transmit Drive Swing in Low Swing Mode at Gen2 Speed
148
Serdes Power Management
149
Hot-Plug and Hot-Swap
151
Introduction
151
Hot-Plug Signals
153
Port Reset Outputs
155
Power Enable Controlled Reset Output
155
Power Good Controlled Reset Output
156
Hot-Plug Events
156
Legacy System Hot-Plug Support
157
Hot-Swap
158
Power Management
159
Introduction
159
Table 11.1 PES64H16AG2 Power Management State Transition Diagram
160
PME Messages
161
PCI Express Power Management Fence Protocol
161
Upstream Switch Port or Downstream Switch Port Mode
161
Power Budgeting Capability
162
General Purpose I/O
163
Introduction
163
GPIO Configuration
163
Configured as an Input
163
Configured as an Output
163
Configured as an Alternate Function
163
Table 12.1 GPIO Pin Configuration
163
Table 12.2 General Purpose I/O Pin Alternate Function
164
Table 12.3 GPIO Alternate Function Pins
165
Smbus Interfaces
167
Introduction
167
Master Smbus Interface
167
Initialization
167
Figure 13.1 Split Smbus Interface Configuration
167
Serial EEPROM
168
Initialization from Serial EEPROM
168
Table 13.1 Serial EEPROM Smbus Address
168
Table 13.2 PES64H16AG2 Compatible Serial Eeproms
168
Figure 13.2 Single Double Word Initialization Sequence Format
169
Figure 13.3 Sequential Double Word Initialization Sequence Format
170
Figure 13.4 Configuration Done Sequence Format
170
Programming the Serial EEPROM
171
Table 13.3 Serial EEPROM Initialization Errors
171
I/O Expanders
172
Table 13.4 I/O Expander Function Allocation
172
Table 13.5 I/O Expander Default Output Signal Value
173
Table 13.7 Pin Mapping I/O Expander 8
176
Table 13.10 I/O Expander 11 - Partition Fundamental Reset Inputs
178
Table 13.11 I/O Expander 12 - Link up Status
179
Slave Smbus Interface
180
Initialization
180
Table 13.12 I/O Expander 13 - Link Activity Status
180
Table 13.13 Slave Smbus Address
180
Smbus Transactions
181
Table 13.14 Slave Smbus Command Code Fields
181
Figure 13.5 Slave Smbus Command Code Format
181
Table 13.15 CSR Register Read or Write Operation Byte Sequence
182
Figure 13.6 CSR Register Read or Write CMD Field Format
182
Table 13.16 CSR Register Read or Write CMD Field Description
183
Table 13.17 Serial EEPROM Read or Write Operation Byte Sequence
183
Table 13.18 Serial EEPROM Read or Write CMD Field Description
184
Figure 13.7 Serial EEPROM Read or Write CMD Field Format
184
Figure 13.8 CSR Register Read Using Smbus Block Write/Read Transactions with PEC Disabled
185
Figure 13.9 Serial EEPROM Read Using Smbus Block Write/Read Transactions with PEC
185
Figure 13.10 CSR Register Write Using Smbus Block Write Transactions with PEC Disabled
185
Figure 13.11 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Disabled
186
Figure 13.12 Serial EEPROM Write Using Smbus Block Write Transactions with PEC Enabled
186
Figure 13.13 CSR Register Read Using Smbus Read and Write Transactions with PEC Disabled
186
Multicast
187
Introduction
187
Addressing and Routing
187
Multicast TLP Determination
187
Figure 14.1 Multicast Group Address Ranges
188
Figure 14.2 Multicast Group Address Region Determination
189
Multicast TLP Routing
190
Multicast Egress Processing
190
Register Organization
193
Introduction
193
Table 15.1 Global Address Space Organization
193
Partial-Byte Access to Word and Dword Registers
194
Register Side-Effects
194
Address Maps
195
PCI-To-PCI Bridge Registers
195
Capability Structures
195
Table 15.2 Default PCI Capability List Linkage
196
Table 15.3 Default PCI Express Capability List Linkage
196
Figure 15.1 PCI-To-PCI Bridge Configuration Space Organization
197
Register Definition
198
Table 15.4 PCI-To-PCI Bridge Configuration Space Registers
198
IDT Proprietary Port Specific Registers
202
Figure 15.2 Proprietary Port Specific Register Organization
202
Table 15.5 Proprietary Port Specific Registers
203
Switch Configuration and Status Registers
204
Figure 15.3 Switch Configuration and Status Space Organization
204
Table 15.6 Switch Configuration and Status
205
PCI to PCI Bridge and Proprietary Port Specific Registers
211
Type 1 Configuration Header Registers
211
PCI Express Capability Structure
221
Power Management Capability Structure
237
Message Signaled Interrupt Capability Structure
239
Subsystem ID and Subsystem Vendor ID
241
Extended Configuration Space Access Registers
241
Advanced Error Reporting (AER) Enhanced Capability
242
Device Serial Number Enhanced Capability
251
PCI Express Virtual Channel Capability
252
Power Budgeting Enhanced Capability
257
ACS Extended Capability
259
Multicast Extended Capability
262
Proprietary Port Specific Registers
266
Port Control and Status Registers
266
Internal Error Control and Status Registers
268
Physical Layer Control and Status Registers
276
Power Management Control and Status Registers
279
Request Metering
279
Global Address Space Access Registers
281
Switch Configuration and Status Registers
283
Switch Control and Status Registers
283
Internal Switch Timer
286
Switch Partition and Port Registers
287
Protection
290
Serdes Control and Status Registers
290
General Purpose I/O Registers
298
Hot-Plug and Smbus Interface Registers
303
JTAG Boundary Scan
311
Introduction
311
Test Access Point
311
Signal Definitions
311
Figure 18.1 Diagram of the JTAG Logic
311
Table 18.1 JTAG Pin Descriptions
312
Figure 18.2 State Diagram of the TAP Controller
312
Boundary Scan Chain
313
Table 18.2 Boundary Scan Chain
313
Test Data Register (DR)
316
Boundary Scan Registers
316
Figure 18.3 Diagram of Observe-Only Input Cell
316
Figure 18.4 Diagram of Output Cell
317
Figure 18.5 Diagram of Bidirectional Cell
317
Instruction Register (IR)
318
Extest
318
Table 18.3 Instructions Supported by the JTAG Boundary Scan
318
Sample/Preload
319
Bypass
319
Clamp
319
Idcode
319
Table 18.4 System Controller Device Identification Register
319
Figure 18.6 Device ID Register Format
319
Validate
320
Extest_Train
320
Extest_Pulse
320
Reserved
320
Usage Considerations
320
Corporate Headquarters
321
Contact Information
321

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