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PEX 8624-AA RDK
PLX Technology PEX 8624-AA RDK Manuals
Manuals and User Guides for PLX Technology PEX 8624-AA RDK. We have
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PLX Technology PEX 8624-AA RDK manual available for free PDF download: Hardware Reference Manual
PLX Technology PEX 8624-AA RDK Hardware Reference Manual (46 pages)
Brand:
PLX Technology
| Category:
Industrial Equipment
| Size: 0 MB
Table of Contents
A T M
3
Revision History
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Table of Contents
4
1 General Information
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Figure 1-1. PEX 8624-AA RDK Front View
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PEX 8624 Features
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PEX 8624-AA RDK Features
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2 PEX 8624-AA RDK Hardware Architecture
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PEX 8624 PCI Express Gen 2 Switch
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PEX 8624-AA RDK PCI Express Interfaces
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Figure 2-1. PEX 8624-AA RDK Hardware Architecture
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Configuration Modules and Receptacle CM1
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Figure 2-2. PCI Express up to 5Gt/S Gen 2 Connections
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4X Mini-SAS Connector IP1
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PCI Express Card Edge Connector P1
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PCI Express Edge Card Connector SLOT 1
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PCI Express Edge Card Connector SLOT 2
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PCI Express Edge Card Connector SLOT 3
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Reference Clock Circuitry
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Figure 2-3. Use Mini-SAS Connector for NT Function Setup
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Figure 2-4. PEX 8624-AA RDK Reference Clock Circuit
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Reset Circuitry
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Hot-Plug Circuits
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Parallel Hot-Plug Controller Circuit
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Figure 2-5. PEX 8624-AA RDK Reset Circuit
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Serial Hot-Plug Controller Circuits
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Figure 2-6. PEX 8624-AA RDK PHP Circuits
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Serial EEPROM
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I 2 C Interface
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Figure 2-7. PEX 8624-AA RDK SERIAL HOT-PLUG Circuits
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Power Distribution
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LED Indicators
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Figure 2-8. PEX 8624-AA RDK Power Subsystem
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Table 2-1. PEX 8624-AA RDK LED Indicator Descriptions
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Fatal Error Indication (D24)
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PEX_INTA Interrupt Indication (D23)
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Port Link Status Indication (D17 - D22)
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Table 2-2. Port Link Status LED Functions
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GPIO Pins
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PEX 8624 Voltage Level Monitoring (D10 - D11)
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Reserved Pins
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Table 2-3. Voltage Level Monitoring LED Functions
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Table 2-4. Strap_Reserved Pin Connections
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3 On-Board Connectors, Switches, and Jumpers
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DIP Switches
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Slot ID Selection (SW1)
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Serial Hot-Plug Signal and Control (SW2)
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Figure 3-1. Switch SW1 Default Settings
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Figure 3-2. Switch SW2 Default Settings
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Table 3-1. Switch SW2 Description
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Parallel Hot-Plug Signal and Control (SW3)
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DC/DC Converter and Mode Controls (SW4)
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Figure 3-3. Switch SW3 Default Settings
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Figure 3-4. Switch SW4 Default Settings
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Table 3-2. Switch SW3 Description
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Upstream Port Select (SW5)
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Port Configuration and NT Upstream Port Select (SW6)
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Figure 3-5. Switch SW5 Default Settings
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Figure 3-6. Switch SW6 Default Settings
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Table 3-3. Switch SW5 Description
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Test Mode Select (SW7)
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Figure 3-7. Switch SW7 Default Settings
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Table 3-4. Switch SW6 Description
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I 2 C Address and Other Mode Select (SW8)
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Figure 3-8. Switch SW8 Default Settings
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Table 3-5. Switch SW7 Description
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Table 3-6. Switch SW8 Description
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Push-Button Switches
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Manual Reset# (S1)
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Serial Hot-Plug Controller Attention Button (S2)
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Parallel Hot-Plug Controller Attention Button (S3)
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Midbus Probe Footprints (JP1 - JP2)
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Figure 3-9. Midbus 2.0 Footprint Dimensions, Pin Numbering and Specification (Copied from Agilent's Document)
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Table 3-7. Signal Names of X8 PCI Express Midbus Probe Footprint
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Header (JP3)
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JTAG Header (JP4)
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I 2 C Port (JP5 - JP6)
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Table 3-8. Midbus Probe Footprints VS. Lanes of PEX 8624
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Table 3-9. Pin Assignment of JP4
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Table 3-10. Pin Assignment of JP5 and JP6
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ATX HD Power Connector (J1)
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Reference Clock Header (J2)
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Probe Mode Input Header (J3)
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Table 3-11. Pin Assignment of J1
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Table 3-12. Pin Assignment of J2
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Table 3-13. Pin Assignment of J3
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PLX Use Header (J4)
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Table 3-14. Pin Assignment of J4
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4 Bill of Materials/ Schematics
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