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PEX 8632-AA
PLX Technology PEX 8632-AA Manuals
Manuals and User Guides for PLX Technology PEX 8632-AA. We have
1
PLX Technology PEX 8632-AA manual available for free PDF download: Quick Start Manual
PLX Technology PEX 8632-AA Quick Start Manual (31 pages)
Brand:
PLX Technology
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
5
Notice
5
Revision History
5
1 Switch Interfaces
7
Introduction
7
Figure 1. Sample PCI Express Link Block Diagram
8
Figure 2. Single-Ended Versus Differential Voltage
9
Transmitter
9
Receiver
11
Receiver Equalizer Registers - 8-Port Mode
11
Receiver Equalizer Registers - 12-Port Mode
11
Table 1. Receiver Equalization Settings
11
Reference Clock
12
Channel
13
Figure 3. Transport Delay Delta
13
Figure 4. PEX 8632 Refclk Circuitry
13
PCI Express Link Interface
8
Figure 5. Enable NT Function with NT Strapping Balls
14
Figure 6. Disable NT Function with NT Strapping Balls
14
NT Function
14
Figure 7. PHPC Circuit Block Diagram
15
Hot Plug Controller Interface
15
Figure 8. SHPC Interface to PEX 8632 Block Diagram
16
Figure 9. JTAG Interface Block Diagram
17
JTAG Interface
17
C Interface
18
PCI Express Port Good Indicators
18
PCI Express Port Good Indicators - 8-Port Mode
18
PCI Express Port Good Indicators - 12-Port Mode
18
Figure 10. I 2 C Interface Block Diagram
18
Table 2. PEX 8632 LED On/Off Patterns, by State
18
Strapping Balls
19
Strapping Balls - 8 Port Mode
19
Table 3. Configuration Strapping Balls - 8-Port Mode
19
Table 4. Active Lanes - 8- and 12-Port Modes
20
Table 5. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements - 8-Port Mode
20
Strapping Balls - 12 Port Mode
21
Table 6. Configuration Strapping Balls - 12-Port Mode
21
GPIO Balls
22
GPIO Balls - 8-Port Mode
22
GPIO Balls - 12-Port Mode
22
Table 7. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements - 12-Port Mode
22
Power Supplies, Sequencing, and De-Coupling
23
Power Supplies
23
Figure 11. Power Balls and Capacitor Placement
23
Power Sequencing
24
Board-Level De-Coupling
25
Figure 12. Power Plane Impedance Versus Frequency
25
Figure 13. Capacitor Footprint Effects on Series Inductance
26
2 PCB Layout and Layer Stackup Considerations
27
BGA Routing Escape and De-Coupling Capacitor Placement
27
Figure 14. Top Layer BGA Layout and Routing Escape
28
Figure 15. Bottom Layer BGA Layout, Escape, and De-Coupling Capacitor Placement
28
Add-In Board Routing
29
System Board Routing
29
Figure 16. Add-In Board Routing to PCI Express Gold Fingers
29
Figure 17. System Board Routing to PCI Express Slot
29
Midbus Routing
30
PCB Layer Stackup Considerations
30
Figure 18. PCI Express Midbus Routing Example
30
3 References
31
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