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PEX 8614AA
PLX Technology PEX 8614AA Manuals
Manuals and User Guides for PLX Technology PEX 8614AA. We have
1
PLX Technology PEX 8614AA manual available for free PDF download: Hardware Reference Manual
PLX Technology PEX 8614AA Hardware Reference Manual (66 pages)
Base Board RDK
Brand:
PLX Technology
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
4
General Information
6
PEX 8614 Features
6
Figure 1. PEX 8614AA Base Board RDK Front View
7
PEX 8614AA-BB RDK Features
8
System Architecture
9
Hardware Architecture
9
Pex 8614
9
Figure 2. Connecting the RDK to a PC with X1 or X4 Link
9
PCI Express Interfaces
10
RDK Configuration Modules and Their Receptacles
10
PCI Express Lane 0 to Lane 3
10
Table 1. Port Configurations Supported by the RDK
10
PCI Express Lane 4 to Lane 7
11
Figure 3. Lanes 0-3 Hardware Connections on the RDK
11
PCI Express Lane 8 to Lane 11
12
Figure 4. Lanes 4-7 Hardware Connections on the RDK
12
Figure 5. Lanes 8-11 Hardware Connections on the RDK
12
Reference Clock Circuits
13
Reset Circuits
13
Figure 6. RDK Reference Clock Circuits
13
Serial Hot-Plug (SHP) Controller Circuits
14
Figure 7. RDK Reset Circuits
14
Serial EEPROM
15
I 2 C Interface
15
Figure 8. SERIAL HOT-PLUG Circuits
15
Power Distribution Circuits
16
Figure 9. RDK ATX Power Connectors
16
FPGA Interface
17
Figure 10. RDK Power Distribution Circuits
17
LED and 7-Segment Displays
18
LED Indicators
18
Figure 11. FPGA Interface on RDK
18
Table 2. RDK LED Indicator Descriptions
18
7-Segment Displays
19
Table 3. RDK 7-Segment Display Functions
19
GPIO Pins
20
Reserved Pins
20
Table 4. Strap_Reserved Pin Connections
20
On-Board Connectors, Switches, and Jumpers
21
DIP Switches
21
Dip Switch Group 1
21
Figure 12. RDK Dip Switch Groups
21
Figure 13. Group1 of Switches
21
Table 5. Functional Description of Group 1 Dip Switches
21
Dip Switch Group 2
22
Figure 14. Group 2 of Dipswitches
22
Table 6. Functional Description of Group 2 Dip Switches
23
Dip Switch Group 3
24
Figure 15. Group 3 of Dip Switches
24
Table 7. Port Configurations Use Dipswitch SW2
24
Push-Button Switches
25
Manual Reset# (S1)
25
FPGA Manual Reset# (S2)
25
Table 8. Functional Descriptions of SW3, SW6, SW13-SW14
25
Serial Hot-Plug Controller Attention Button (S3)
26
Connectors and Headers
26
ATX Peripheral Power Connectors (J1-J4 & J7-J8)
26
X4 PCI Express External Cable Connectors (J5 & J6)
26
Table 9. Signal Names of J1-J4 & J7-J8
26
Table 10. Signal Names of J5 and J6
26
ATX Main Power Connector (J9)
27
ATX +12V Power Connector(J10)
27
Xilinx JTAG Connector (J12)
27
Table 11. Signal Names of J9
27
Table 12. Signal Names of J10
27
Table 13. Signal Names of J12
27
Xilinx Mode Setting Header (J13)
28
PEX 8614 JTAG Header (JP3)
28
Smbus Header (JP5)
28
PCI Express X8 Midbus Probe Footprint (JP6)
28
Table 14. Signal Names of J13
28
Table 15. Pin Assignment of JP3
28
Table 16. Signal Names of JP5
28
Table 17. Signal Names of JP6
28
PEX 8614 I C Port (JP8)
29
Debug Signal Header (JP9 & JP11)
29
Table 18. Pin Assignment of JP8
29
Table 19. Pin Assignment of JP9 & JP11
29
Debug Input Header (JP10)
31
Reference Clock Header (JP100)
31
Table 20. Pin Assignment of JP10
31
Table 21. Pin Assignment of JP100
31
RDK Port Configurations
32
Figure 16. X1 Upstream and 11X1 Downstream (PCFG=0000)
32
Figure 17. X4 Upstream 8X1 Downstream (PCFG=0001)
33
Figure 18. X4 Upstream, 1X4 and 4X1 Downstream (PCFG=0010)
34
Bill of Materials/ Schematics
35
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