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phyCORE-MPC5676/57 Series
User Manuals: Phytec phyCORE-MPC5676/57 Series Module
Manuals and User Guides for Phytec phyCORE-MPC5676/57 Series Module. We have
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Phytec phyCORE-MPC5676/57 Series Module manual available for free PDF download: Hardware Manual
Phytec phyCORE-MPC5676/57 Series Hardware Manual (92 pages)
Brand:
Phytec
| Category:
Computer Hardware
| Size: 4 MB
Table of Contents
Table of Contents
3
List of Figures
5
Conventions, Abbreviations and Acronyms
7
Table 1: Signal Types Used in this Manual
8
Table 2: Abbreviations and Acronyms Used in this Manual
9
Preface
10
1 Introduction
13
Features of the Phycore-Mpc5676/57X
13
Internal Features of the MPC5676R
14
Memory Configuration of the Phycore-Mpc5676/57Xx
14
Other Board-Level Features
14
Block Diagram
15
Figure 1: Block Diagram of the Phycore-Mpc5676/57Xx
15
Phycore-Mpc5676/57Xx Component Placement
16
Figure 2: Phycore-Mpc5676/57Xx Component Placement (Top View)
16
Figure 3: Phycore-Mpc5676/57Xx Component Placement (Top View)
17
Minimum Requirements to Operate the Phycore-Mpc5676/57Xx
18
Phycore-Mpc5676/57Xx Without FPGA
18
Phycore-Mpc5676/57Xx with FPGA
18
2 Pin Description
19
Figure 4: Pinout of the Phycore-Connector (Top View)
20
Table 3: Pinout of the Phycore-Connector X1, Row a
21
Table 4: Pinout of the Phycore-Connector X1, Row B
23
Table 5: Pinout of the Phycore-Connector X2, Row a
26
Table 6: Pinout of the Phycore-Connector X2, Row B
28
Table 7: Pinout of the FPGA Connector X3, Row a
31
Table 8: Pinout of the FPGA Connector X3, Row B
33
3 Jumpers
36
Figure 5: Typical Jumper Pad Numbering Scheme
36
Figure 6: Jumper Locations (Top View)
37
Table 9: Jumper Settings
39
4 Power Requirements
46
Voltage Supervisor and Reset
47
5 System Configuration and Booting
48
Table 10: Boot Modes of the Phycore-Mpc5676/57Xx
48
6 System Memory
49
External Standard Flash Memory (U100,U101)
49
Table 11: Choice of Standard Flash Memory Devices and Manufacturers
49
Synchronous Burst SRAM(U102,U103)
50
Table 12: Memory Options for the Synchronous Burst SRAM
50
Spi Eeprom (U6)
51
EEPROM Write Protection Control (J30)
51
SPI Flash Memory (U19)
51
Table 13: EEPROM Write Protection States Via J30 and GPIO463
51
7 FPGA System Logic Device U18
52
Addressing the FPGA from MPC
52
Configuration of the FPGA
52
FPGA Connector X3
52
8 Serial Interfaces
53
Universal Asynchronous Interface
53
Table 14: Location of the UART Signals
53
8.2 CAN Interface
54
SPI Interface
54
Table 15: Location of the UART Signals
54
9 LAN9221I Ethernet Controller
55
Ethernet Transformer
55
Addressing the Ethernet Controller
56
Software Reset of the Ethernet Controller
56
MAC Address
56
Table 16: Location of the Ethernet Signals
56
10 Real-Time Clock M41T93 (U7)
57
11 Jtag/Once/Nexus Debufg Interface
58
Table 17: 14-Pin Jtag/Once Connector (X8) and Corresponding Pins on the Phycore-Connector (X2)
58
12 Technical Specifications
59
Figure 8: Physical Dimensions (Top View)
59
13 Hints for Integrating and Handling the Phycore-Mpc5676/57Xx
62
13.1 Integrating the Phycore-Mpc5676/57Xx
62
13.2 Handling the Phycore-Mpc5676/57Xx
62
14 The Phycore- MPC5676R on the Phycore Carrier Board
63
Concept of the Phycore Carrier Board
63
14.2 Overview of the Phycore Carrier Board Peripherals
64
Figure 9: Phycore Carrier Board Overview of Connectors, Leds and Buttons (Top View)
64
Connectors and Pin Header
65
Table 18: Phycore Carrier Board Connectors and Pin Headers
65
Leds
66
Switches
66
Table 19: Phycore Carrier Board Push Buttons Descriptions
66
Table 20: Phycore Carrier Board Leds Descriptions
66
Analog Input Potentiometer
67
Figure 10: Typical Jumper Numbering Scheme
67
Jumpers
67
Figure 11: Phycore Carrier Board Jumper Locations (Top View)
68
Table 21: Phycore Carrier Board Jumper Descriptions
69
14.3 Functional Components on the Phycore Carrier Board
70
Phycore- MPC5676R SOM Connectivity (X1, X2, X3)
70
Figure 12: Phycore- MPC5676R SOM Connectivity to the Carrier Board
70
Power (X8, X9)
71
Figure 13: Powering Scheme
71
Wall Adapter Input (X8)
72
Figure 14: Power Connector Corresponding to Wall Adapter Input X12
72
First Serial Interface at Socket P2A
73
Second Serial Interface at Socket P2B
73
Figure 15: Pin Assignment of P2A as First RS-232 (Front View)
73
Figure 16: Pin Assignment of P2B as Second RS-232 (Front View)
73
First CAN Interface at Plug P1A
74
14.3.6 Second CAN Interface at Plug P1B
74
Ethernet Connectivity (X28)
75
User Programmable Leds
75
Table 22: User Programmable Leds on the Carrier Board
75
Boot Mode Selection (BOOTCFG1)
76
Table 23: Phycore Carrier Board DIP Switch S3 Descriptions
76
System Reset Button (RESET1)
77
FPGA_JTAG Connector
78
Jtag/Once/Nexus Debug Interface
78
Reduced Jtag/Once/Nexus Pin Header Connector X
78
Table 24: Pin Assignment of the JTAG_FPGA Connector X6
78
Table 25: Pin Assignment of the Reduced Jtag/Once/Nexus Pin Header X7
78
14.3.14 Full Jtag/Once/Nexus Pin Header Connector X10
79
Table 26: Pin Assignment of the Full Jtag/Once/Nexus Pin Header X10
79
14.3.15 Phycore-Mpc5676/57Xx Expansion Connector
80
Figure 19: Expansion Connector Location on the Development Board KSP-0150-B0
80
Schematic of Carrier Board KSP-0180-Bx
81
Figure 20: Page 2/5 of KSP-0150-B0 Schematic
82
Figure 21: Page 3/5 of KSP-0150-B0 Schematic
83
Figure 22: Page 4/5 of KSP-0150-B0 Schematic
84
Figure 23: Page 5/5 of KSP-0150-B0 Schematic
85
15 Revision History
86
Index
87
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