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Mips Technologies MIPS32 M14K Manuals
Manuals and User Guides for Mips Technologies MIPS32 M14K. We have
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Mips Technologies MIPS32 M14K manual available for free PDF download: User Manual
Mips Technologies MIPS32 M14K User Manual (302 pages)
Processor Core Family Software
Brand:
Mips Technologies
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
5
List of Figures
13
Chapter 1: Introduction to the MIPS32® M14K™ Processor Core
20
1.1 Features
20
1.2 M14K™ Core Block Diagram
24
1: Execution Unit
24
1: Required Logic Blocks
25
Figure 1.1: M14K™ Processor Core Block Diagram
25
2: General Purposed Register (GPR) Shadow Registers
26
3: Multiply/Divide Unit (MDU)
26
4: System Control Coprocessor (CP0)
26
5: Memory Management Unit (MMU)
28
Figure 1.2 M14K™ Core Virtual Address Map
29
6: SRAM Interface Controller
30
Figure 1.3 Address Translation During SRAM Access with FMT Implementation
30
7: Power Management
31
1: Reference Design
32
2: Optional Logic Blocks
32
2: Micromips™ ISA
33
3: Memory Protection Unit
33
4: Coprocessor 2 Interface
33
Figure 1.4: Reference Design Block Diagram
33
5: Corextend® User-Defined Instruction Extensions
34
6: EJTAG Debug Support
34
Figure 1.5 FDC Overview
36
Figure 1.6 Cjtag Support
37
Chapter 2: Pipeline of the M14K™ Core
38
2.1 Pipeline Stages
38
Figure 2.1 M14K™ Core Pipeline Stages with High-Performance MDU
39
Figure 2.2: M14K™ Core Pipeline Stages with Area-Efficient MDU
39
1: I Stage: Instruction Fetch
40
2: E Stage: Execution
40
3: M Stage: Memory Fetch
40
4: a Stage: Align
41
5: W Stage: Writeback
41
2.2 Multiply/Divide Operations
41
2.3 MDU Pipeline - High-Performance MDU
41
Table 2.1 MDU Instruction Latencies (High-Performance MDU)
42
Table 2.2 MDU Instruction Repeat Rates (High-Performance MDU)
43
1: 32X16 Multiply (High-Performance MDU)
44
Figure 2.3 MDU Pipeline Behavior During Multiply Operations
44
2: 32X32 Multiply (High-Performance MDU)
45
3: Divide (High-Performance MDU)
45
Figure 2.4 MDU Pipeline Flow During a 32X16 Multiply Operation
45
Figure 2.5 MDU Pipeline Flow During a 32X32 Multiply Operation
45
MDU Pipeline - Area-Efficient MDU
46
Figure 2.6 High-Performance MDU Pipeline Flow During a 8-Bit Divide (DIV) Operation
46
Figure 2.7 High-Performance MDU Pipeline Flow During a 16-Bit Divide (DIV) Operation
46
Figure 2.8 High-Performance MDU Pipeline Flow During a 24-Bit Divide (DIV) Operation
46
Figure 2.9 High-Performance MDU Pipeline Flow During a 32-Bit Divide (DIV) Operation
46
1: Multiply (Area-Efficient MDU)
47
Figure 2.10: M14K™ Area-Efficient MDU Pipeline Flow During a Multiply Operation
47
Table 2.3: M14K™ Core Instruction Latencies (Area-Efficient MDU)
47
2: Multiply Accumulate (Area-Efficient MDU)
48
3: Divide (Area-Efficient MDU)
48
2.5 Branch Delay
48
Figure 2.11: M14K™ Core Area-Efficient MDU Pipeline Flow During a Multiply Accumulate Operation
48
Figure 2.12: M14K™ Core Area-Efficient MDU Pipeline Flow During a Divide (DIV) Operation
48
2.6 Data Bypassing
49
Figure 2.13 IU Pipeline Branch Delay
49
1: Load Delay
50
Figure 2.14 IU Pipeline Data Bypass
50
Figure 2.15 IU Pipeline M to E Bypass
50
2: Move from HI/LO and CP0 Delay
51
2.7 Coprocessor 2 Instructions
51
Figure 2.16 IU Pipeline a to E Data Bypass
51
Figure 2.17 IU Pipeline Slip after a MFHI
51
2.8 Interlock Handling
52
Figure 2.18 Coprocessor 2 Interface Transactions
52
2.9 Slip Conditions
53
Table 2.4 Pipeline Interlocks
53
2.10 Instruction Interlocks
54
Figure 2.19 Instruction Cache Miss Slip
54
Table 2.5 Instruction Interlocks
54
2.11 Hazards
55
1: Types of Hazards
55
2: Instruction Listing
56
Table 2.6 Execution Hazards
56
Table 2.7 Instruction Hazards
56
Table 2.8 Hazard Instruction Listing
56
1: Instruction Encoding
57
3: Eliminating Hazards
57
Chapter 3: Memory Management of the M14K™ Core
59
3.1 Introduction
59
1: Fixed Mapping Translation (FMT)
59
1: Memory Management Unit (MMU)
59
3.2 Modes of Operation
60
1: Virtual Memory Segments
60
Figure 3.1 Address Translation During SRAM Access
60
1: Unmapped Segments
61
2: User Mode
61
Figure 3.2 M14K™ Processor Core Virtual Memory Map
61
2: Mapped Segments
62
Figure 3.3: User Mode Virtual Address Space
62
Table 3.1: User Mode Segments
62
3: Kernel Mode
63
Figure 3.4 Kernel Mode Virtual Address Space
64
Table 3.2 Kernel Mode Segments
64
1: Kernel Mode, User Space (Kuseg)
65
2: Kernel Mode, Kernel Space 0 (Kseg0)
65
3: Kernel Mode, Kernel Space 1 (Kseg1)
65
4: Debug Mode
65
4: Kernel Mode, Kernel Space 2 (Kseg2)
65
5: Kernel Mode, Kernel Space 3 (Kseg3)
65
1: Conditions and Behavior for Access to Drseg, EJTAG Registers
66
Figure 3.5: Debug Mode Virtual Address Space
66
Table 3.3: Physical Address and Cache Attributes for Dseg, Dmseg, and Drseg Address Spaces
66
Table 3.4: CPU Access to Drseg Address Range
66
2: Conditions and Behavior for Access to Dmseg, EJTAG Memory
67
3.3 Fixed Mapping MMU
67
Table 3.5 CPU Access to Dmseg Address Range
67
Table 3.6 Cacheability of Segments with Block Address Translation
67
Figure 3.6: FMT Memory Map (ERL=0) in the M14K™ Processor Core
68
System Control Coprocessor
69
Figure 3.7: FMT Memory Map (ERL=1) in the M14K™ Processor Core
69
Chapter 4: Exceptions and Interrupts in the M14K™ Core
71
4.1 Exception Conditions
71
4.2 Exception Priority
72
Table 4.1 Priority of Exceptions
72
4.3 Interrupts
73
1: Interrupt Modes
73
1: Interrupt Compatibility Mode
74
Table 4.2 Interrupt Modes
74
2: Vectored Interrupt (VI) Mode
76
Table 4.3 Relative Interrupt Priority for Vectored Interrupt Mode
77
Figure 4.1: Interrupt Generation for Vectored Interrupt Mode
78
3: External Interrupt Controller Mode
79
Figure 4.2: Interrupt Generation for External Interrupt Controller Interrupt Mode
81
2: Generation of Exception Vector Offsets for Vectored Interrupts
82
Table 4.4 Exception Vector Offsets for Vectored Interrupts
82
1: Interrupt Delivery
83
2: Interrupt Latency Reduction
83
3: MCU ASE Enhancement for Interrupt Handling
83
4.4 GPR Shadow Registers
84
4.5 Exception Vector Locations
85
Table 4.5 Exception Vector Base Addresses
86
Table 4.6 Exception Vector Offsets
86
Table 4.7 Exception Vectors
86
4.6 General Exception Processing
87
Table 4.8 Value Stored in EPC, Errorepc, or DEPC on an Exception
87
4.7 Debug Exception Processing
89
4.8 Exception Descriptions
90
1: Reset/Softreset Exception
90
Table 4.9 Debug Exception Vector Addresses
90
2: Debug Single Step Exception
91
3: Debug Interrupt Exception
92
4: Non-Maskable Interrupt (NMI) Exception
92
5: Interrupt Exception
93
6: Debug Instruction Break Exception
93
7: Address Error Exception - Instruction Fetch/Data Access
93
Table 4.10 Register States an Interrupt Exception
93
8: SRAM Parity Error Exception
94
9: Bus Error Exception - Instruction Fetch or Data Access
94
Table 4.11 CP0 Register States on an Address Exception Error
94
Table 4.12 CP0 Register States on a SRAM Parity Error Exception
94
10: Protection Exception
95
11: Debug Software Breakpoint Exception
95
12: Execution Exception - System Call
95
13: Execution Exception - Breakpoint
96
14: Execution Exception - Reserved Instruction
96
15: Execution Exception - Coprocessor Unusable
96
16: Execution Exception - Corextend Unusable
97
17: Execution Exception - Coprocessor 2 Exception
97
18: Execution Exception - Implementation-Specific 1 Exception
97
Table 4.13 Register States on a Coprocessor Unusable Exception
97
19: Execution Exception - Integer Overflow
98
20: Execution Exception - Trap
98
21: Debug Data Break Exception
98
22: Complex Break Exception
99
4.9 Exception Handling and Servicing Flowcharts
99
Figure 4.3 General Exception Handler (HW)
100
Figure 4.4 General Exception Servicing Guidelines (SW)
101
Figure 4.5 Reset, Soft Reset and NMI Exception Handling and Servicing Guidelines
102
Chapter 5: CP0 Registers of the M14K™ Core
104
5.1 CP0 Register Summary
104
Table 5.1 CP0 Registers
104
5.2 CP0 Register Descriptions
106
1: Userlocal Register (CP0 Register 4, Select 2)
106
Figure 5.1 Userlocal Register Format
106
Table 5.2 CP0 Register R/W Field Types
106
2: Hwrena Register (CP0 Register 7, Select 0)
107
Figure 5.2 Hwrena Register Format
107
Table 5.3 Userlocal Register Field Descriptions
107
Table 5.4 Hwrena Register Field Descriptions
107
3: Badvaddr Register (CP0 Register 8, Select 0)
108
4: Badinstr Register (CP0 Register 8, Select 1)
108
Figure 5.3 Badvaddr Register Format
108
Table 5.5 Badvaddr Register Field Description
108
5: Badinstrp Register (CP0 Register 8, Select 2)
109
Figure 5.4 Badinstr Register Format
109
Figure 5.5 Badinstrp Register Format
109
Table 5.6 Badinstr Register Field Descriptions
109
6: Count Register (CP0 Register 9, Select 0)
110
7: Compare Register (CP0 Register 11, Select 0)
110
Figure 5.6 Count Register Format
110
Table 5.7 Badinstrp Register Field Descriptions
110
Table 5.8 Count Register Field Description
110
8: Status Register (CP0 Register 12, Select 0)
111
Figure 5.7: Compare Register Format
111
Figure 5.8 Status Register Format
111
Table 5.9 Compare Register Field Description
111
Table 5.10 Status Register Field Descriptions
112
9: Intctl Register (CP0 Register 12, Select 1)
115
Figure 5.9 Intctl Register Format
115
Table 5.11 Intctl Register Field Descriptions
116
10: Srsctl Register (CP0 Register 12, Select 2)
119
Figure 5.10 Srsctl Register Format
119
Table 5.12 Srsctl Register Field Descriptions
119
11: Srsmap Register (CP0 Register 12, Select 3)
122
Figure 5.11 Srsmap Register Format
122
Table 5.13: Sources for New Srsctl
122
Table 5.14 Srsmap Register Field Descriptions
122
12: View_Ipl Register (CP0 Register 12, Select 4)
123
13: Srsmap2 Register (CP0 Register 12, Select 5)
123
Figure 5-12 View_Ipl Register Format
123
Table 5.15 View_Ipl Register Field Descriptions
123
14: Cause Register (CP0 Register 13, Select 0)
124
Figure 5-13 Srsmap Register Format
124
Figure 5.14 Cause Register Format
124
Table 5.16 Srsmap Register Field Descriptions
124
Table 5.17 Cause Register Field Descriptions
124
Table 5.18 Cause Register Exccode Field
128
15: View_Ripl Register (CP0 Register 13, Select 4)
129
16: Nestedexc (CP0 Register 13, Select 5)
129
Figure 5-15 View_Ripl Register Format
129
Table 5.19 View_Ripl Register Field Descriptions
129
17: Exception Program Counter (CP0 Register 14, Select 0)
130
Figure 5-16 Nestedexc Register Format
130
Table 5.20 Nestedexc Register Field Descriptions
130
18: Nestedepc (CP0 Register 14, Select 2)
131
Figure 5.17 EPC Register Format
131
Table 5.21 EPC Register Field Description
131
19: Processor Identification (CP0 Register 15, Select 0)
132
Figure 5-18 Nestedepc Register Format
132
Figure 5.19 Prid Register Format
132
Table 5.22 Nestedepc Register Field Descriptions
132
Table 5.23 Prid Register Field Descriptions
132
20: Ebase Register (CP0 Register 15, Select 1)
133
21: Cdmmbase Register (CP0 Register 15, Select 2)
134
Figure 5.20 Ebase Register Format
134
Figure 5.21 Cdmmbase Register Format
134
Table 5.24 Ebase Register Field Descriptions
134
22: Config Register (CP0 Register 16, Select 0)
135
Figure 5.22: Config Register Format - Select 0
135
Table 5.25 Cdmmbase Register Field Descriptions
135
Table 5.26: Config Register Field Descriptions
136
23: Config1 Register (CP0 Register 16, Select 1)
137
Figure 5.23: Config1 Register Format - Select 1
137
Table 5.27 Cache Coherency Attributes
137
Table 5.28: Config1 Register Field Descriptions - Select 1
137
24: Config2 Register (CP0 Register 16, Select 2)
138
Figure 5.24: Config2 Register Format - Select 2
138
Table 5.29: Config2 Register Field Descriptions - Select 1
138
25: Config3 Register (CP0 Register 16, Select 3)
139
Figure 5-25: Config3 Register Format
139
Table 5.30: Config3 Register Field Descriptions
139
26: Config4 Register (CP0 Register 16, Select 4)
142
27: Config5 Register (CP0 Register 16, Select 5)
142
Figure 5-26: Config4 Register Format
142
Table 5.31: Config4 Register Field Descriptions
142
28: Config7 Register (CP0 Register 16, Select 7)
143
29: Debug Register (CP0 Register 23, Select 0)
143
Figure 5-27: Config5 Register Format
143
Figure 5.28: Config7 Register Format
143
Table 5.32: Config5 Register Field Descriptions
143
Table 5.33: Config7 Register Field Descriptions
143
Figure 5.29 Debug Register Format
144
Table 5.34 Debug Register Field Descriptions
144
30: Trace Control Register (CP0 Register 23, Select 1)
148
Figure 5.30 Tracecontrol Register Format
148
Table 5.35 Tracecontrol Register Field Descriptions
148
31: Trace Control2 Register (CP0 Register 23, Select 2)
150
Figure 5.31 Tracecontrol2 Register Format
150
Table 5.36 Tracecontrol2 Register Field Descriptions
150
32: User Trace Data1 Register (CP0 Register 23, Select 3)/User Trace Data2 Register (CP0 Register 24, Select 3)
151
33: Tracebpc Register (CP0 Register 23, Select 4)
152
Figure 5.32 User Trace Data1/User Trace Data2 Register Format
152
Figure 5.33 Trace BPC Register Format
152
Table 5.37 Usertracedata1/Usertracedata2 Register Field Descriptions
152
Table 5.38 Tracebpc Register Field Descriptions
152
34: Debug2 Register (CP0 Register 23, Select 6)
153
Figure 5.34 Debug2 Register Format
153
35: Debug Exception Program Counter Register (CP0 Register 24, Select 0)
154
Table 5.39 Debug2 Register Field Descriptions
154
36: Performance Counter Register (CP0 Register 25, Select 0-3)
155
Figure 5.35 DEPC Register Format
155
Table 5.40 DEPC Register Formats
155
Table 5.41 Performance Counter Register Selects
155
Figure 5.36 Performance Counter Control Register
156
Table 5.42 Performance Counter Control Register Field Descriptions
156
Table 5.43 Performance Counter Events Sorted by Event Number
156
Table 5.44 Performance Counter Event Descriptions Sorted by Event Type
158
Figure 5.37 Performance Counter Count Register
159
37: Errctl Register (CP0 Register 26, Select 0)
160
38: Cacheerr Register (CP0 Register 27, Select 0)
160
Figure 5.38 Errctl Register Format
160
Figure 5.39 Cacheerr Register (Primary Caches)
160
Table 5.45 Performance Counter Count Register Field Descriptions
160
Table 5.46 Errctl Register Field Descriptions
160
Table 5.47 Cacheerr Register Field Descriptions (Primary Caches)
161
Figure 5.40 Errorepc Register Format
162
Figure 5.41 Desave Register Format
162
Table 5.48 Errorepc Register Field Description
162
Table 5.49 Desave Register Field Description
162
Figure 5-42 Kscratchn Register Format
163
Table 5.50 Kscratchn Register Field Descriptions
163
Figure 8.1 DCR Register Format
172
Table 8.1 DCR Register Field Descriptions
172
Table 8.2 Addresses for Instruction Breakpoint Registers
182
Figure 8.2 IBS Register Format
183
Figure 8.3 Iban Register Format
183
Table 8.3 IBS Register Field Descriptions
183
Table 8.4 Iban Register Field Descriptions
183
Figure 8.4 Ibmn Register Format
184
Figure 8.5 Ibasidn Register Format
184
Table 8.5 Ibmn Register Field Descriptions
184
Table 8.6 Ibasidn Register Field Descriptions
184
Figure 8.6 Ibcn Register Format
185
Table 8.7 Ibcn Register Field Descriptions
185
Figure 8.7 Ibccn Register Format
186
Table 8.8 Ibccn Register Field Descriptions
186
Figure 8.8 Ibpcn Register Format
187
Table 8.10 Addresses for Data Breakpoint Registers
187
Table 8.9 Ibpcn Register Field Descriptions
187
Figure 8.10 Dban Register Format
188
Figure 8.9 DBS Register Format
188
Table 8.11 DBS Register Field Descriptions
188
Table 8.12 Dban Register Field Descriptions
188
Figure 8.11 Dbmn Register Format
189
Figure 8.12 Dbasidn Register Format
189
Figure 8.13 Dbcn Register Format
189
Table 8.13 Dbmn Register Field Descriptions
189
Table 8.14 Dbasidn Register Field Descriptions
189
Table 8.15 Dbcn Register Field Descriptions
190
Figure 8.14 Dbvn Register Format
191
Table 8.16 Dbvn Register Field Descriptions
191
Figure 8.15 Dbccn Register Format
192
Table 8.17 Dbccn Register Field Descriptions
192
Figure 8.16 Dbpcn Register Format
193
Figure 8.17 DVM Register Format
193
Table 8.18 Dbpcn Register Field Descriptions
193
Table 8.19 DVM Register Field Descriptions
193
Figure 8.18 CBTC Register Format
194
Table 8.20 Addresses for Complex Breakpoint Registers
194
Table 8.21 CBTC Register Field Descriptions
194
Figure 8.19 Prcnda Register Format
195
Table 8.22 Prcnda Register Field Descriptions
196
Table 8.23: Priming Conditions and Register Values for 6I/2D Configuration
196
Table 8.24: Priming Conditions and Register Values for 8I/4D Configuration
196
Figure 8.20 Stctl Register Format
197
Table 8.25 Stctl Register Field Descriptions
197
Figure 8.21 Stcnt Register Format
198
Table 8.26: Stctl Register Field Descriptions
198
Table 8.27 EJTAG Interface Pins
202
Figure 8.22 TAP Controller State Diagram
204
Table 8.28 Implemented EJTAG Instructions
207
Figure 8.23 Concatenation of the EJTAG Address, Data and Control Registers
208
Figure 8.24 TDI to TDO Path When in Shift-DR State and FASTDATA Instruction Is Selected
209
Figure 8.25: Device Identification Register Format
210
Figure 8.26 Implementation Register Format
211
Table 8.29: Device Identification Register
211
Table 8.30 Implementation Register Descriptions
211
Figure 8.27 EJTAG Control Register Format
212
Table 8.31 EJTAG Control Register Descriptions
213
Figure 8.28 Endian Formats for the PAD Register
219
Figure 8.29 Fastdata Register Format
219
Table 8.32 Fastdata Register Field Description
219
Table 8.33 Operation of the FASTDATA Access
220
Table 8.34 Ej_Disableprobedebug Signal Overview
223
Figure 8.30 Trace Logic Overview
228
Table 8.35 Data Bus Encoding
229
Table 8.36 Tag Bit Encoding
229
Figure 8.31 Control/Status Register
230
Table 8.37 Control/Status Register Field Descriptions
231
Figure 8.32 ITCBTW Register Format
232
Table 8.38 ITCBTW Register Field Descriptions
232
Figure 8.33 ITCBRDP Register Format
233
Figure 8.34 ITCBWRP Register Format
233
Table 8.39 ITCBRDP Register Field Descriptions
233
Table 8.40 ITCBWRP Register Field Descriptions
233
Table 8.41 Drseg Registers that Enable/Disable Trace from Breakpoint-Based Triggers
234
Figure 8.35 PCSAMPLE TAP Register Format (MIPS32)
235
Figure 8.36 Fast Debug Channel Buffer Organization
238
Figure 8.37 FDC TAP Register Format
239
Table 8.42 FDC TAP Register Field Descriptions
239
Figure 8.38 FDC Access Control and Status Register
240
Table 8.43 FDC Register Mapping
240
Table 8.44 FDC Access Control and Status Register Field Descriptions
240
Figure 8.39: FDC Configuration Register
241
Table 8.45: FDC Configuration Register Field Descriptions
241
Figure 8.40 FDC Status Register
242
Table 8.46 FDC Status Register Field Descriptions
242
Figure 8.41 FDC Receive Register
243
Figure 8.42 FDC Transmit Register
243
Table 8.47 FDC Receive Register Field Descriptions
243
Figure 8.43: Cjtag Interface
244
Table 8.48 FDC Transmit Register Field Descriptions
244
Table 8.49 Fdtxn Address Decode
244
Figure 9.1: Instruction Formats
247
Table 9.1 Byte Access Within a Word
248
Table 10.1 Encoding of the Opcode Field
253
Table 10.2 Special Opcode Encoding of Function Field
253
Table 10.3 Special2 Opcode Encoding of Function Field
253
Table 10.4 Special3 Opcode Encoding of Function Field
254
Table 10.5 Regimm Encoding of Rt Field
254
Table 10.6 COP2 Encoding of Rs Field
254
Table 10.7 COP2 Encoding of Rt Field When Rs=Bc2
254
Table 10.10 Instruction Set
255
Table 10.8 COP0 Encoding of Rs Field
255
Table 10.9 COP0 Encoding of Function Field When Rs=Co
255
Figure 11.1 16-Bit Instruction Formats
286
Figure 11.2 32-Bit Instruction Formats
287
Figure 11.3 Immediate Fields Within 32-Bit Instructions
287
Table 11.1 16-Bit Re-Encoding of Frequent MIPS32 Instructions
290
Table 11.2 16-Bit Re-Encoding of Frequent MIPS32 Instruction Sequences
291
Table 11.3: Instruction-Specific Register Specifiers and Immediate Field Values
293
Table 11.4 16-Bit Instruction General-Purpose Registers - $2-$7, $16, $17
294
Table 11.5 SB16, SH16, SW16 Source Registers - $0, $2-$7, $17
295
Table 11.6 16-Bit Instruction Implicit General-Purpose Registers
295
Table 11.7 16-Bit Instruction Special-Purpose Registers
296
Table 11.8 32-Bit Instructions Introduced Within Micromips
296
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