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MIPS32® M14K™ Processor Core Family

Software User's Manual

Document Number: MD00668

Revision 02.04

March 24, 2014

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Page 1 MIPS32® M14K™ Processor Core Family Software User’s Manual Document Number: MD00668 Revision 02.04 March 24, 2014...
Page 2 Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party. MIPS, MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPSr3, MIPS32, MIPS64, microMIPS32, microMIPS64, MIPS-3D, MIPS16,...
Page 3 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 4 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 5: Table Of Contents
Table of Contents Chapter 1: Introduction to the MIPS32® M14K™ Processor Core ............. 4 1.1: Features ..............................4 1.2: M14K™ Core Block Diagram ........................8 1.2.1: Required Logic Blocks ........................9 1.2.1.1: Execution Unit .......................... 9 1.2.1.2: General Purposed Register (GPR) Shadow Registers............10 1.2.1.3: Multiply/Divide Unit (MDU) .....................
Page 6 2.11.3: Eliminating Hazards ........................41 Chapter 3: Memory Management of the M14K™ Core ..............43 3.1: Introduction..............................43 3.1.1: Memory Management Unit (MMU) ....................43 3.1.1.1: Fixed Mapping Translation (FMT) ..................43 3.2: Modes of Operation ........................... 44 3.2.1: Virtual Memory Segments........................ 44 3.2.1.1: Unmapped Segments ......................
Page 7 4.8.14: Execution Exception — Reserved Instruction ................80 4.8.15: Execution Exception — Coprocessor Unusable ................80 4.8.16: Execution Exception — CorExtend Unusable................81 4.8.17: Execution Exception — Coprocessor 2 Exception................. 81 4.8.18: Execution Exception — Implementation-Specific 1 Exception............81 4.8.19: Execution Exception — Integer Overflow..................82 4.8.20: Execution Exception —...
Page 8 5.2.39: ErrorEPC (CP0 Register 30, Select 0) ..................145 5.2.40: DeSave Register (CP0 Register 31, Select 0) ................146 5.2.41: KScratchn Registers (CP0 Register 31, Selects 2 to 3)............... 146 Chapter 6: Hardware and Software Initialization of the M14K™ Core ........... 149 6.1: Hardware-Initialized Processor State ......................
Page 9 8.2.8.4: Stopwatch Timer Count (STCnt) Register (0x8908) ............. 182 8.3: Complex Breakpoint Usage........................182 8.3.1: Checking for Presence of Complex Break Support................ 182 8.3.2: General Complex Break Behavior....................183 8.3.3: Usage of Pass Counters ........................ 183 8.3.4: Usage of Tuple Breakpoints......................184 8.3.5: Usage of Priming Conditions......................
Page 10 8.5.4: Fastdata Register (TAP Instruction FASTDATA) ................203 8.6: TAP Processor Accesses ........................204 8.6.1: Fetch/Load and Store from/to EJTAG Probe Through dmseg ............205 8.7: SecureDebug............................206 8.7.1: Disabling EJTAG Debugging ......................206 8.7.1.1: EJ_DisableProbeDebug Signal .................... 206 8.7.1.2: Override for EjtagBrk and DINT Disable................207 8.7.2: EJTAG Features Unmodified by SecureDebug ................
Page 11 9.6: Coprocessor Instructions......................... 233 9.7: Enhancements to the MIPS Architecture....................233 9.7.1: CLO - Count Leading Ones......................234 9.7.2: CLZ - Count Leading Zeros......................234 9.7.3: MADD - Multiply and Add Word ..................... 234 9.7.4: MADDU - Multiply and Add Unsigned Word .................. 234 9.7.5: MSUB - Multiply and Subtract Word ....................
Page 12 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 13 List of Figures Figure 1.1: M14K™ Processor Core Block Diagram ....................9 Figure 1.2: M14K™ Core Virtual Address Map ...................... 13 Figure 1.3: Address Translation During SRAM Access with FMT Implementation ..........14 Figure 1.4: Reference Design Block Diagram......................17 Figure 1.5: FDC Overview............................
Page 14 Figure 5.11: SRSMap Register Format......................... 106 Figure 5-12: View_IPL Register Format........................ 107 Figure 5-13: SRSMap Register Format......................... 108 Figure 5.14: Cause Register Format........................108 Figure 5-15: View_RIPL Register Format ......................113 Figure 5-16: NestedExc Register Format......................114 Figure 5.17: EPC Register Format ........................115 Figure 5-18: NestedEPC Register Format ......................
Page 15 Figure 8.22: TAP Controller State Diagram ......................188 Figure 8.23: Concatenation of the EJTAG Address, Data and Control Registers ..........192 Figure 8.24: TDI to TDO Path When in Shift-DR State and FASTDATA Instruction is Selected ......193 Figure 8.25: Device Identification Register Format ....................194 Figure 8.26: Implementation Register Format ......................
Page 16 MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 17 List of Tables Table 2.1: MDU Instruction Latencies (High-Performance MDU) ................26 Table 2.2: MDU Instruction Repeat Rates (High-Performance MDU)..............27 Table 2.3: M14K™ Core Instruction Latencies (Area-Efficient MDU) ..............31 Table 2.4: Pipeline Interlocks ..........................37 Table 2.5: Instruction Interlocks ..........................38 Table 2.6: Execution Hazards ..........................
Page 18 Table 5.21: EPC Register Field Description......................115 Table 5.22: NestedEPC Register Field Descriptions .................... 116 Table 5.23: PRId Register Field Descriptions ....................... 116 Table 5.24: EBase Register Field Descriptions..................... 118 Table 5.25: CDMMBase Register Field Descriptions.................... 119 Table 5.26: Config Register Field Descriptions..................... 120 Table 5.27: Cache Coherency Attributes ......................
Page 19 Table 8.22: PrCndA Register Field Descriptions....................180 Table 8.25: STCtl Register Field Descriptions ...................... 181 Table 8.26: STCtl Register Field Descriptions ...................... 182 Table 8.27: EJTAG Interface Pins ........................186 Table 8.28: Implemented EJTAG Instructions ...................... 191 Table 8.30: Implementation Register Descriptions ....................195 Table 8.29: Device Identification Register......................
Page 20: Chapter 1: Introduction To The Mips32® M14K™ Processor Core
Chapter 1 Introduction to the MIPS32® M14K™ Processor Core The MIPS32® M14K™ core from MIPS Technologies is a high-performance, low-power, 32-bit MIPS RISC proces- sor core intended for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripher- als with a high-performance RISC processor.
Page 21 1.1 Features • MIPS32 Instruction Set Architecture • MIPS32 Enhanced Architecture Features • Vectored interrupts and support for external interrupt controller • Programmable exception vector base • Atomic interrupt enable/disable • GPR shadow registers (one, three, seven, or ﬁfteen additional shadows can be optionally added to minimize latency for interrupt handlers) •...
Page 22 Introduction to the MIPS32® M14K™ Processor Core • Simple Fixed Mapping Translation (FMT) mechanism • Memory Protection Unit • Optional feature that improves system security by restricting access, execution, and trace capabilities from untrusted code in predeﬁned memory regions. • Simple SRAM-Style Interface •...
Page 23 1.1 Features • Maintains full MIPS32 compatibility • Supported by industry-standard development tools • Single or multi-cycle instructions • Multi-Core Support • External lock indication enables multi-processor semaphores based on LL/SC instructions • External sync indication allows memory ordering • Debug support includes cross-core triggers •...
Page 24: 1.2 M14K™ Core Block Diagram
Introduction to the MIPS32® M14K™ Processor Core • Support for Fast Debug Channel (FDC) • SecureDebug • An optional feature that disables access via EJTAG in an untrusted environment • Testability • Full scan design achieves test coverage in excess of 99% (dependent on library and conﬁguration options) 1.2 M14K™...
Page 26: 2: General Purposed Register (Gpr) Shadow Registers
Introduction to the MIPS32® M14K™ Processor Core 1.2.1.2 General Purposed Register (GPR) Shadow Registers The M14K core contains thirty-two 32-bit general-purpose registers used for integer operations and address calcula- tion. Optionally, one, three, seven or ﬁfteen additional register ﬁle shadow sets (each containing thirty-two registers) can be added to minimize context switching overhead during interrupt/exception processing.
Page 27 1.2 M14K™ Core Block Diagram Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data, external events, or program errors. Interrupt Handling The M14K core includes support for eight hardware interrupt pins, two software interrupts, and a timer interrupt. These interrupts can be used in any of three interrupt modes, as deﬁned by Release 2 of the MIPS32 Architecture: •...
Page 28: 5: Memory Management Unit (Mmu)
Introduction to the MIPS32® M14K™ Processor Core Shadow sets are new copies of the GPRs that can be substituted for the normal GPRs on entry to kernel mode via an interrupt or exception. When a shadow set is bound to a kernel-mode entry condition, references to GPRs operate exactly as one would expect, but they are redirected to registers that are dedicated to that condition.
Page 29: Figure 1.2 M14K™ Core Virtual Address Map
1.2 M14K™ Core Block Diagram Figure 1.2 M14K™ Core Virtual Address Map 0xFFFFFFFF Fix Mapped 0xFF400000 0xFF3FFFFF kseg3 Memory/EJTAG 0xFF200000 0xF1FFFFFF Fix Mapped 0xE0000000 0xDFFFFFFF Kernel Virtual Address Space kseg2 Fix Mapped, 512 MB 0xC0000000 0xBFFFFFFF Kernel Virtual Address Space kseg1 Unmapped, 512 MB Uncached...
Page 30: 6: Sram Interface Controller
Introduction to the MIPS32® M14K™ Processor Core Figure 1.3 Address Translation During SRAM Access with FMT Implementation Virtual Physical Instruction Address Address Address Inst Calculator SRAM SRAM interface Data SRAM Data Address Physical Virtual Calculator Address Address 1.2.1.6 SRAM Interface Controller Instead of caches, the M14K core contains an interface to SRAM-style memories that can be tightly coupled to the core.
Page 31: 7: Power Management
1.2 M14K™ Core Block Diagram core, and thus eliminate the need for external registers to gather the entire 32 bits of data. External muxes are required to redirect the narrower data to the appropriate byte lanes. Lock Mechanism The SRAM interface includes a protocol to identify a locked sequence, and is used in conjunction with the LL/SC atomic read-modify-write semaphore instructions.
Page 32: 2: Optional Logic Blocks
Introduction to the MIPS32® M14K™ Processor Core Instruction-Controlled Power Management The second mechanism for invoking power-down mode is by executing the WAIT instruction. When the WAIT instruction is executed, the internal clock is suspended; however, the internal timer and some of the input pins , and ) continue to run.
Page 34: 5: Corextend® User-Defined Instruction Extensions
Introduction to the MIPS32® M14K™ Processor Core 1.2.2.5 CorExtend® User-deﬁned Instruction Extensions An optional CorExtend User-deﬁned Instruction (UDI) block enables the implementation of a small number of appli- cation-speciﬁc instructions that are tightly coupled to the core’s execution unit. The interface to the UDI block is external to the M14K core.
Page 35 1.2 M14K™ Core Block Diagram • Four data and eight instruction breakpoints, with or without complex breakpoints Instruction breakpoints occur on instruction execution operations, and the breakpoint is set on the virtual address. A mask can be applied to the virtual address to set breakpoints on a binary range of instructions. Data breakpoints occur on load/store transactions, and the breakpoint is set on a virtual address value, with the same single address or binary address range as the Instruction breakpoint.
Page 36: Figure 1.5 Fdc Overview
Introduction to the MIPS32® M14K™ Processor Core Figure 1.5 FDC Overview M14K Probe EJTAG Receive from FIFO Probe to Core Transmit from FIFO Core to Probe Tap Controller iFlowtrace™ The M14K core has an option for a simple trace mechanism named iFlowtrace. This mechanism only traces the instruction PC, not data addresses or values.
Page 37: Figure 1.6 Cjtag Support
1.2 M14K™ Core Block Diagram Figure 1.6 cJTAG Support M14K EJTAG cJTAG EJTAG 4-wire 2-wire interface interface cJTAG TMSC Conversion Controller Block SecureDebug SecureDebug improves security by disabling untrusted EJTAG debug access. An input signal is used to disable debug features, such as Probe Trap, Debug Interrupt Exception (EjtagBrk and DINT), EJTAGBOOT instruction, and PC Sampling.
Page 38: Chapter 2: Pipeline Of The M14K™ Core
Chapter 2 Pipeline of the M14K™ Core The M14K processor core implements a 5-stage pipeline similar to the original M4K pipeline. The pipeline allows the processor to achieve high frequency while minimizing device complexity, reducing both cost and power con- sumption.
Page 39: Figure 2.1 M14K™ Core Pipeline Stages With High-Performance Mdu
2.1 Pipeline Stages The M14K core implements a bypass mechanism that allows the result of an operation to be forwarded directly to the instruction that needs it without having to write the result to the register and then read it back. The M14K soft core includes a build-time option that determines the type of multiply/divide unit (MDU) imple- mented.
Page 40: 1: I Stage: Instruction Fetch
Pipeline of the M14K™ Core 2.1.1 I Stage: Instruction Fetch During the Instruction fetch stage: • An instruction is fetched from the instructionSRAM. • If both MIPS32 and microMIPS ISAs are supported, microMIPS instructions are converted to MIPS32-like instructions. If the MIPS32 ISA is not supported, 16-bit microMIPS instructions will be ﬁrst recoded into 32-bit microMIPS equivalent instructions, and then decoded in native microMIPS ISA format.
Page 41: 4: A Stage: Align
2.2 Multiply/Divide Operations 2.1.4 A Stage: Align During the Align stage: • Load data is aligned to its word boundary. • A multiply/divide operation updates the HI/LO registers (area-efﬁcient MDU option). • Multiply operation performs the carry-propagate-add. The actual register writeback is performed in the W stage (high-performance MDU option).
Page 42: Table 2.1 Mdu Instruction Latencies (High-Performance Mdu)
Pipeline of the M14K™ Core The MDU consists of a 32x16 Booth-encoded multiplier array, a carry propagate adder, result/accumulation registers (HI and LO), multiply and divide state machines, and all necessary multiplexers and control logic. The ﬁrst number shown (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The core only checks the latter (rt) operand value to determine how many times the operation must pass through the mul- tiplier array.
Page 43: Table 2.2 Mdu Instruction Repeat Rates (High-Performance Mdu)
2.3 MDU Pipeline - High-performance MDU Table 2.1, a latency of one means that the ﬁrst and second instructions can be issued back-to-back in the code, without the MDU causing any stalls in the IU pipeline. A latency of two means that if issued back-to-back, the IU pipeline will be stalled for one cycle.
Page 44: 1: 32X16 Multiply (High-Performance Mdu)
Pipeline of the M14K™ Core Figure 2.3 MDU Pipeline Behavior During Multiply Operations cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 Mult Mult The following is a cycle-by-cycle analysis of Figure 2.3. The ﬁrst 32x16 multiply operation (Mult ) is fetched from the instruction cache and enters the I stage.
Page 45: 2: 32X32 Multiply (High-Performance Mdu)
2.3 MDU Pipeline - High-performance MDU Figure 2.4 MDU Pipeline Flow During a 32x16 Multiply Operation Clock Booth Array 2.3.2 32x32 Multiply (High-Performance MDU) The 32x32 multiply operation begins in the last phase of the E stage, which is shared between the integer and MDU pipelines.
Page 46: Mdu Pipeline - Area-Efficient Mdu
Pipeline of the M14K™ Core Figure 2.6 High-Performance MDU Pipeline Flow During a 8-bit Divide (DIV) Operation Clock 4-10 Stage E Stage Stage Stage Stage Stage Stage RS Adjust Add/Subtract Add/Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2.7 High-Performance MDU Pipeline Flow During a 16-bit Divide (DIV) Operation Clock 4-18...
Page 47: 1: Multiply (Area-Efficient Mdu)
2.4 MDU Pipeline - Area-Efficient MDU tive numbers. Adjustment before and after are thus required depending on the sign of the operands. All divide opera- tions complete in 33 to 35 clocks. Table 2.3 lists the latencies (number of cycles until a result is available) for multiply and divide instructions. The latencies are listed in terms of pipeline clocks.
Page 48: 2: Multiply Accumulate (Area-Efficient Mdu)
Pipeline of the M14K™ Core 2.4.2 Multiply Accumulate (Area-Efﬁcient MDU) Multiply-accumulate operations use the same multiply machine as used for multiply only. Two extra stages are needed to perform the addition/subtraction. The operations uses 34 cycles in M stage to complete the multi- ply-accumulate.
Page 49: 2.6 Data Bypassing
2.6 Data Bypassing being injected into the pipeline on branch instructions. Both the address calculation and the branch condition check are performed in the E stage. The pipeline begins the fetch of either the branch path or the fall-through path in the cycle following the delay slot. After the branch decision is made, the processor continues with the fetch of either the branch path (for a taken branch) or the fall-through path (for the non-taken branch).
Page 50: 1: Load Delay
Pipeline of the M14K™ Core Figure 2.14 IU Pipeline Data Bypass I stage E stage M stage A stage W stage A to E bypass M to E bypass Rs Addr Instruction Rs Read Rt Addr E stage M stage Reg File Rd Write Rt Read...
Page 51: 2: Move From Hi/Lo And Cp0 Delay
2.7 Coprocessor 2 Instructions Figure 2.16 IU Pipeline A to E Data bypass One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle Load Instruction Data bypass from A to E Consumer of Load Data Instruction One Clock Load Delay 2.6.2 Move from HI/LO and CP0 Delay As indicated in...
Page 52: 2.8 Interlock Handling
Pipeline of the M14K™ Core If all the expected control and data signals were presented to the core in the previous M stage, the core will pro- ceed to execute the A stage. If some return information is missing, the A stage will not advance and cause a slip in all I, E, and M stages (see 2.9 “Slip Conditions”...
Page 53: 2.9 Slip Conditions
2.9 Slip Conditions Table 2.4 lists the types of pipeline interlocks for the M14K processor core. Table 2.4 Pipeline Interlocks Interlock Type Sources Slip Stage I-side SRAM Stall SRAM Access not complete E Stage Instruction Producer-consumer hazards E/M Stage Hardware Dependencies (MDU) E Stage BC2 waiting for COP2 Condition Check D-side SRAM Stall...
Page 54: 2.10 Instruction Interlocks
Pipeline of the M14K™ Core Figure 2.19 Instruction Cache Miss Slip Clock Stage 1 Cache miss detected 2 Critical word received 3 Execute E-stage In the ﬁrst clock cycle in Figure 2.19, the pipeline is full and the cache miss is detected. Instruction I is in the A stage, instruction I is in the M stage, instruction I...
Page 55: 2.11 Hazards
2.11 Hazards Table 2.5 Instruction Interlocks (Continued) Instruction Interlocks Issue Delay (in First Instruction Second Instruction Clock Cycles) Slip Stage 16bx32b Non-Consumer of target data E stage (high-performance MDU) 32bx32b E stage MFHI/MFLO Consumer of target data E stage MULTx/MADDx/MSUBx 16bx32b MULT/MUL/MADD/MSUB E stage...
Page 56: 2: Instruction Listing
Pipeline of the M14K™ Core Execution hazards are those created by the execution of one instruction, and seen by the execution of another instruc- tion. Table 2.6 lists execution hazards. Table 2.6 Execution Hazards Spacing Producer → Consumer Hazard On (Instructions) →...
Page 57: 1: Instruction Encoding
2.11 Hazards Table 2.8 Hazard Instruction Listing (Continued) Mnemonic Function JALR.HB Clear both execution and instruction hazards JR.HB Clear both execution and instruction hazards SYNCI Synchronize caches after instruction stream write 2.11.2.1 Instruction Encoding The EHB instruction is encoded using a variant of the NOP/SSNOP encoding. This encoding was chosen for compat- ibility with the Release 1 SSNOP instruction, such that existing software may be modiﬁed to be compatible with both Release 1 and Release 2 implementations.
Page 58 Pipeline of the M14K™ Core MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 59: Chapter 3: Memory Management Of The M14K™ Core
Chapter 3 Memory Management of the M14K™ Core The M14K™ processor core includes a Memory Management Unit (MMU) that interfaces between the execution unit and the cache controller. The core implements a simple Fixed Mapping Translation (FMT) style MMU. This chapter contains the following sections: •...
Page 60: 3.2 Modes Of Operation
Memory Management of the M14K™ Core Figure 3.1 Address Translation During SRAM Access Virtual Physical Instruction Address Address Address Instn Calculator SRAM SRAM Interface Data SRAM Data Address Physical Virtual Calculator Address Address 3.2 Modes of Operation The M14K core implements three modes of operation: •...
Page 61: 1: Unmapped Segments
3.2 Modes of Operation Figure 3.2 M14K™ processor core Virtual Memory Map Virtual Address User Mode Kernel Mode Debug Mode 0xFFFF_FFFF kseg3 0xFF40_0000 dseg kseg3 0xFF3F_FFFF kseg3 0xFF20_0000 0xFF1F_FFFF kseg2 kseg2 0xE000_0000 0xDFFF_FFFF 0xC000_0000 kseg1 kseg1 0xBFFF_FFFF 0xA000_0000 0x9FFF_FFFF kseg0 kseg0 0x8000_0000 0x7FFF_FFFF...
Page 63: 3: Kernel Mode
3.2 Modes of Operation All valid user mode virtual addresses have their most signiﬁcant bit cleared to 0, indicating that user mode can only access the lower half of the virtual memory map. Any attempt to reference an address with the most signiﬁcant bit set while in user mode causes an address error exception.
Page 64: Figure 3.4 Kernel Mode Virtual Address Space
Memory Management of the M14K™ Core Figure 3.4 Kernel Mode Virtual Address Space 0xFFFF_FFFF Kernel virtual address space kseg3 Fix Mapped, 512MB 0xE000_0000 0xDFFF_FFFF Kernel virtual address space kseg2 Fix Mapped, 512MB 0xC000_0000 0xBFFF_FFFF Kernel virtual address space kseg1 Unmapped, Uncached, 512MB 0xA000_0000 0x9FFF_FFFF Kernel virtual address space...
Page 65: 1: Kernel Mode, User Space (Kuseg)
3.2 Modes of Operation 3.2.3.1 Kernel Mode, User Space (kuseg) In Kernel mode, when the most-signiﬁcant bit of the virtual address (A31) is cleared, the 32-bit kuseg virtual address space is selected and covers the full 2 bytes (2 GBytes) of the current user address space mapped to addresses 0x0000_0000 - 0x7FFF_FFFF.
Page 67: 2: Conditions And Behavior For Access To Dmseg, Ejtag Memory
3.3 Fixed Mapping MMU unpredictable, and writes are ignored to any unimplemented register in the drseg. Refer to Chapter 8, “EJTAG Debug Support in the M14K™ Core” on page 155 for more information on the The allowed access size is limited for the drseg. Only word size transactions are allowed. Operation of the processor is undeﬁned for other transaction sizes.
Page 70 Memory Management of the M14K™ Core MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 71: Chapter 4: Exceptions And Interrupts In The M14K™ Core
Chapter 4 Exceptions and Interrupts in the M14K™ Core The M14K™ processor core receives exceptions from a number of sources, including arithmetic overﬂows, I/O inter- rupts, and system calls. When the CPU detects one of these exceptions, the normal sequence of instruction execution is suspended and the processor enters kernel mode.
Page 72: 4.2 Exception Priority
Exceptions and Interrupts in the M14K™ Core When an exception condition is detected on an instruction fetch, the core aborts that instruction and all instructions that follow. When this instruction reaches the W stage, various CP0 registers are written with the exception state, change the current program counter (PC) to the appropriate exception vector address, and clearing the exception bits of earlier pipeline stages.
Page 73: 4.3 Interrupts
4.3 Interrupts Table 4.1 Priority of Exceptions (Continued) Exception Description Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare. CBrk EJTAG complex breakpoint. 4.3 Interrupts In the MIPS32® Release 1 architecture, support for exceptions included two software interrupts, six hardware inter- rupts, and a special-purpose timer interrupt.
Page 74: 1: Interrupt Compatibility Mode
Exceptions and Interrupts in the M14K™ Core Table 4.2 shows the current interrupt mode of the processor as a function of the Coprocessor 0 register ﬁelds that can affect the mode. Table 4.2 Interrupt Modes Interrupt Mode Compatibly Compatibility Compatibility ≠0 Vectored Interrupt ≠0...
Page 75 4.3 Interrupts xori k0, k0, 0x17 /* 14..23 => 9..0 */ k0, k0, VS /* Shift to emulate software IntCtl k1, VectorBase /* Get base of 10 interrupt vectors */ addu k0, k0, k1 /* Compute target from base and offset */ /* Jump to specific exception routine */ * Each interrupt processing routine processes a specific interrupt, analogous * to those reached in VI or EIC interrupt mode.
Page 76: 2: Vectored Interrupt (Vi) Mode
Exceptions and Interrupts in the M14K™ Core re-enable interrupts */ * Process interrupt here, including clearing device interrupt. * In some environments this may be done with a thread running in * kernel or user mode. Such an environment is well beyond the scope of * this example.
Page 77: Table 4.3 Relative Interrupt Priority For Vectored Interrupt Mode
4.3 Interrupts = 0, and = 0), an interrupt is signaled and a priority encoder scans the values in the order shown Status Status Table 4.3. Table 4.3 Relative Interrupt Priority for Vectored Interrupt Mode Interrupt Vector Number Relative Interrupt Interrupt Request Generated by...
Page 79: 3: External Interrupt Controller Mode
4.3 Interrupts k1, ~IMbitsToClear /* Get Im bits to clear for this interrupt */ this must include at least the IM bit */ for the current interrupt, and may include */ others */ k0, k0, k1 /* Clear bits in copy of Status */ /* If switching shadow sets, write new value to SRSCtl here */ k0, zero, S_StatusEXL, (W_StatusKSU+W_StatusERL+W_StatusEXL)
Page 80 Exceptions and Interrupts in the M14K™ Core The external interrupt controller prioritizes its interrupt requests and produces the priority level and the vector num- ber of the highest priority interrupt to be serviced. The priority level, called the Requested Interrupt Priority Level (RIPL), is an 8-bit encoded value in the range 0..255, inclusive.
Page 82: 2: Generation Of Exception Vector Offsets For Vectored Interrupts
Exceptions and Interrupts in the M14K™ Core k0, StatusSave /* Save in memory */ k0, k1, S_StatusIPL, 6 /* Set IPL to RIPL in copy of Status */ mfc0 k1, C0_SRSCtl /* Save SRSCtl if changing shadow sets */ k1, SRSCtlSave /* If switching shadow sets, write new value to SRSCtl here */ k0, zero, S_StatusEXL, (W_StatusKSU+W_StatusERL+W_StatusEXL)
Page 83: 3: Mcu Ase Enhancement For Interrupt Handling
4.3 Interrupts The general equation for the exception vector offset for a vectored interrupt is: vectorOffset ← 16#200 + (vectorNumber × (IntCtl || 2#00000)) When using large vector spacing and EIC mode, the offset value can overlap with bits that are speciﬁed in the EBase register.
Page 84: 4.4 Gpr Shadow Registers
Exceptions and Interrupts in the M14K™ Core Automated Interrupt Epilogue A mirror to the Automated Prologue, this features automates the restoration of some of the COP0 registers from the stack and the preparation of some of the COP0 registers for returning to non-exception mode. This feature is imple- mented within the IRET instruction, which is introduced in this ASE.
Page 85: 4.5 Exception Vector Locations
4.5 Exception Vector Locations is copied to SRSCtl SRSCtl is updated from one of the following sources: SRSCtl • The appropriate ﬁeld of the register, based on IPL, if the exception is an interrupt, = 1, SRSMap Cause = 0, and = 1.
Page 86: Table 4.5 Exception Vector Base Addresses
Exceptions and Interrupts in the M14K™ Core vector selection. To avoid complexity in the table, the vector address value assumes that the register, as imple- EBase mented in Release 2 devices, is not changed from its reset state and that is 0.
Page 87: 4.6 General Exception Processing
4.6 General Exception Processing Table 4.7 Exception Vectors (Continued) Vector For Release 2 Implementations, assumes that EBase retains its reset EJTAG Status Status Cause state and that IntCtl Exception ProbEn Interrupt 16#8000.0200 Interrupt 16#BFC0.0380 Interrupt 16#BFC0.0400 All others 16#8000.0180 All others 16#BFC0.0380 ‘x’...
Page 88 Exceptions and Interrupts in the M14K™ Core The value loaded into represents the restart address for the exception and need not be modiﬁed by exception handler software in the normal case. Software need not look at the bit in the register unless it wishes to Cause identify the address of the instruction that actually caused the exception.
Page 89: 4.7 Debug Exception Processing
4.7 Debug Exception Processing /* Calculate the vector base address */ if Status = 1 then vectorBase ← 16#BFC0.0200 else if ArchitectureRevision ≥ 2 then /* The fixed value of EBase forces the base to be in kseg0 or kseg1 */ 31..30 vectorBase ←...
Page 90: 4.8 Exception Descriptions
Exceptions and Interrupts in the M14K™ Core ← DebugExceptionType Debug D* bits ← HaltStatusAtDebugException Debug Halt ← DozeStatusAtDebugException Debug Doze ← 1 Debug if EJTAGControlRegister = 1 then ProbTrap PC ← 0xFF20_0200 else PC ← 0xBFC0_0480 endif The same debug exception vector location is used for all debug exceptions. The location is determined by the Prob- Trap bit in the EJTAG Control register (ECR), as shown in Table 4.9.
Page 91: 2: Debug Single Step Exception
4.8 Exception Descriptions Operation: Config ← ConfigurationState ← 0 Status ← 1 Status ← 0 Status ← 0/1 (depending on Reset or SoftReset) Status ← 0 Status ← 1 Status if InstructionInBranchDelaySlot then ErrorEPC ← PC - 4 else ErrorEPC ← PC endif PC ←...
Page 92: 3: Debug Interrupt Exception
Exceptions and Interrupts in the M14K™ Core 4.8.3 Debug Interrupt Exception A debug interrupt exception is either caused by the bit in the register (controlled through the EjtagBrk EJTAG Control TAP), or caused by the debug interrupt request signal to the CPU. The debug interrupt exception is an asynchronous debug exception which is taken as soon as possible, but with no speciﬁc relation to the executed instructions.
Page 93: 5: Interrupt Exception
4.8 Exception Descriptions ErrorEPC ← PC endif PC ← 0xBFC0_0000 4.8.5 Interrupt Exception The interrupt exception occurs when one or more of the eight hardware, two software, or timer interrupt requests is enabled by the register, and the interrupt input is asserted. See 4.3 “Interrupts”...
Page 94: 8: Sram Parity Error Exception
Exceptions and Interrupts in the M14K™ Core Note that in the case of an instruction fetch that is not aligned on a word boundary, PC is updated before the condition is detected. Therefore, both point to the unaligned instruction address. In the case of a data access BadVAddr the exception is taken if either an unaligned address or an address that was inaccessible in the current processor mode was referenced by a load or store instruction.
Page 95: 10: Protection Exception
4.8 Exception Descriptions DBE: Error on a data reference Additional State Saved: None Entry Vector Used: General exception vector (offset 0x180) 4.8.10 Protection Exception The protection exception occurs when an access to memory that has been protected by the Memory Protection Unit has been attempted.
Page 96: 13: Execution Exception - Breakpoint
Exceptions and Interrupts in the M14K™ Core Entry Vector Used: General exception vector (offset 0x180) 4.8.13 Execution Exception — Breakpoint The breakpoint exception is one of the execution exceptions. All of these exceptions have the same priority. A break- point exception occurs when a BREAK instruction is executed. Cause Register ExcCode Value: Additional State Saved: None...
Page 97: 16: Execution Exception - Corextend Unusable
4.8 Exception Descriptions Additional State Saved: Table 4.13 Register States on a Coprocessor Unusable Exception Register State Value Cause Unit number of the coprocessor being referenced Entry Vector Used: General exception vector (offset 0x180) 4.8.16 Execution Exception — CorExtend Unusable The CorExtend unusable exception is one of the execution exceptions.
Page 98: 19: Execution Exception - Integer Overflow
Exceptions and Interrupts in the M14K™ Core Cause Register ExcCode Value: Additional State Saved: Depending on the coprocessor 2 implementation, additional state information of the exception can be saved in a coprocessor 2 control register. Entry Vector Used: General exception vector (offset 0x180) 4.8.19 Execution Exception —...
Page 99: 22: Complex Break Exception
4.9 Exception Handling and Servicing Flowcharts Additional State Saved: None Entry Vector Used: Debug exception vector 4.8.22 Complex Break Exception A complex data break exception occurs when the complex hardware breakpoint detects an enabled breakpoint. Com- plex breaks are taken imprecisely—the instruction that actually caused the exception is allowed to complete and the register and DBD bit in the register point to a following instruction.
Page 100: Figure 4.3 General Exception Handler (Hw)
Exceptions and Interrupts in the M14K™ Core Figure 4.3 General Exception Handler (HW) Exceptions other than Reset, Soft Reset, NMI, EJTag Debug and cache error, or first-level TLB miss. Note: Interrupts can be masked by IE or IMs and Watch is masked if EXL = 1 Comments BadVA is set only for AdEL/S exceptions.
Page 101: Figure 4.4 General Exception Servicing Guidelines (Sw)
4.9 Exception Handling and Servicing Flowcharts Figure 4.4 General Exception Servicing Guidelines (SW) Comments * EXL=1 so Watch, Interrupt exceptions disabled * OS/System to avoid all other exceptions MFC0 - * Only Reset, Soft Reset, NMI exceptions possible. EPC, Status, Cause MTC0 - Set Status bits: (Optional - only to enable Interrupts while keeping Kernel...
Page 102: Figure 4.5 Reset, Soft Reset And Nmi Exception Handling And Servicing Guidelines
Exceptions and Interrupts in the M14K™ Core Figure 4.5 Reset, Soft Reset and NMI Exception Handling and Servicing Guidelines Reset Exception Config ← Reset state Status: Soft Reset or NMI Exception RP ← 0 Status: BEV ← 1 BEV ← 1 TS ←...
Page 103 4.9 Exception Handling and Servicing Flowcharts MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 104: Chapter 5: Cp0 Registers Of The M14K™ Core
Chapter 5 CP0 Registers of the M14K™ Core The System Control Coprocessor (CP0) provides the register interface to the M14K processor core for the support of memory management, address translation, exception handling, and other privileged operations. Each CP0 register is identiﬁed by a Register Number, from 0 through 31, and a Select Number that is used as the value in the sel ﬁeld of the MFC0 and MTC0 instructions.
Page 105 5.1 CP0 Register Summary Table 5.1 CP0 Registers (Continued) Register Select Number Number Register Name Function Status Processor status and control IntCtl Interrupt system status and control SRSCtl Shadow Register Sets status and control SRSMap1 Shadow set IPL mapping View_IPL Contiguous view of IM and IPL ﬁelds SRSMAP2 Shadow set IPL mapping...
Page 106: 5.2 Cp0 Register Descriptions
CP0 Registers of the M14K™ Core 5.2 CP0 Register Descriptions This section contains descriptions of each CP0 register.The registers are listed in numerical order, ﬁrst by Register Number, then by Select Number. For each register described below, ﬁeld descriptions include the read/write properties of the ﬁeld (shown in Table 5.2) and the reset state of the ﬁeld.
Page 107: 2: Hwrena Register (Cp0 Register 7, Select 0)
5.2 CP0 Register Descriptions Table 5.3 UserLocal Register Field Descriptions Fields Read / Name Bit(s) Description Write Reset State UserLocal 31:0 This ﬁeld contains software information that is not interpreted by Undeﬁned hardware. Programming Notes Privileged software may write this register with arbitrary information and make it accessible to unprivileged software via register 29 ( ) of the RDHWR instruction.
Page 108: 3: Badvaddr Register (Cp0 Register 8, Select 0)
CP0 Registers of the M14K™ Core instruction, and returning the virtualized value. For example, if it is not desirable to provide direct access to the Count register, access to that register may be individually disabled and the return value can be virtualized by the operating system.
Page 109: 5: Badinstrp Register (Cp0 Register 8, Select 2)
5.2 CP0 Register Descriptions Presence of the register is indicated by the bit. The register is instantiated per-VPE in an BadInstr Conﬁg3 BadInstr MT ASE processor. Figure 5.4 shows the proposed format of the BadInstr register; Table 5.6 describes the BadInstr register ﬁelds.
Page 110: 6: Count Register (Cp0 Register 9, Select 0)
CP0 Registers of the M14K™ Core Table 5.7 BadInstrP Register Field Descriptions Fields Read / Reset Name Bits Description Write State BadInstrP 31:0 Prior branch instruction. Undeﬁned Instruction words smaller than 32 bits are placed in bits 15:0, with bits 31:16 containing zero. 5.2.6 Count Register (CP0 Register 9, Select 0) register acts as a timer, incrementing at a constant rate, whether or not an instruction is executed, retired, Count...
Page 111: 8: Status Register (Cp0 Register 12, Select 0)
5.2 CP0 Register Descriptions Compare Register Format Figure 5.7 Compare Table 5.9 Compare Register Field Description Fields Name Bit(s) Description Read/Write Reset State Compare 31:0 Interval count compare value. Undeﬁned 5.2.8 Status Register (CP0 Register 12, Select 0) register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic Status states of the processor.
Page 112: Table 5.10 Status Register Field Descriptions
CP0 Registers of the M14K™ Core Table 5.10 Status Register Field Descriptions Fields Name Bits Description Read/Write Reset State Controls access to coprocessor 3. COP3 is not supported. This bit cannot be written and will read as 0. Controls access to coprocessor 2. This bit can only be writ- ten if coprocessor is attached to the COP2 interface.
Page 113 5.2 CP0 Register Descriptions Table 5.10 Status Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State Indicates that the entry through the reset exception vector 1 for Soft was due to a Soft Reset: Reset; 0 other- wise Encoding Meaning Not Soft Reset (NMI or Reset)
Page 114 CP0 Registers of the M14K™ Core Table 5.10 Status Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State IM1:IM0 Interrupt Mask: Controls the enabling of each of the soft- Undeﬁned ware interrupts. Refer to Section 4.3 “Interrupts”for a complete discussion of enabled interrupts.
Page 115: 9: Intctl Register (Cp0 Register 12, Select 1)
5.2 CP0 Register Descriptions Table 5.10 Status Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State Exception Level; Set by the processor when any exception Undeﬁned other than Reset, Soft Reset, or NMI exceptions is taken. Encoding Meaning Normal level Exception level When...
Page 116: Table 5.11 Intctl Register Field Descriptions
CP0 Registers of the M14K™ Core Table 5.11 IntCtl Register Field Descriptions Fields Reset Name Bits Description Read/Write State IPTI 31:29 For Interrupt Compatibility and Vectored Interrupt Externally modes, this ﬁeld speciﬁes the IP number to which the Timer Interrupt request is merged, and allows software to determine whether to consider Cause for a poten-...
Page 117 5.2 CP0 Register Descriptions Table 5.11 IntCtl Register Field Descriptions (Continued) Fields Reset Name Bits Description Read/Write State IPFDC 25:23 For Interrupt Compatibility and Vectored Interrupt Preset or modes, this ﬁeld speciﬁes the IP number to which the Externally Fast Debug Channel Interrupt request is merged, and allows software to determine whether to consider Cause for a potential interrupt.
Page 118 CP0 Registers of the M14K™ Core Table 5.11 IntCtl Register Field Descriptions (Continued) Fields Reset Name Bits Description Read/Write State ClrEXL For Auto-Prologue feature and IRET instruction. If set, during Auto-Prologue and IRET interrupt chain- ing, the KSU/ERL/EXL ﬁelds are cleared. Encoding Meaning Fields are not cleared by these opera-...
Page 119: 10: Srsctl Register (Cp0 Register 12, Select 2)
5.2 CP0 Register Descriptions Table 5.11 IntCtl Register Field Descriptions (Continued) Fields Reset Name Bits Description Read/Write State Vector Spacing. If vectored interrupts are implemented (as denoted by Conﬁg3 Conﬁg3 ), this ﬁeld VInt VEIC speciﬁes the spacing between vectored interrupts. Spacing Spacing Between...
Page 120 CP0 Registers of the M14K™ Core Table 5.12 SRSCtl Register Field Descriptions (Continued) Fields Reset Name Bits Description Read/Write State 29:26 Highest Shadow Set. This ﬁeld contains the highest Preset shadow set number that is implemented by this proces- sor. A value of zero in this ﬁeld indicates that only the normal GPRs are implemented.
Page 121 5.2 CP0 Register Descriptions Table 5.12 SRSCtl Register Field Descriptions (Continued) Fields Reset Name Bits Description Read/Write State Previous Shadow Set. If GPR shadow registers are implemented, and with the exclusions noted in the next paragraph, this ﬁeld is copied from the ﬁeld when an exception or interrupt occurs.
Page 122: 11: Srsmap Register (Cp0 Register 12, Select 3)
CP0 Registers of the M14K™ Core 5.2.11 SRSMap Register (CP0 Register 12, Select 3) Table 5.13 Sources for new SRSCtl on an Exception or Interrupt SRSCtl Source Exception Type Condition Comment Exception SRSCtl Non-Vectored Cause SRSCtl Treat as exception Interrupt Vectored Interrupt Cause = 1 and...
Page 123: 12: View_Ipl Register (Cp0 Register 12, Select 4)
5.2 CP0 Register Descriptions 5.2.12 View_IPL Register (CP0 Register 12, Select 4) Figure 5-12 View_IPL Register Format Table 5.15 View_IPL Register Field Descriptions Fields Read / Name Bits Description Write Reset State Interrupt Mask. Undeﬁned for If EIC interrupt mode is not enabled, controls which inter- IM7:IM2 rupts are enabled.
Page 124: 14: Cause Register (Cp0 Register 13, Select 0)
CP0 Registers of the M14K™ Core Figure 5-13 SRSMap Register Format SSV9 SSV8 Table 5.16 SRSMap Register Field Descriptions Fields Read / Reset Name Bits Description Write State 31:8 Must be written as zero; returns zero on read. SSV9 Shadow register set number for Vector Number 9 SSV8 Shadow register set number for Vector Number 8 5.2.14 Cause Register (CP0 Register 13, Select 0)
Page 125 5.2 CP0 Register Descriptions Table 5.17 Cause Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State Timer Interrupt. This bit denotes whether a timer inter- Undeﬁned rupt is pending (analogous to the bits for other inter- rupt types): Encoding Meaning No timer interrupt is pending...
Page 126 CP0 Registers of the M14K™ Core Table 5.17 Cause Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State Indicates whether an exception occurred during Inter- Undeﬁned rupt Auto-Prologue. Encoding Meaning Exception did not occur during Auto-Prologue operation. Exception occurred during Auto-Pro- logue operation.
Page 127 5.2 CP0 Register Descriptions Table 5.17 Cause Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State FDCI Fast Debug Channel Interrupt. This bit denotes whether Undeﬁned a FDC Interrupt is pending (analogous to the bits for other interrupt types): Encoding Meaning No Fast Debug Channel interrupt is...
Page 128: Table 5.18 Cause Register Exccode Field
CP0 Registers of the M14K™ Core Table 5.17 Cause Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State IP1:IP0 Controls the request for software interrupts: Undeﬁned Name Meaning Request software interrupt 1 Request software interrupt 0 These bits are exported to an external interrupt control- ler for prioritization in EIC interrupt mode with other interrupt sources.
Page 129: 15: View_Ripl Register (Cp0 Register 13, Select 4)
5.2 CP0 Register Descriptions Table 5.18 Cause Register ExcCode Field (Continued) Exception Code Value Decimal Hexadecimal Mnemonic Description 16#1e Parity Error Parity error. In normal mode, a parity error exception has a dedicated vector and the Cause register is not updated. If a parity error occurs while in Debug Mode, this code is written to the Debug DExcCode...
Page 130: 17: Exception Program Counter (Cp0 Register 14, Select 0)
CP0 Registers of the M14K™ Core This register is part of the Nested Fault feature. The existence of the register can be determined by reading the bit. Conﬁg5 NFExists Figure 5-16 shows the format of the register; Table 5.20 describes the register ﬁelds.
Page 131: 18: Nestedepc (Cp0 Register 14, Select 2)
5.2 CP0 Register Descriptions • The virtual address of the immediately preceding branch or jump instruction, when the exception-causing instruction is in a branch delay slot, and the bit in the register is set. Branch Delay Cause On new exceptions, the processor does not write to the register when the bit in the register is set;...
Page 132: 19: Processor Identification (Cp0 Register 15, Select 0)
Company ID 23:16 Company Identiﬁer. Identiﬁes the company that designed or manufactured the processor. In the M14K this ﬁeld con- tains a value of 1 to indicate MIPS Technologies, Inc. MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 133: 20: Ebase Register (Cp0 Register 15, Select 1)
15:8 Processor Identiﬁer. Identiﬁes the type of processor. This 0x9B ﬁeld allows software to distinguish between the various types of MIPS Technologies processors. Revision Processor Revision. Speciﬁes the revision number of the Preset processor. This ﬁeld allows software to distinguish between different revisions of the same processor type.
Page 134: 21: Cdmmbase Register (Cp0 Register 15, Select 2)
CP0 Registers of the M14K™ Core If the value of the exception base register is to be changed, this must be done with equal 1. The operation of Status the processor is UNDEFINED if the Exception Base ﬁeld is written with a different value when is 0.
Page 135: 22: Config Register (Cp0 Register 16, Select 0)
5.2 CP0 Register Descriptions Table 5.25 CDMMBase Register Field Descriptions Fields Name Bits Description Read/Write Reset State CDMM_UP 31:11 Bits 35:15 of the base physical address of the mem- Undeﬁned PER_ADDR ory mapped registers. The number of implemented physical address bits is implementation-speciﬁc.
Page 136: Table 5.26: Config Register Field Descriptions
CP0 Registers of the M14K™ Core Table 5.26 Conﬁg Register Field Descriptions Fields Name Bit(s) Description Read/Write Reset State This bit is hardwired to ‘1’ to indicate the presence of the Conﬁg1 register. 30:28 This ﬁeld controls the cacheability of the kseg2 and kseg3 FM: R/W FM: 010 address segments in FM implementations.
Page 137: 23: Config1 Register (Cp0 Register 16, Select 1)
5.2 CP0 Register Descriptions Table 5.27 Cache Coherency Attributes C(2:0) Value Cache Coherency Attribute Uncached. Cached (Core treats as uncached, but passes attribute to the system for use with any exter- nal caching mechanisms) 5.2.23 Conﬁg1 Register (CP0 Register 16, Select 1) register is an adjunct to the register and encodes additional information about capabilities present Conﬁg1...
Page 138: 24: Config2 Register (Cp0 Register 16, Select 2)
CP0 Registers of the M14K™ Core Table 5.28 Conﬁg1 Register Field Descriptions — Select 1 (Continued) Fields Name Bit(s) Description Read/Write Reset State Coprocessor 2 present. Preset 0: No coprocessor is attached to the COP2 interface 1: A coprocessor is attached to the COP2 interface If the Cop2 interface logic is not implemented, this bit will read 0.
Page 139: 25: Config3 Register (Cp0 Register 16, Select 3)
5.2 CP0 Register Descriptions 5.2.25 Conﬁg3 Register (CP0 Register 16, Select 3) register encodes additional capabilities. All ﬁelds in the register are read-only. Conﬁg3 Conﬁg3 Figure 5-25 shows the format of the register; Table 5.30 describes the register ﬁelds. Conﬁg3 Conﬁg3 Figure 5-25 Conﬁg3 Register Format 31 30...
Page 140 CP0 Registers of the M14K™ Core Table 5.30 Conﬁg3 Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State ISAOnExc Reﬂects the Instruction Set Architecture used when vectoring to Preset, driven an exception. Affects exceptions whose vectors are offsets from by signal EBASE.
Page 141 5.2 CP0 Register Descriptions Table 5.30 Conﬁg3 Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State Denotes the presence of support for large physical addresses on MIPS64 processors. Not used by MIPS32 processors and returns zero on read. Encoding Meaning Large physical address support is not...
Page 142: 26: Config4 Register (Cp0 Register 16, Select 4)
CP0 Registers of the M14K™ Core Table 5.30 Conﬁg3 Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State SmartMIPS™ ASE implemented. This bit indicates whether the SmartMIPS ASE is implemented. Because SmartMIPS isnot present on the M14K core, this bit will always be 0. Encoding Meaning SmartMIPS ASE is not implemented...
Page 143: 28: Config7 Register (Cp0 Register 16, Select 7)
5.2 CP0 Register Descriptions Figure 5-27 shows the format of the register; Table 5.32 describes the register ﬁelds. Conﬁg5 Conﬁg5 Table 5.32 Conﬁg5 Register Field Descriptions Fields Read / Reset Name Bits Description Write State This bit is reserved. With the current architectural deﬁni- tion, this bit should always read as a 0.
Page 144: Figure 5.29 Debug Register Format
CP0 Registers of the M14K™ Core read-only information bits are updated every time the debug exception is taken, or when a normal exception is taken when already in debug mode. Only the bit and the ﬁeld are valid when read from non-debug mode; the values of all other bits and EJTAGver ﬁelds are UNPREDICTABLE.
Page 145 5.2 CP0 Register Descriptions Table 5.34 Debug Register Field Descriptions (Continued) Fields Name Description Read/Write Reset State Bit(s) NoDCR Indicates whether the dseg memory segment is present and the Debug Control Register is accessible: Encoding Meaning dseg is present No dseg present LSNM Controls access of load/store between dseg and main memory:...
Page 146 CP0 Registers of the M14K™ Core Table 5.34 Debug Register Field Descriptions (Continued) Fields Name Description Read/Write Reset State Bit(s) MCheckP Indicates that an imprecise Machine Check exception is pending. All Machine Check exceptions are precise on the M14K processor, so this bit will always read as 0. CacheEP Indicates that an imprecise Cache Error is pending.
Page 147 5.2 CP0 Register Descriptions Table 5.34 Debug Register Field Descriptions (Continued) Fields Name Description Read/Write Reset State Bit(s) DIBImpr Indicates that an Imprecise debug instruction break Undeﬁned exception occurred (due to a complex breakpoint). Cleared on exception in debug mode. DINT Indicates that a debug interrupt exception occurred.
Page 148: 30: Trace Control Register (Cp0 Register 23, Select 1)
CP0 Registers of the M14K™ Core 5.2.30 Trace Control Register (CP0 Register 23, Select 1) register conﬁguration is shown below. TraceControl This register is only implemented if the EJTAG PDtrace capability is present. Figure 5.30 TraceControl Register Format 29 28 26 25 24 23 22 21 20 13 12 TS UT...
Page 149 5.2 CP0 Register Descriptions Table 5.35 TraceControl Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State When set to one, this enables tracing in Kernel Mode. Undeﬁned For trace to be enabled in Kernel mode, the On bit must be one.
Page 150: 31: Trace Control2 Register (Cp0 Register 23, Select 2)
CP0 Registers of the M14K™ Core 5.2.31 Trace Control2 Register (CP0 Register 23, Select 2) register provides additional control and status information. Note that some ﬁelds in the TraceControl2 register are read-only, but have a reset state of “Undeﬁned”. This is because these values are loaded TraceControl2 from the Trace Control Block (TCB) (see ).
Page 151: 32: User Trace Data1 Register (Cp0 Register 23, Select 3)/User Trace Data2 Register (Cp0 Register 24, Select 3)
5.2 CP0 Register Descriptions Table 5.36 TraceControl2 Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State This bit denotes which trace buffer is currently being Undeﬁned written by the trace and is used to select the appropri- ate interpretation of the TraceControl2 ﬁeld.
Page 152: 33: Tracebpc Register (Cp0 Register 23, Select 4)
CP0 Registers of the M14K™ Core Figure 5.32 User Trace Data1/User Trace Data2 Register Format Data Table 5.37 UserTraceData1/UserTraceData2 Register Field Descriptions Fields Read / Name Bits Description Write Reset State Data 31:0 Software readable/writable data. When written, this triggers a user format trace record out of the PDtrace interface that transmits the Data ﬁeld to trace memory.
Page 153: 34: Debug2 Register (Cp0 Register 23, Select 6)
5.2 CP0 Register Descriptions Table 5.38 TraceBPC Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State DBPOn 17:16 Each of the 2 bits corresponds to the 2 possible EJTAG hardware data breakpoints that may be imple- mented. For example, bit 16 corresponds to the ﬁrst data breakpoint.
Page 154: 35: Debug Exception Program Counter Register (Cp0 Register 24, Select 0)
CP0 Registers of the M14K™ Core Table 5.39 Debug2 Register Field Descriptions Fields Name Bits Description Read/Write Reset State 31:4 Reserved Primed - indicates whether a complex breakpoint with Undeﬁned an active priming condition was seen on the last debug exception.
Page 155: 36: Performance Counter Register (Cp0 Register 25, Select 0-3)
5.2 CP0 Register Descriptions Figure 5.35 DEPC Register Format DEPC Table 5.40 DEPC Register Formats Fields Name Bit(s) Description Read/Write Reset DEPC 31:0 DEPC register is updated with the virtual address of Undeﬁned the instruction that caused the debug exception. If the instruction is in the branch delay slot, then the virtual address of the immediately preceding branch or jump instruction is placed in this register.
Page 156: Figure 5.36 Performance Counter Control Register
CP0 Registers of the M14K™ Core Figure 5.36 Performance Counter Control Register 31 30 15 14 11 10 EventExt Event IE U 0 K EXL Table 5.42 Performance Counter Control Register Field Descriptions Fields Name Bits Description Read/Write Reset State If this bit is one, another pair of Performance Control Counter...
Page 157 5.2 CP0 Register Descriptions Table 5.43 Performance Counter Events Sorted by Event Number (Continued) Event Num Counter 0 Mode Counter 1 Mode Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved integer instructions completed Reserved loads completed Stores completed J/JAL completed microMIPS instructions completed no-ops completed...
Page 158: Table 5.44 Performance Counter Event Descriptions Sorted By Event Type
CP0 Registers of the M14K™ Core Table 5.43 Performance Counter Events Sorted by Event Number (Continued) Event Num Counter 0 Mode Counter 1 Mode Other interlock stall cycles Reserved Reserved Reserved Reserved Reserved EJTAG Instruction Triggerpoints EJTAG Data Triggerpoints Reserved Reserved Reserved Reserved...
Page 159: Figure 5.37 Performance Counter Count Register
5.2 CP0 Register Descriptions Table 5.44 Performance Counter Event Descriptions Sorted by Event Type (Continued) Event Event Name Counter Number Description Instruction execution events SC instructions failed SC instruction that did not update memory. Note: While this event and the SC instruction count event can be con- ﬁgured to count in speciﬁc operating modes, the timing of the events is much different, and the observed operating mode could change between them, causing some inaccuracy in the measured ratio.
Page 160: 37: Errctl Register (Cp0 Register 26, Select 0)
CP0 Registers of the M14K™ Core Table 5.45 Performance Counter Count Register Field Descriptions Fields Name Bits Description Read / Write Reset State Counter 31:0 Counter Undeﬁned 5.2.37 ErrCtl Register (CP0 Register 26, Select 0) register controls parity protection of data and instruction SRAM. Parity protection can be enabled or dis- ErrCtl abled using the bit.
Page 161: Table 5.47 Cacheerr Register Field Descriptions (Primary Caches)
5.2 CP0 Register Descriptions Table 5.47 CacheErr Register Field Descriptions (Primary Caches) Fields Name Bits Description Read / Write Reset State Error Reference. Indicates the type of reference that encountered an Undeﬁned error. Encoding Meaning Instruction Data SRAM parity Undeﬁned Error Both.
Page 162: Figure 5.40 Errorepc Register Format
CP0 Registers of the M14K™ Core That is, the upper 31 bits of the GPR are written to the upper 31 bits of the error exception PC, and the lower bit of the error exception PC is cleared. The upper bit of the ﬁeld is cleared and the lower bit is loaded from the lower ISAMode bit of the GPR.
Page 163: Figure 5-42 Kscratchn Register Format
5.2 CP0 Register Descriptions Figure 5-42 KScratchn Register Format Data Table 5.50 KScratchn Register Field Descriptions Fields Read / Reset Name Bits Description Write State Data 31:0 Scratch pad data saved by kernel software. Undeﬁned MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 164 CP0 Registers of the M14K™ Core MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 165 Chapter 6 Hardware and Software Initialization of the M14K™ Core The M14K processor core contains only a minimal amount of hardware initialization and relies on software to fully initialize the device. This chapter contains the following sections: • Section 6.1 “Hardware-Initialized Processor State” •...
Page 166 Hardware and Software Initialization of the M14K™ Core • - cleared to 0 on Reset/SoftReset Debug IBusEP • - cleared to 0 on Reset/SoftReset Debug DBusEP • - cleared to 0 on Reset/SoftReset Debug IEXI • - cleared to 0 on Reset/SoftReset Debug 6.1.2 Bus State Machines All pending bus transactions are aborted and the state machines in the SRAM interface unit are reset when a Reset or...
Page 167 6.2 Software Initialized Processor State • : Desired state of the device should be set. Status • Other COP0 state: Other registers should be written before they are read. Some registers are not explicitly write- able, and are only updated as a by-product of instruction execution or a taken exception. Uninitialized bits should be masked off after reading these registers.
Page 168 Hardware and Software Initialization of the M14K™ Core MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 169 Chapter 7 Power Management of the M14K™ Core The M14K processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halted, reducing system power con- sumption during idle periods.
Page 170 Power Management of the M14K™ Core • signal indicates that the processor has entered debug mode. EJ_DebugM 7.2 Instruction-Controlled Power Management The second mechanism for invoking power down mode is through execution of the WAIT instruction. If the bus is idle at the time the WAIT instruction reaches the M stage of the pipeline the internal clocks are suspended and the pipeline is frozen.
Page 171 Chapter 8 EJTAG Debug Support in the M14K™ Core The EJTAG debug logic in the M14K processor core provides three optional modules: Hardware breakpoints Test Access Port (TAP) for a dedicated connection to a debug host Tracing of program counter/data address/data value trace to On-chip memory or to a Trace probe These features are covered in the following sections: •...
Page 172: Figure 8.1 Dcr Register Format
EJTAG Debug Support in the M14K™ Core bit allows implementation-dependent masking of none, some or all sources for soft reset. The soft reset masking may only be applied to a soft reset source if that source can be efﬁciently masked in the system, thus result- ing in no reset at all.
Page 173 8.1 Debug Control Register Table 8.1 DCR Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State PCIM Conﬁgure PC Sampling to capture all executed addresses or only those that miss the instruction cache This feature is not supported and this bit will read as 0. Encoding Meaning All PCs captured...
Page 174 EJTAG Debug Support in the M14K™ Core Table 8.1 DCR Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State DataBrk Indicates if data hardware breakpoint is implemented: Preset Encoding Meaning No data hardware breakpoint imple- mented Data hardware breakpoint imple- mented InstBrk...
Page 175 8.1 Debug Control Register Table 8.1 DCR Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State Indicates if the PC Sampling feature is implemented. Encoding Meaning No PC Sampling implemented PC Sampling implemented PC Sampling rate. Values 0 to 7 map to values 2 to 2 cycles, respectively.
Page 176 EJTAG Debug Support in the M14K™ Core Table 8.1 DCR Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State ProbEn Probe Enable. This bit reﬂects the ProbEn bit in the Same value EJTAG Control register: ProbEn Encoding Meaning (see Table...
Page 177 8.2 Hardware Breakpoints exception and/or a trigger is generated. An internal bit in the instruction breakpoint registers is set to indicate that the match occurred. 8.2.1 Data Breakpoints Data breakpoints occur on load/store transactions. Breakpoints are set on virtual address values, similar to the Instruc- tion breakpoint.
Page 178 EJTAG Debug Support in the M14K™ Core The breakpoint is not evaluated on instructions from a speculative fetch or execution, nor for addresses which are unaligned with an executed instruction. A breakpoint match depends on the virtual address of the executed instruction (PC) which can be masked at bit level. The registers for each instruction breakpoint have the values and mask used in the compare, and the equation that determines the match is shown below in C-like notation.
Page 179 8.2 Hardware Breakpoints ( IBCnexcl && (IBM[MSB:1] > PC[MSB:1] || PC[MSB:1] > IBA[MSB:1]) Also note that addresses that overlap a boundary is considered for both exclusive and inclusive breakpoint matches. 8.2.3.2 Conditions for Matching Data Breakpoints There are two methods for matching conditions, namely 1) by Equality and Mask or 2) by Address Range: Equality and Mask When a data breakpoint is enabled, that breakpoint is evaluated for every data transaction due to a load/store instruc- tion executed in non-debug mode, including load/store for coprocessor, and transactions causing an address error on...
Page 180 EJTAG Debug Support in the M14K™ Core DBCnIVM ^ (((DATA[7:0] == DBVn ) || ! BYTELANE[0] || DBCn || DBCn ) && DBV[7:0] BLM[0] BAI[0] ((DATA[15:8] == DBVn ) || ! BYTELANE[1] || DBCn || DBCn ) && DBV[15:8] BLM[1] BAI[1] ((DATA[23:16] == DBVn ) || ! BYTELANE[2] || DBCn...
Page 181 8.2 Hardware Breakpoints 8.2.4 Debug Exceptions from Breakpoints Instruction and data breakpoints may be set up to generate a debug exception when the match condition is true, as described below. 8.2.4.1 Debug Exception by Instruction Breakpoint If the breakpoint is enabled by bit in the register, then a debug instruction break exception occurs if the IBCn...
Page 182: Table 8.2 Addresses For Instruction Breakpoint Registers
EJTAG Debug Support in the M14K™ Core • On a store the ] bits are allowed but not required to be set for all matching breakpoints with a data value compare, but either all or none of the ] bits must be set for these breakpoints. •...
Page 183: Figure 8.2 Ibs Register Format
8.2 Hardware Breakpoints 8.2.6.1 Instruction Breakpoint Status (IBS) Register (0x1000) ) register holds implementation and status information about the instruction Instruction Breakpoint Status breakpoints. This register is required only if instruction breakpoints are implemented. Figure 8.2 IBS Register Format 29 28 27 24 23 Res ASIDsup Table 8.3 IBS Register Field Descriptions...
Page 184: Figure 8.4 Ibmn Register Format
EJTAG Debug Support in the M14K™ Core 8.2.6.3 Instruction Breakpoint Address Mask n (IBMn) Register (0x1108 + n*0x100) The Instruction ) register has the mask for the address compare used in the condi- Breakpoint Address Mask n IBMn tion for instruction breakpoint n. A 1 indicates that the corresponding address bit will not be considered in the match. A mask value of all 0’s would require an exact address match, while a mask value of all 1’s would match on any address.
Page 185: Figure 8.6 Ibcn Register Format
8.2 Hardware Breakpoints Figure 8.6 IBCn Register Format ASIDuse hwarts excl hwart Res TE Res BE Table 8.7 IBCn Register Field Descriptions Fields Name Bits Description Read/Write Reset State 31:24 Must be written as zero; returns zero on read. ASIDuse Use ASID value in compare for instruction breakpoint n: Encoding Meaning...
Page 186: Figure 8.7 Ibccn Register Format
EJTAG Debug Support in the M14K™ Core 8.2.6.6 Instruction Breakpoint Complex Control n (IBCCn) Register (0x1120 + n*0x100) The Instruction ) register controls the complex break conditions for instruction Breakpoint Complex Control n IBCCn breakpoint n. This register is required only if complex breakpoints are implemented and only for implemented instruction breakpoints.
Page 187: Figure 8.8 Ibpcn Register Format
8.2 Hardware Breakpoints If complex breakpoints are implemented, there will be an 8b pass counter for each of the instruction breakpoints on the M14K core. Figure 8.8 IBPCn Register Format PassCnt Table 8.9 IBPCn Register Field Descriptions Fields Name Bits Description Read/Write Reset State...
Page 188: Figure 8.9 Dbs Register Format
EJTAG Debug Support in the M14K™ Core An example of some of the registers; is at offset 0x2108 and is at offset 0x2220. DBM0 DBV1 8.2.7.1 Data Breakpoint Status (DBS) Register (0x2000) ) register holds implementation and status information about the data breakpoints. Data Breakpoint Status This register is required only if data breakpoints are implemented.
Page 189: Figure 8.11 Dbmn Register Format
8.2 Hardware Breakpoints 8.2.7.3 Data Breakpoint Address Mask n (DBMn) Register (0x2108 + 0x100 * n) ) register has the mask for the address compare used in the condition for Data Breakpoint Address Mask n DBMn data breakpoint n. A 1 indicates that the corresponding address bit will not be considered in the match. A mask value of all 0’s would require an exact address match, while a mask value of all 1’s would match on any address.
Page 190: Table 8.15 Dbcn Register Field Descriptions
EJTAG Debug Support in the M14K™ Core Table 8.15 DBCn Register Field Descriptions Fields Name Bits Description Read/Write Reset State 31:24 Must be written as zero; returns zero on reads. ASIDuse Use ASID value in compare for data breakpoint n: Encoding Meaning Don’t use ASID value in compare...
Page 191: Figure 8.14 Dbvn Register Format
8.2 Hardware Breakpoints Table 8.15 DBCn Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State hwart A value of 0 indicates that the breakpoint will match using the “Equality and Mask” equation as found sec- tion under 8.2.3.2 “Conditions for Matching Data Breakpoints”.
Page 192: Figure 8.15 Dbccn Register Format
EJTAG Debug Support in the M14K™ Core 8.2.7.7 Data Breakpoint Complex Control n (DBCCn) Register (0x2128 + n*0x100) The Data Breakpoint Complex Control n ( ) register controls the complex break conditions for data breakpoint DBCCn n. This register is required only if complex breakpoints are implemented and only for implemented data breakpoints. Figure 8.15 DBCCn Register Format 4 3 2 1 0 TIBrkNum...
Page 193: Figure 8.16 Dbpcn Register Format
8.2 Hardware Breakpoints 8.2.7.8 Data Breakpoint Pass Counter n (DBPCn) Register (0x2130 + n*0x100) ) register controls the pass counter associated with data breakpoint n. Data Breakpoint Pass Counter n DBPCn This register is required only if complex breakpoints are implemented and only for implemented data breakpoints. If complex breakpoints are implemented, there will be an 16b pass counter for each of the data breakpoints on the M14K core.
Page 194: Figure 8.18 Cbtc Register Format
EJTAG Debug Support in the M14K™ Core 8.2.8 Complex Breakpoint Registers The registers for complex breakpoints are described Table 8.20. These registers have implementation information and are used to setup the data breakpoints. All registers are in drseg. Table 8.20 Addresses for Complex Breakpoint Registers Register Offset in drseg Mnemonic...
Page 195: Figure 8.19 Prcnda Register Format
8.2 Hardware Breakpoints Table 8.21 CBTC Register Field Descriptions (Continued) Fields Name Bits Description Read/Write Reset State Stopwatch Timer Present - indicates whether stopwatch timer is implemented. Priming Present - indicates whether primed breakpoints are supported Data Qualify Present - indicates whether data qualiﬁed breakpoints are supported.
Page 196: Table 8.23: Priming Conditions And Register Values For 6I/2D Configuration
EJTAG Debug Support in the M14K™ Core Table 8.22 PrCndA Register Field Descriptions Fields Read/Wr Name Bit(s) Description Reset State CondN 31:24 Speciﬁes which triggerpoint is connected to priming Preset 23:16 condition 3, 2, 1, or 0 for the current breakpoint. 15:8 31:30 Reserved...
Page 197: Figure 8.20 Stctl Register Format
8.2 Hardware Breakpoints drseg Break Cond0 Cond1 Cond2 Cond3 PrCndA Value offset Inst5 Bypass Data2 Inst4 Inst6 0x1614_2200 0x83a0 Inst6 Bypass Data3 Inst7 Inst0 0x1017_2300 0x83c0 Inst7 Bypass Data3 Inst6 Inst0 0x1016_2300 0x83e0 Data0 Bypass Inst0 Inst1 Data1 0x2111_1000 0x84e0 Data1 Bypass Inst2...
Page 198: Figure 8.21 Stcnt Register Format
EJTAG Debug Support in the M14K™ Core Table 8.25 STCtl Register Field Descriptions Fields Read/Wr Name Bit(s) Description Reset State StartChan0 Indicates the instruction breakpoint channel that will start the counter if the timer is under pair0 breakpoint control. Enables the ﬁrst pair (pair0) of breakpoint registers to control the timer when under breakpoint control.
Page 199 8.3 Complex Breakpoint Usage Read the bit to check for the presence of any complex break and trigger features DCRCBT Read the register to check for the presence of each individual feature. If the M14K core implements CBTControl any complex break and trigger features, it will implement all of them If Pass Counters are implemented, they may not be implemented for all break channels and may have different counter sizes.
Page 200 EJTAG Debug Support in the M14K™ Core • Controlled by writing to the per-breakpoint pass counter register • Resets to 0 • Writing to a non-zero value enables the pass counter. When enabled, each time the breakpoint conditions match, the counter will be decremented by 1. After the counter value reaches 0, the breakpoint action (breakpoint excep- tion, trigger, or complex break enable) will occur on any subsequent matches and the counter will not decrement further.
Page 201 8.3 Complex Breakpoint Usage • When the priming condition has been seen, the primed breakpoint will remain primed until its register is xBCCn written • The primed state is stored with the breakpoint being primed and not with the breakpoint that is doing the priming. •...
Page 202: Table 8.27 Ejtag Interface Pins
EJTAG Debug Support in the M14K™ Core • Bit in register controls whether the counter is free-running or breakpoint controlled. CBTControl • Counter does not count in debug mode • When breakpoint controlled, the involved instruction breakpoints must have set in order to IBCn IBCCn start or stop the timer.
Page 203 8.4 Test Access Port (TAP) Table 8.27 EJTAG Interface Pins (Continued) Type Description TRST_N Test Reset Input (Optional pin) TRST_N pin is an active-low signal for asynchronous reset of the TAP controller and instruction in the TAP module, independent of the processor logic.
Page 204: Figure 8.22 Tap Controller State Diagram
EJTAG Debug Support in the M14K™ Core Figure 8.22 TAP Controller State Diagram Test-Logic-Reset Run-Test/Idle Select_DR_Scan Select_IR_Scan Capture_DR Capture_IR Shift_DR Shift_IR Exit1_DR Exit1_IR Pause_DR Pause_IR Exit2_DR Exit2_IR Update_DR Update_IR 8.4.2.1 Test-Logic-Reset State In the Test-Logic-Reset state the boundary scan test logic is disabled. The test logic enters the Test-Logic-Reset state when the input is held HIGH for at least ﬁve rising edges of .
Page 205 8.4 Test Access Port (TAP) HIGH on causes the controller to transition to the Test-Reset-Logic state. The instruction cannot change while the TAP controller is in this state. 8.4.2.5 Capture_DR State In this state the boundary scan register captures the value of the register addressed by the Instruction register, and the value is then shifted out in the Shift_DR.
Page 206 EJTAG Debug Support in the M14K™ Core 8.4.2.11 Capture_IR State In this state the shift register contained in the Instruction register loads a ﬁxed pattern (00001 ) on the rising edge of . The data registers selected by the current instruction retain their previous state. is sampled LOW at the rising edge of , the controller transitions to the Shift_IR state.
Page 207: Table 8.28 Implemented Ejtag Instructions
8.4 Test Access Port (TAP) The Instruction register is a 5-bit register. In the current EJTAG implementation only some instructions have been decoded; the unused instructions default to the BYPASS instruction. Table 8.28 Implemented EJTAG Instructions Value Instruction Function 0x01 IDCODE Select Chip Identiﬁcation data register 0x03...
Page 208: Figure 8.23 Concatenation Of The Ejtag Address, Data And Control Registers
EJTAG Debug Support in the M14K™ Core 8.4.3.5 DATA Instruction This instruction is used to select the Data register to be connected between . The EJTAG Probe shifts 32 bits of data into the Data register and shifts out the captured data via the pin.
Page 209: Figure 8.24 Tdi To Tdo Path When In Shift-Dr State And Fastdata Instruction Is Selected
8.5 EJTAG TAP Registers 8.4.3.10 FASTDATA Instruction This selects the Data and the Fastdata registers at once, as shown in Figure 8.24. Figure 8.24 TDI to TDO Path When in Shift-DR State and FASTDATA Instruction is Selected Data Fastdata 8.4.3.11 PCsample Register (PCSAMPLE Instruction) This selects the PCsample Register.
Page 210: Figure 8.25: Device Identification Register Format
EJTAG Debug Support in the M14K™ Core occurs on the falling edge of . In the Test-Logic-Reset and Capture-IR state, the instruction shift register is set to 00001 , as for the IDCODE instruction. This forces the device into the functional mode and selects the Device ID register.
Page 211: Figure 8.26 Implementation Register Format
8.5 EJTAG TAP Registers Table 8.29 Device Identiﬁcation Register Fields Read/ Name Bit(s) Description Write Reset State Version 31:28 Version (4 bits) EJ_Version[3:0] This ﬁeld identiﬁes the version number of the proces- sor derivative. PartNumber 27:12 Part Number (16 bits) EJ_PartNumber[15:0] This ﬁeld identiﬁes the part number of the processor derivative.
Page 212: Figure 8.27 Ejtag Control Register Format
EJTAG Debug Support in the M14K™ Core Table 8.30 Implementation Register Descriptions Fields Read/Wr Name Bit(s) Description Reset State ASIDsize 23:21 Size of ASID ﬁeld in implementation: Encoding Meaning No ASID in implementation 6-bit ASID 8-bit ASID Reserved Reserved 20:17 Reserved MIPS16 Indicates whether MIPS16 is implemented:...
Page 213: Table 8.31 Ejtag Control Register Descriptions
8.5 EJTAG TAP Registers Table 8.31 EJTAG Control Register Descriptions Fields Read/ Name Bit(s) Description Write Reset State Rocc Reset Occurred The bit indicates if a CPU reset has occurred: Encoding Meaning No reset occurred since bit last cleared. Reset occurred since bit last cleared. Rocc bit will keep the 1 value as long as reset is applied.
Page 214 EJTAG Debug Support in the M14K™ Core Table 8.31 EJTAG Control Register Descriptions (Continued) Fields Read/ Name Bit(s) Description Write Reset State Doze Doze state The Doze bit indicates any kind of low-power mode. The value is sampled in the Capture-DR state of the TAP con- troller: Encoding Meaning...
Page 215 8.5 EJTAG TAP Registers Table 8.31 EJTAG Control Register Descriptions (Continued) Fields Read/ Name Bit(s) Description Write Reset State PrAcc Processor Access (PA) R/W0 Read value of this bit indicates if a Processor Access (PA) to the EJTAG memory is pending: Encoding Meaning No pending processor access...
Page 216 EJTAG Debug Support in the M14K™ Core Table 8.31 EJTAG Control Register Descriptions (Continued) Fields Read/ Name Bit(s) Description Write Reset State ProbEn Probe Enable 0 or 1 This bit indicates to the CPU if the EJTAG memory is from handled by the probe so processor accesses are answered: EJTAGBOOT Encoding...
Page 217 8.5 EJTAG TAP Registers Table 8.31 EJTAG Control Register Descriptions (Continued) Fields Read/ Name Bit(s) Description Write Reset State ProbTrap Probe Trap 0 or 1 This bit controls the location of the debug exception vec- from tor: EJTAGBOOT Encoding Meaning In normal memory 0xBFC0.0480 In EJTAG memory at 0xFF20.0200 in dmseg...
Page 218 EJTAG Debug Support in the M14K™ Core Table 8.31 EJTAG Control Register Descriptions (Continued) Fields Read/ Name Bit(s) Description Write Reset State Debug Mode This bit indicates the debug or non-debug mode: Encoding Meaning Processor is in non-debug mode Processor is in debug mode The bit is sampled in the Capture-DR state of the TAP controller.
Page 219: Figure 8.28 Endian Formats For The Pad Register
8.5 EJTAG TAP Registers Figure 8.28 Endian Formats for the PAD Register A[n:0]=4 A[n:2]=1 BIG-ENDIAN A[n:0]=0 A[n:2]=0 Most significant byte is at lowest address. Word is addressed by byte address of most significant byte. A[n:0]=7 A[n:2]=1 LITTLE-ENDIAN A[n:0]=3 A[n:2]=0 Least significant byte is at lowest address. Word is addressed by byte address of least significant byte.
Page 220: Table 8.33 Operation Of The Fastdata Access
EJTAG Debug Support in the M14K™ Core The FASTDATA access is used for efﬁcient block transfers between dmseg (on the probe) and target memory (on the processor). An “upload” is deﬁned as a sequence of processor loads from target memory and stores to dmseg. A “download”...
Page 221 8.6 TAP Processor Accesses in a serial way through the EJTAG interface: the core can thus execute instructions e.g. debug monitor code, without occupying the memory. Accessing the dmseg segment (EJTAG memory) can only occur when the processor accesses an address in the range from 0xFF20.0000 to 0xFF2F.FFFF, the bit is set, and the processor is in debug mode (DM=1).
Page 222 EJTAG Debug Support in the M14K™ Core The internal hardware sets the following bits in the register: EJTAG Control = 1 (selects Processor Access operation) PrAcc = 1 (selects processor write operation) PRnW [1:0] = value depending on the transfer size The EJTAG Probe selects the register, shifts out this control register’s data and tests the EJTAG Control...
Page 223: Table 8.34 Ej_Disableprobedebug Signal Overview
8.8 iFlowtrace™ Mechanism Suggested implementation of the signal is for a microcontroller to provide a bit within EJ_DisableProbeDebug non-volatile memory (outside the core) that is pre-programmed to set or clear this control signal. Table 8.34 EJ_DisableProbeDebug Signal Overview Signal Description Direction Compliance EJ_DisableProbeDebug...
Page 224 EJTAG Debug Support in the M14K™ Core The iFlowtrace tracing scheme is not a strict subset of the PDtrace tracing methodology, and its trace format outputs differ from those of PDtrace. Trace formats, using simpliﬁed instruction state descriptors, were designed for the iFlowtrace trace to simplify the trace mechanism and to obtain better compression.
Page 225 8.8 iFlowtrace™ Mechanism • 11 01 - followed by 16 bits of 1-bit shifted offset from the last PC. The bit assignments of this format on the bus between the core tracing logic and the ITCB is: [3:0] = 4’b1011 [19:4] = PCdelta[16:1] •...
Page 226 EJTAG Debug Support in the M14K™ Core The breakpoints used in this mode must have the TE bet set to enable the match condition. Software should avoid setting up overlapping breakpoints. The behavior when multiple matches occur on the same instruction is to report a BreakpointID of 7.
Page 227 8.8 iFlowtrace™ Mechanism • Exception returns: ERET • MCU ASE Interrupt returns: IRET Other Trace Messages In any of the special trace modes, it is possible to embed messages into the trace stream directly from a program. This is done by writing to the Cop0 registers.
Page 228: Figure 8.30 Trace Logic Overview
EJTAG Debug Support in the M14K™ Core • 1110 - Function Call/Return/Exception Tracing. The output format during this trace mode is: [3:0] = 4’b0111 [4] = FC [5] = Ex [6] = R [37:8] = PC[31:1] [38] = NCC [48:39] = Delta Cycle (if enabled) Note that for a MIPS32 or MIPS64 instruction, NCC=1, and for microMIPS instruction NCC=0.
Page 229: Table 8.35 Data Bus Encoding
8.8 iFlowtrace™ Mechanism therefore the 57 data signals carry valid execution information. The iFlowtrace data bus is encoded as shown in Table 8.35. Note that all the non-deﬁned upper bits of the bus are zeroes. Table 8.35 Data Bus Encoding Valid Data (LSBs) Description...
Page 230: Figure 8.31 Control/Status Register
EJTAG Debug Support in the M14K™ Core Table 8.36 Tag Bit Encoding Starting Bit of First Full Encoding Trace Message (decimal) Unused 0,16,32,48 Reserved 62,63 Others StartingBit When trace stops (ON set to zero), any partially ﬁlled trace words are written to memory. Any unused space above the ﬁnal message is ﬁlled with 1’s.
Page 231: Table 8.37 Control/Status Register Field Descriptions
8.8 iFlowtrace™ Mechanism Table 8.37 Control/Status Register Field Descriptions Fields Read / Reset Name Bits Description Write State Compliance 30:16 Reserved for future use. Read as zeros, must be written as Required zeros Illegal This bit is set by hardware and indicates if the currently Required enabled trace output modes are an illegal combination.
Page 232: Figure 8.32 Itcbtw Register Format
EJTAG Debug Support in the M14K™ Core Table 8.37 Control/Status Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State Compliance OfClk Controls the Off-chip clock ratio. When the bit is set, this Required implies 1:2, that is, the trace clock is running at 1/2 the core clock, and when the bit is clear, implies 1:4 ratio, that is, the trace clock is at 1/4 the core clock.
Page 233: Figure 8.33 Itcbrdp Register Format
8.8 iFlowtrace™ Mechanism 8.8.6.3 ITCBRDP Register (Offset 0x3f88) register is the address pointer to on-chip trace memory. It points to the TW read when reading the ITCBRDP ITCBTW register. This value will be automatically incremented after a read of the register.
Page 234: Table 8.41 Drseg Registers That Enable/Disable Trace From Breakpoint-Based Triggers
EJTAG Debug Support in the M14K™ Core 8.8.7 ITCB iFlowtrace Off-Chip Interface The off-chip interface consists of a 4-bit data port ( ) and a trace clock ( can be a DDR TR_DATA TR_CLK TR_CLK clock; that is, both edges are signiﬁcant. follow the same timing and have the same output TR_DATA TR_CLK...
Page 235: Figure 8.35 Pcsample Tap Register Format (Mips32)
8.9 PC/Data Address Sampling • Bits 14:0 (IBrk/DBrk): Used to explicitly specify which instruction (data or tuple) breaks enable or disable iFlowtrace. A value of 0 implies that trace is turned off (unconditional trace stop) and a value of 1 speciﬁes that the trigger enables trace (unconditional trace start).
Page 236 EJTAG Debug Support in the M14K™ Core 8.9.1 PC Sampling in Wait State Note that the processor samples PC even when it is asleep, that is, in a WAIT state. This permits an analysis of the amount of time spent by a processor in WAIT state which may be used for example to revert to a low power mode during the non-execution phase of a real-time application.
Page 237 8.10 Fast Debug Channel 8.10.1 Common Device Memory Map Software on the core accesses FDC through memory-mapped registers, located within the Common Device Memory Map (CDMM). The CDMM is a region of physical address space that is reserved for mapping IO device conﬁgura- tion registers within a MIPS processor.
Page 238: Figure 8.36 Fast Debug Channel Buffer Organization
EJTAG Debug Support in the M14K™ Core Figure 8.36 Fast Debug Channel Buffer Organization FDSTAT FDRX FDTXn Load from Load from Store Address Store Data to Addr Decode TxFIFO RxFIFO Chan Data Chan Data Data Data Chan Chan SI_ClkIn EJ_TCK Data Data Chan...
Page 239: Figure 8.37 Fdc Tap Register Format
8.10 Fast Debug Channel condition is met, there will be 0 or 1 valid entries. However, the interrupt will not be asserted when there is only one valid entry if it is an entry SI_ClkIn • The RxFIFO has similar characteristics, but these are even less visible to software since must be run- SI_ClkIn ning to access the FDC registers.
Page 240: Figure 8.38 Fdc Access Control And Status Register
EJTAG Debug Support in the M14K™ Core Table 8.42 FDC TAP Register Field Descriptions Fields Read / Reset Name Bits Description Write State Data 31:0 Data value being scanned in or out Undeﬁned 8.10.6 Fast Debug Channel Registers This section describes the Fast Debug Channel registers. CPU access to FDC is via loads and stores to the FDC device in the Common Device Memory Map (CDMM) region.
Page 241: Figure 8.39: Fdc Configuration Register
8.10 Fast Debug Channel Table 8.44 FDC Access Control and Status Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State This bit indicates if user-mode write access to this device is enabled. A value of 1 indicates that access is enabled. A value of 0 indicates that access is disabled.
Page 242: Figure 8.40 Fdc Status Register
EJTAG Debug Support in the M14K™ Core Table 8.45 FDC Conﬁguration Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State TxIntThresh 19:18 Controls whether transmit interrupts are enabled and the state of the TxFIFO needed to generate an interrupt. Encoding Meaning Transmit Interrupt Disabled...
Page 243: Figure 8.41 Fdc Receive Register
8.10 Fast Debug Channel Table 8.46 FDC Status Register Field Descriptions (Continued) Fields Read / Reset Name Bits Description Write State If RxE is set, the receive FIFO is empty. If RxE is not set, the FIFO is not empty. If RxF is set, the receive FIFO is full.
Page 244: Figure 8.43: Cjtag Interface
EJTAG Debug Support in the M14K™ Core Table 8.48 FDC Transmit Register Field Descriptions Fields Read / Reset Name Bits Description Write State TxData 31:0 This register holds the bottom entry in the transmit FIFO W, Unde- Undeﬁned ﬁned value on read Table 8.49 FDTXn Address Decode Address...
Page 245 8.11 cJTAG Interface MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 246 Chapter 9 Instruction Set Overview This chapter provides a general overview on the three CPU instruction set formats of the MIPS architecture: Immedi- ate, Jump, and Register. Refer to Chapter 10, “M14K™ Processor Core Instructions” on page 236 for a complete list- ing and description of instructions.
Page 248: Table 9.1 Byte Access Within A Word
Instruction Set Overview The access type, together with the three low-order bits of the address, deﬁne the bytes accessed within the addressed word as shown in Table 9.1. Only the combinations shown in Table 9.1 are permissible; other combinations cause address error exceptions.
Page 249 9.4 Jump and Branch Instructions 9.3.1 Cycle Timing for Multiply and Divide Instructions Any multiply instruction in the integer pipeline is transferred to the multiplier as remaining instructions continue through the pipeline; the product of the multiply instruction is saved in the HI and LO registers. If the multiply instruction is followed by an MFHI or MFLO before the product is available, the pipeline interlocks until this product does become available.
Page 250 Instruction Set Overview • CLOCount Leading Ones • CLZCount Leading Zeros • MADDMultiply and Add Word • MADDUMultiply and Add Unsigned Word • MSUBMultiply and Subtract Word • MSUBUMultiply and Subtract Unsigned Word • MULMultiply Word to Register • SSNOPSuperscalar Inhibit NOP 9.7.1 CLO - Count Leading Ones The CLO instruction counts the number of leading ones in a word.
Page 251 No arithmetic exception occurs under any circumstances. 9.7.8 SSNOP- Superscalar Inhibit NOP The MIPS32 M14K processor cores treat this instruction as a regular NOP. 9.8 MCU ASE Instructions The MCU ASE includes some new instructions which are particularly useful in microcontroller applications.
Page 252 This chapter supplements the MIPS32® Architecture Reference Manual, Volume II by describing instruction behav- ior that is speciﬁc to a MIPS32 M14K processor core. For complete descriptions of all MIPS32 and mciroMIPS32 instructions, refer to MIPS® Architecture For Programmers, Volume II: The MIPS32® Instruction Set and MIPS®...
Page 253: Table 10.1 Encoding Of The Opcode Field
10.2 M14K™ Core Opcode Map Table 10.1 Encoding of the Opcode Field opcode bits 28..26 bits 31..29 Special RegImm BLEZ BGTZ ADDI ADDIU SLTI SLTIU ANDI XORI β β COP0 COP2 BEQL BNEL BLEZL BGTZL α α α α ϑΑΛΞ α...
Page 254: Table 10.4 Special3 Opcode Encoding Of Function Field
M14K™ Processor Core Instructions Table 10.4 Special3 Opcode Encoding of Function Field function bits 2..0 bits 5..3 α α α α α α α α α α α α α α α α α α α α α α α α...
Page 255: Table 10.8 Cop0 Encoding Of Rs Field
10.3 MIPS32® Instruction Set for the M14K™ Core Table 10.8 COP0 Encoding of rs Field bits 23..21 bits 25..24 α α α α α α MFC0 MTC0 α α Ρ∆ΠΓΠΡ ΜΦΜΧ0 α α ΩΡΠΓΠΡ α Table 10.9 COP0 Encoding of Function Field When rs=CO function bits 2..0 bits 5..3...
Page 256 M14K™ Processor Core Instructions Table 10.10 Instruction Set (Continued) Instruction Description Function Branch and Link GPR[31] = PC + 8 (Assembler idiom for: BGEZAL r0, offset) PC += (int)offset BC2F Branch On COP2 Condition False if COP2Condition(cc) == 0 PC += (int)offset BC2FL Branch On COP2 Condition False Likely if COP2Condition(cc) == 0...
Page 257 10.3 MIPS32® Instruction Set for the M14K™ Core Table 10.10 Instruction Set (Continued) Instruction Description Function BLTZ Branch on Less Than Zero if Rs[31] PC += (int)offset BLTZAL Branch on Less Than Zero And Link GPR[31] = PC + 8 if Rs[31] PC += (int)offset BLTZALL...
Page 258 M14K™ Processor Core Instructions Table 10.10 Instruction Set (Continued) Instruction Description Function ERET Return from Exception if SR[2] PC = ErrorEPC else PC = EPC SR[1] = 0 SR[2] = 0 LL = 0 Extract Bit Field Rt=ExtractField(Rs,msbd,lsb) Insert Bit Field Rt=InsertField(Rt,Rs,msb,lsb) IRET Return from Exception...
Page 259 10.3 MIPS32® Instruction Set for the M14K™ Core Table 10.10 Instruction Set (Continued) Instruction Description Function ≠ MOVN Move Conditional on Not Zero if GPR[rt] 0 then GPR[rd] GPR[rs] MOVZ Move Conditional on Zero if GPR[rt] = 0 then GPR[rd] GPR[rs] MSUB Multiply-Subtract...
Page 260 M14K™ Processor Core Instructions Table 10.10 Instruction Set (Continued) Instruction Description Function SLTI Set on Less Than Immediate if (int)Rs < (int)Immed Rt = 1 else Rt = 0 SLTIU Set on Less Than Immediate Unsigned if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0...
Page 261 10.3 MIPS32® Instruction Set for the M14K™ Core Table 10.10 Instruction Set (Continued) Instruction Description Function TLTIU Trap if Less Than Immediate Unsigned if (uns)Rs < (uns)Immed TrapException TLTU Trap if Less Than Unsigned if (uns)Rs < (uns)Rt TrapException Trap if Not Equal if Rs != Rt TrapException TNEI...
Page 262 Atomically Clear Bit within Byte ACLR 21 20 16 15 14 12 11 REGIMM ATOMIC base offset 000001 00111 Format: MIPS32 and MCU ASE ACLR bit, offset(base) Purpose: Atomically Clear Bit within Byte Disable interrupts; temp ← memory[GPR[base] + offset]; temp ← (temp and ~(1 Description: <<...
Page 263 Atomically Clear Bit within Byte ACLR 24 23 21 20 16 15 12 11 ACLR POOL32B base offset 1011 001000 Format: microMIPS and MCU ASE ACLR bit, offset(base) Purpose: Atomically Clear Bit within Byte Disable interrupts; temp ← memory[GPR[base] + offset]; temp ← (temp and ~(1 Description: <<...
Page 264 Atomically Set Bit within Byte ASET 21 20 16 15 14 12 11 REGIMM ATOMIC base offset 000001 00111 Format: MIPS32 and MCU ASE ASET bit, offset(base) Purpose: Atomically Set Bit within Byte Disable interrupts;temp ← memory[GPR[base] + offset]; temp ← (temp or (1 << Description: bit)) ;...
Page 265 Atomically Set Bit within Byte 24 23 21 20 16 15 12 11 ASET POOL32B base offset 0011 001000 Format: microMIPS AND MCU ASE ASET bit, offset(base) Purpose: Atomically Set Bit within Byte Disable interrupts;temp ← memory[GPR[base] + offset]; temp ← (temp or (1 << Description: bit)) ;...
Page 266 Interrupt Return with Automated Interrupt Epilogue IRET COP0 IRET 010000 00 0000 0000 0000 0000 111000 Format: MIPS32 and MCU ASE IRET Purpose: Interrupt Return with Automated Interrupt Epilogue Optionally jump directly to another interrupt vector without returning to original return address. Description: IRET is used to automate some of the operations that are required when returning from an interrupt handler.
Page 267 Interrupt Return with Automated Interrupt Epilogue I RET Restrictions: The operation of the processor is UNDEFINED if an IRET is executed in the delay slot of a branch or jump instruc- tion. The operation of the processor is UNDEFINED if an IRET is executed when either Shadow Register Sets are not enabled or when EIC interrupt mode is not enabled.
Page 268 Interrupt Return with Automated Interrupt Epilogue IRET endif if IsMicroMIPSImplemented() then PC ← temp || 0 31..1 ISAMode ← temp else PC ← temp endif LLbit ← 0 ← 0 Cause ClearHazards() else Signal_EIC_for_Next_Interrupt() (wait for EIC outputs to update) ←...
Page 269 Interrupt Return with Automated Interrupt Epilogue I RET else if ( Config3 = 1 and EIC_Option=1) VEIC VectorNum = Cause RIPL elseif (Config3 = 1 and EIC_Option=2) VEIC VectorNum = EIC_VectorNum elseif (Config3 = 0 ) VEIC VectorNum = VIntPriorityEncoder() endif if (Config3 = 1 and EIC_Option=3)
Page 270 Interrupt Return with Automated Interrupt Epilogue IRET POOL32A POOL32AXf 000 0000 0011 0100 1101 000000 111100 Format: microMIPS and MCU ASE IRET Purpose: Interrupt Return with Automated Interrupt Epilogue Optionally jump directly to another interrupt vector without returning to original return address. Description: IRET automates some of the operations that are required when returning from an interrupt handler and can be used in place of the ERET instruction at the end of interrupt handlers.
Page 271 Interrupt Return with Automated Interrupt Epilogue I RET Restrictions: The operation of the processor is UNDEFINED if IRET is executed in the delay slot of a branch or jump instruction. The operation of the processor is UNDEFINED if IRET is executed when either Shadow Register Sets are not enabled, or the EIC interrupt mode is not enabled.
Page 272 Interrupt Return with Automated Interrupt Epilogue IRET PC ← temp || 0 31..1 ISAMode ← temp else PC ← temp endif LLbit ← 0 ← 0 Cause ClearHazards() else Signal_EIC_for_Next_Interrupt() (wait for EIC outputs to update) ← EIC Cause RIPL RIPL ←...
Page 273 Interrupt Return with Automated Interrupt Epilogue I RET VectorNum = Cause RIPL elseif (Config3 = 1 and EIC_Option=2) VEIC VectorNum = EIC_VectorNum elseif (Config3 = 0 ) VEIC VectorNum = VIntPriorityEncoder() endif if (Config3 = 1 and EIC_Option=3) VEIC vectorOffset = EIC_VectorOffset else || 0 vectorOffset = 0x200 + (VectorNum x (IntCtl...
Page 274 Load Linked Word 21 20 16 15 base offset 110000 Format: MIPS32 LL rt, offset(base) Purpose: Load Linked Word To load a word from memory for an atomic read-modify-write GPR[rt] ← memory[GPR[base] + offset] Description: The LL and SC instructions provide the primitives to implement atomic read-modify-write (RMW) operations for synchronizable memory locations.
Page 275 Prefetch P REF 26 25 21 20 16 15 PREF base hint offset 110011 Format: PREF hint,offset(base) MIPS32 Purpose: Prefetch To move data between memory and cache. Description: prefetch_memory(GPR[base] + offset) PREF adds the 16-bit signed offset to the contents of GPR base to form an effective byte address. The hint ﬁeld sup- plies information about the way that the data is expected to be used.
Page 276 Prefetch PREF Restrictions: Value Name Data Use and Desired Prefetch Action load Use: Prefetched data is expected to be read (not modiﬁed). Action: Fetch data as if for a load. store Use: Prefetched data is expected to be stored or modiﬁed. Action: Fetch data as if for a store.
Page 277 Prefetch P REF high-reliability requirements. Prefetch operations have no effect on cache lines that were previously locked with the CACHE instruction. MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 278 Store Conditional Word 21 20 16 15 base offset 111000 Format: MIPS32 SC rt, offset(base) Purpose: Store Conditional Word To store a word to memory to complete an atomic read-modify-write if atomic_update then memory[GPR[base] + offset] ← GPR[rt], GPR[rt] ← 1 Description: else GPR[rt] ←...
Page 279 Store Conditional Word Operation: vAddr ← sign_extend(offset) + GPR[base] ≠ 0 if vAddr then 1..0 SignalException(AddressError) endif (pAddr, CCA) ← AddressTranslation (vAddr, DATA, STORE) dataword ← GPR[rt] if LLbit then StoreMemory (CCA, WORD, dataword, pAddr, vAddr, DATA) endif GPR[rt] ← 0 || LLbit Exceptions: TLB Reﬁll, TLB Invalid, TLB Modiﬁed, Address Error, Watch...
Page 280 Store Conditional Word MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 281 Synchronize Shared Memory SYNC 21 20 16 15 11 10 SPECIAL SYNC stype 000000 00 0000 0000 0000 0 001111 Format: MIPS32 SYNC (stype = 0 implied) Purpose: Synchronize Shared Memory To order loads and stores. Description: Simple Description: • SYNC affects only uncached and cached coherent loads and stores.
Page 282 Enter Standby Mode WAIT COP0 WAIT Implementation-Dependent Code 010000 100000 Format: MIPS32 WAIT Purpose: Enter Standby Mode Wait for Event Description: The WAIT instruction forces the core into low power mode. The pipeline is stalled and when all external requests are completed, the processor’s main clock is stopped.
Page 283 Chapter 11 microMIPS™ Instruction Set Architecture The microMIPS™ architecture minimizes the code footprint of applications, thus reducing the cost of memory, which is particularly high for embedded memory. At the same time, the high performance of MIPS cores is maintained. Using this technology, the customer can generate best results without spending time to proﬁle its application.
Page 284 microMIPS™ Instruction Set Architecture 11.1.2 Default ISA Mode The instruction sets available in an implementation are reported in the register ﬁeld (bits 15:14). Conﬁg3 (bit 2) is not used for microMIPS. Conﬁg1 For implementations that support both microMIPS and MIPS32, the selected ISA mode following reset is determined by the setting of the register ﬁeld, which is a read-only ﬁeld set by a hardware signal external to the pro- Conﬁg3...
Page 285 11.2 Instruction Formats • The JR and JALR instructions interpret bit 0 of the source registers as the target ISA mode (0=MIPS32, 1=micro- MIPS) and therefore set the ISA Mode bit according to the contents of bit 0 of the source register. For the actual jump operation, the PC is loaded with the value of the source register with bit 0 set to 0.
Page 286: Figure 11.1 16-Bit Instruction Formats
microMIPS™ Instruction Set Architecture The name ‘immediate ﬁeld’ as used here includes the address offset ﬁeld for branches and load/store instructions as well as the jump target ﬁeld. Other instruction-speciﬁc ﬁelds are typically located between the immediate and minor opcode ﬁelds. Instructions that have multiple “other”...
Page 287: Figure 11.2 32-Bit Instruction Formats
11.2 Instruction Formats Figure 11.2 32-Bit Instruction Formats 26 25 Major Opcode Immediate/Minor Opcode/Other 26 25 21 20 16 15 Major Opcode Imm/Other rs/fs/base Immediate/Minor Opcode/Other 26 25 21 20 16 15 Major Opcode rt/ft/index rs/fs/base Immediate/Minor Opcode/Other 26 25 21 20 16 15 11 10...
Page 288 microMIPS™ Instruction Set Architecture The instruction size can be completely derived from the major opcode. For 32-bit instructions, the major opcode also deﬁnes the position of the minor opcode ﬁeld and whether or not the immediate ﬁeld is right-aligned. Instructions formats are named according to the number of the register ﬁelds and the size of the immediate ﬁeld. The names have the structure R<x>I<y>.
Page 289 11.3 microMIPS Re-encoded Instructions To differentiate between 16-bit and 32-bit encoded instructions, the instruction mnemonic can be optionally extended with the sufﬁx “16” or “32” respectively. This sufﬁx is placed at the end of the instruction before the ﬁrst ‘.’ if there is one.
Page 290: Table 11.1 16-Bit Re-Encoding Of Frequent Mips32 Instructions
microMIPS™ Instruction Set Architecture The compact instruction JRC is to be used instead of JR, when the jump delay slot after JR cannot be ﬁlled. This saves code size. Because JRC may execute as fast as JR with a NOP in the delay slot, JR is preferred if the delay slot can be ﬁlled.
Page 291: Table 11.2 16-Bit Re-Encoding Of Frequent Mips32 Instruction Sequences
11.3 microMIPS Re-encoded Instructions Table 11.1 16-Bit Re-encoding of Frequent MIPS32 Instructions (Continued) Register Total Major Number of Immediate Field Size of Empty 0 Minor Opcode Register Field Size Width Other Field Size Opcode Instruction Name Fields (bit) (bit) Fields (bit) Size (bit) Comment...
Page 292 microMIPS™ Instruction Set Architecture Table 11.2 16-Bit Re-encoding of Frequent MIPS32 Instruction Sequences (Continued) Register Total Major Number of Immediate Field Size of Empty 0 Minor Opcode Register Field Size Width Other Field Size Opcode Instruction Name Fields (bit) (bit) Fields (bit) Size (bit)
Page 293: Table 11.3: Instruction-Specific Register Specifiers And Immediate Field Values
11.3 microMIPS Re-encoded Instructions 11.3.1.3 Instruction-Speciﬁc Register Speciﬁers and Immediate Field Encodings Table 11.3 Instruction-Speciﬁc Register Speciﬁers and Immediate Field Values Number Immediate Register 1 Register 2 Register 3 Register Field Size Decoded Decoded Decoded Immediate Field Decoded Instruction Fields (bit) Value Value...
Page 294: Table 11.4 16-Bit Instruction General-Purpose Registers - $2-$7, $16, $17
microMIPS™ Instruction Set Architecture Table 11.3 Instruction-Speciﬁc Register Speciﬁers and Immediate Field Values (Continued) Number Immediate Register 1 Register 2 Register 3 Register Field Size Decoded Decoded Decoded Immediate Field Decoded Instruction Fields (bit) Value Value Value Value SRL16 rs1:2-7,16, 17 rd:2-7,16, 17 1..8 (see encoding tables) SUBU16...
Page 295: Table 11.5 Sb16, Sh16, Sw16 Source Registers - $0, $2-$7, $17
11.3 microMIPS Re-encoded Instructions 1. “0-7” correspond to the register’s 16-bit binary encoding and show how that encoding relates to the MIPS registers. “0-7” never refer to the registers, except within the binary microMIPS instructions. From the assembler, only the MIPS names ($16, $17, $2, etc.) or the symbolic names (s0, s1, v0, etc.) refer to the registers.
Page 296: Table 11.7 16-Bit Instruction Special-Purpose Registers
microMIPS™ Instruction Set Architecture Table 11.7 16-Bit Instruction Special-Purpose Registers Symbolic Name Purpose Program counter. The PC-relative ADDIU can access this register as an operand. Contains high-order word of multiply or divide result. Contains low-order word of multiply or divide result. 11.3.3 32-Bit Category 11.3.3.1 New 32-bit instructions The following table lists the 32-bit instructions introduced in the microMIPS ISA.
Page 297 11.3 microMIPS Re-encoded Instructions MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 298 microMIPS™ Instruction Set Architecture MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 299 Appendix A References This appendix lists other publications available from MIPS Technologies, Inc. that are referenced in this document. These documents may be included in the $MIPS_PROJECT/doc area of a typical M14K soft or hard core release, or in some cases may be available on the MIPS web site http://www.mips.com.
Page 300 References MIPS32® M14K™ Processor Core Family Software User’s Manual, Revision 02.04...
Page 301 Appendix B Revision History Change bars (vertical lines) in the margins of this document indicate signiﬁcant changes in the document since its last release. Change bars are removed for changes that are more than one revision old. This document may refer to Architecture speciﬁcations (for example, instruction set descriptions and EJTAG register deﬁnitions), and change bars in these sections indicate changes since the previous version of the relevant Architecture document.

Mips Technologies MIPS32 M14K User Manual

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Chapter 1: Introduction to the MIPS32® M14K™ Processor Core

Chapter 2: Pipeline of the M14K™ Core

Chapter 3: Memory Management of the M14K™ Core

Chapter 4: Exceptions and Interrupts in the M14K™ Core

Chapter 5: CP0 Registers of the M14K™ Core

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