Mips Technologies R4000 Design Manuals

Mips Technologies R4000 Design Manuals

Manuals and User Guides for Mips Technologies R4000 Design. We have 1 Mips Technologies R4000 Design manual available for free PDF download: User Manual

Mips Technologies R4000 User Manual

Mips Technologies R4000 User Manual (754 pages)

Microprocessor

Brand: Mips Technologies | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table of Contents
14
Introduction

32
- Benefits of RISC Design
  32
- Compatibility
  36
- Processor General Features
  36
- R4000 Processor Configurations
  37
- R4400 Processor Enhancements
  37
- R4000 Processor
  39
  - 64-Bit Architecture
    39
  - Superpipeline Architecture
    41
  - System Interface
    41
  - CPU Register Overview
    42
  - CPU Instruction Set Overview
    44
  - Data Formats and Addressing
    54
  - Coprocessors (CP0-CP2)
    57
    
    System Control Coprocessor, CP0
    57
    
    Floating-Point Unit (FPU), CP1
    60
  - Memory Management System (MMU)
    61
    
    The Translation Lookaside Buffer (TLB)
    61
    
    Cache Memory Hierarchy
    62
    
    Operating Modes
    62
    
    Primary Caches
    63
    
    Secondary Cache Interface
    63
CPU Instruction Set Summary

65
- CPU Instruction Formats
  66
  - Load and Store Instructions
    67
    
    Defining Access Types
    67
    
    Scheduling a Load Delay Slot
    67
  - Computational Instructions
    69
    
    64-Bit Operations
    69
    
    Cycle Timing for Multiply and Divide Instructions
    70
  - Jump and Branch Instructions
    71
    
    Overview of Branch Instructions
    71
    
    Overview of Jump Instructions
    71
  - Special Instructions
    72
  - Exception Instructions
    72
  - Coprocessor Instructions
    72
The CPU Pipeline

73
- CPU Pipeline Operation
  74
- CPU Pipeline Stages
  75
- Branch Delay
  78
- Load Delay
  78
- Interlock and Exception Handling
  79
  - Exception Conditions
    82
  - Stall Conditions
    83
  - Slip Conditions
    83
  - External Stalls
    83
  - Interlock and Exception Timing
    83
    
    Backing up the Pipeline
    84
    
    Aborting an Instruction Subsequent to an Interlock
    85
  - Pipelining the Exception Handling
    86
  - Special Cases
    88
    
    Correctness Considerations
    88
    
    Performance Considerations
    88
- R4400 Processor Uncached Store Buffer
  89
- Memory Management
  91
Memory Management

92
- Translation Lookaside Buffer (TLB)
  92
  - Hits and Misses
    92
  - Multiple Matches
    92
- Address Spaces
  93
  - Virtual Address Space
    93
  - Physical Address Space
    94
  - Virtual-To-Physical Address Translation
    94
  - 32-Bit Mode Address Translation
    95
  - 64-Bit Mode Address Translation
    96
  - Operating Modes
    97
    
    User Mode Operations
    97
    
    Supervisor Mode Operations
    99
    
    Kernel Mode Operations
    103
- System Control Coprocessor
  110
  - Format of a TLB Entry
    111
  - CP0 Registers
    114
    
    Index Register (0)
    115
    
    Random Register (1)
    116
    
    Entrylo0 (2), and Entrylo1 (3) Registers
    117
    
    Pagemask Register (5)
    117
    
    Wired Register (6)
    118
    
    Entryhi Register (CP0 Register 10)
    119
    
    Processor Revision Identifier (Prid) Register (15)
    119
    
    Config Register (16)
    120
    
    Cache Tag Registers [Taglo (28) and Taghi (29)]
    123
    
    Load Linked Address (Lladdr) Register (17)
    123
  - Virtual-To-Physical Address Translation Process
    125
  - TLB Misses
    127
  - TLB Instructions
    127
CPU Exception Processing

130
- How Exception Processing Works
  130
- Exception Processing Registers
  131
  - Context Register (4)
    132
  - Bad Virtual Address Register (Badvaddr) (8)
    133
  - Count Register (9)
    133
  - Compare Register (11)
    134
  - Status Register (12)
    135
    
    Status Register Format
    135
Output Buffer ∆I/∆T Control Mechanism

137
- Mode Bits
  137
- Processor Exceptions
  149
  - Exception Types
    149
    
    Cache Error Exception Process
    150
    
    Reset Exception Process
    150
    
    General Exception Process
    151
    
    Soft Reset and NMI Exception Process
    151
  - Exception Vector Locations
    152
  - Priority of Exceptions
    153
  - Reset Exception
    154
  - Soft Reset Exception
    155
  - Address Error Exception
    157
  - TLB Exceptions
    158
    
    TLB Refill Exception
    159
    
    TLB Invalid Exception
    160
    
    TLB Modified Exception
    161
  - Cache Error Exception
    162
  - Virtual Coherency Exception
    163
  - Bus Error Exception
    164
  - Integer Overflow Exception
    165
  - Trap Exception
    166
  - System Call Exception
    167
  - Breakpoint Exception
    168
  - Reserved Instruction Exception
    169
  - Coprocessor Unusable Exception
    170
  - Floating-Point Exception
    171
  - Watch Exception
    172
  - Interrupt Exception
    173
- Exception Handling and Servicing Flowcharts
  174
Floating-Point Unit

182
- Overview
  182
- FPU Features
  183
- FPU Programming Model
  184
- Floating-Point Formats
  194
- Binary Fixed-Point Format
  196
- Floating-Point Instruction Set Overview
  197
  - Floating-Point Load, Store, and Move Instructions
    199
    
    Load Delay and Hardware Interlocks
    199
    
    Transfers between FPU and CPU
    199
    
    Transfers between FPU and Memory
    199
    
    Data Alignment
    200
    
    Endianness
    200
  - Floating-Point Conversion Instructions
    200
  - Floating-Point Computational Instructions
    200
  - Branch on FPU Condition Instructions
    200
  - Floating-Point Compare Operations
    201
- FPU Instruction Pipeline Overview
  202
  - Instruction Execution
    202
  - Instruction Execution Cycle Time
    203
  - Scheduling FPU Instructions
    205
  - FPU Pipeline Overlapping
    205
    
    Instruction Scheduling Constraints
    206
    
    Instruction Latency, Repeat Rate, and Pipeline Stage Sequences
    211
    
    Resource Scheduling Rules
    212
Floating-Point Exceptions

217
- Exception Types
  218
- Exception Trap Processing
  219
- Flags
  220
- FPU Exceptions
  222
  - Inexact Exception (I)
    222
  - Invalid Operation Exception (V)
    223
  - Division-By-Zero Exception (Z)
    224
  - Overflow Exception (O)
    224
  - Underflow Exception (U)
    225
  - Unimplemented Instruction Exception (E)
    226
- Saving and Restoring State
  227
- Trap Handlers for IEEE Standard 754 Exceptions
  228
R4000 Processor Signal Descriptions

229
- System Interface Signals
  231
- Clock/Control Interface Signals
  233
- Secondary Cache Interface Signals
  235
- Interrupt Interface Signals
  237
- JTAG Interface Signals
  237
- Initialization Interface Signals
  238
- Signal Summary
  239
Initialization Interface

243
- Functional Overview
  244
- Reset Signal Description
  245
  - Power-On Reset
    246
  - Cold Reset
    247
  - Warm Reset
    247
- Initialization Sequence
  248
- Warm Reset
  251
Subblock Ordering

252
- Sequential Ordering
  252
Clock Interface

257
- Signal Terminology
  258
- Basic System Clocks
  259
  - Masterclock
    259
  - Masterout
    259
  - Syncin/Syncout
    259
  - Pclock
    259
  - Sclock
    260
  - Tclock
    260
  - Rclock
    260
  - Pclock-To-Sclock Division
    260
- System Timing Parameters
  263
  - Alignment to Sclock
    263
  - Alignment to Masterclock
    263
  - Phase-Locked Loop (PLL)
    263
- Connecting Clocks to a Phase-Locked System
  264
- Connecting Clocks to a System Without Phase Locking
  265
  - Connecting to a Gate-Array Device
    265
  - Connecting to a CMOS Logic System
    268
- Processor Status Outputs
  271
Cache Organization, Operation, and Coherency

274
- Memory Organization
  274
- Overview of Cache Operations
  275
- R4000 Cache Description
  276
- Cache States
  285
  - Primary Cache States
    286
  - Secondary Cache States
    286
  - Mapping States between Caches
    287
- Cache Line Ownership
  288
- Cache Write Policy
  289
- Cache State Transition Diagrams
  290
- Cache Coherency Overview
  294
  - Cache Coherency Attributes
    294
    
    Noncoherent
    295
    
    Sharable
    295
    
    Uncached
    295
    
    Update
    295
    
    Exclusive
    296
  - Cache Operation Modes
    296
    
    No-Secondary-Cache Mode
    296
    
    Secondary-Cache Mode
    296
  - Strong Ordering
    297
    
    An Example of Strong Ordering
    297
    
    Testing for Strong Ordering
    297
    
    Restarting the Processor
    298
- Maintaining Coherency on Loads and Stores
  299
- Manipulation of the Cache by an External Agent
  300
  - Invalidate
    300
  - Update
    300
  - Snoop
    300
  - Intervention
    301
- Coherency Conflicts
  301
  - How Coherency Conflicts Arise
    302
    
    Processor Coherent Read Requests
    302
    
    Processor Invalidate or Update Requests
    303
    
    External Coherency Requests
    304
  - System Implications of Coherency Conflicts
    305
    
    System Model
    306
    
    Load
    308
    
    Processor Coherent Read Request and Read Response
    308
    
    Store
    308
    
    Processor Invalidate
    309
    
    Processor Write
    309
  - Handling Coherency Conflicts
    310
    
    Coherent Read Conflicts
    310
    
    Coherent Write Conflicts
    311
    
    Invalidate Conflicts
    312
  - Sample Cycle: Coherent Read Request
    313
- R4000 Processor Synchronization Support
  316
  - Test-And-Set (Spinlock)
    316
  - Counter
    318
  - LL and SC
    319
  - Examples Using LL and SC
    320
  - System Interface
    323
System Interface

324
- Terminology
  324
- System Interface Description
  324
  - Interface Buses
    325
    
    Address and Data Cycles
    326
    
    Issue Cycles
    326
  - Handshake Signals
    328
- System Interface Protocols
  329
  - Master and Slave States
    329
  - Moving from Master to Slave State
    330
  - External Arbitration
    330
  - Uncompelled Change to Slave State
    331
- Processor and External Requests
  332
  - Rules for Processor Requests
    333
  - Processor Requests
    334
    
    Processor Read Request
    336
    
    Processor Write Request
    337
    
    Processor Invalidate Request
    338
    
    Processor Update Request
    340
    
    Clusters
    341
  - External Requests
    343
    
    External Invalidate Request
    346
    
    External Read Request
    346
    
    External Update Request
    346
    
    External Write Request
    346
    
    External Intervention Request
    347
    
    External Snoop Request
    347
    
    Read Response
    347
- Handling Requests
  348
  - Load Miss
    348
    
    No-Secondary-Cache Mode
    350
    
    Secondary-Cache Mode
    350
  - Store Miss
    351
    
    Secondary-Cache Mode
    353
    
    No-Secondary-Cache Mode
    355
  - Store Hit
    356
    
    No-Secondary-Cache Mode
    356
    
    Secondary-Cache Mode
    356
  - Uncached Loads or Stores
    356
  - CACHE Operations
    357
  - Load Linked Store Conditional Operation
    357
- Processor and External Request Protocols
  359
  - Processor Request Protocols
    360
    
    Processor Read Request Protocol
    360
    
    Processor Write Request Protocol
    363
    
    Processor Invalidate and Update Request Protocol
    365
    
    Processor Null Write Request Protocol
    366
    
    Processor Cluster Request Protocol
    367
    
    Processor Request and Cluster Flow Control
    368
  - External Request Protocols
    371
    
    External Arbitration Protocol
    372
    
    External Read Request Protocol
    373
    
    External Null Request Protocol
    374
    
    External Write Request Protocol
    377
    
    External Invalidate and Update Request Protocols
    378
    
    External Intervention Request Protocol
    379
    
    External Snoop Request Protocol
    382
    
    Read Response Protocol
    384
- Data Rate Control
  386
  - Data Transfer Patterns
    386
  - Secondary Cache Transfers
    387
  - Secondary Cache Write Cycle Time
    388
  - Independent Transmissions on the Sysad Bus
    389
  - System Interface Endianness
    390
- System Interface Cycle Time
  391
  - Cluster Request Spacing
    391
  - Release Latency
    392
  - External Request Response Latency
    393
- System Interface Commands and Data Identifiers
  394
  - Command and Data Identifier Syntax
    394
  - System Interface Command Syntax
    395
    
    Read Requests
    396
    
    Write Requests
    397
    
    Null Requests
    399
    
    Invalidate Requests
    400
    
    Update Requests
    400
    
    Intervention and Snoop Requests
    402
    
    Coherent Data
    404
    
    Noncoherent Data
    404
    
    System Interface Data Identifier Syntax
    404
    
    Data Identifier Bit Definitions
    405
  - System Interface Addresses
    407
    
    Addressing Conventions
    407
    
    Sequential and Subblock Ordering
    408
  - Processor Internal Address Map
    408
Secondary Cache Interface

409
- Data Transfer Rates
  410
- Duplicating Signals
  410
- Accessing a Split Secondary Cache
  411
- Scdchk Bus
  411
- SCTAG Bus
  411
- Operation of the Secondary Cache Interface
  412
  - Read Cycles
    413
    
    4-Word Read Cycle
    413
    
    8-Word Read Cycle
    414
    
    Notes on a Secondary Cache Read Cycle
    414
  - Write Cycles
    415
    
    4-Word Write Cycle
    415
    
    8-Word Write Cycle
    416
    
    Notes on a Secondary Cache Write Cycle
    417
JTAG Interface

419
- What Boundary Scanning Is
  420
- Signal Summary
  421
- JTAG Controller and Registers
  422
  - Instruction Register
    422
  - Bypass Register
    423
  - Boundary-Scan Register
    424
  - Test Access Port (TAP)
    425
    
    Controller Reset
    426
    
    Controller States
    426
    
    TAP Controller
    426
- Implementation-Specific Details
  430
R4000 Processor Interrupts

431
- Hardware Interrupts
  432
- Nonmaskable Interrupt (NMI)
  432
- Asserting Interrupts
  432
Error Checking and Correcting

438
- Error Checking in the Processor
  438
  - Types of Error Checking
    438
    
    Parity Error Detection
    438
    
    SECDED ECC Code
    439
  - Error Checking Operation
    442
    
    Secondary Cache Data Bus
    442
    
    System Interface
    442
    
    System Interface and Secondary Cache Data Bus
    442
    
    Secondary Cache Tag Bus
    443
    
    System Interface Command Bus
    443
  - SECDED ECC Matrices for Data and Tag Buses
    444
  - ECC Check Bits
    444
  - Data ECC Generation
    445
  - Detecting Data Transmission Errors
    448
    
    Single Data Bit ECC Error
    450
    
    Single Check Bit ECC Error
    451
    
    Double Data Bit ECC Errors
    452
    
    Three Data Bit ECC Errors
    453
    
    Four Data Bit ECC Errors
    454
  - Tag ECC Generation
    455
  - Summary of ECC Operations
    456
- R4400 Master/Checker Mode
  460
  - Connecting a System in Lock Step
    461
  - Master-Listener Configuration
    462
  - Cross-Coupled Checking Configuration
    463
  - Fault Detection
    465
  - Reset Operation
    466
  - Fault History
    466
  - Sra Shift Right Arithmetic
    614
  - Subblock Ordering
    713
- Delay Times
  720
- Cpu Board
  721
R4000 Pinouts

732
- Pinout of R4000PC
  732
- Pinout of R4000MC/SC Package Pinout
  735

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