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JYTEK PCIe-69529 Acquisition Module Manuals
Manuals and User Guides for JYTEK PCIe-69529 Acquisition Module. We have
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JYTEK PCIe-69529 Acquisition Module manual available for free PDF download: User Manual
JYTEK PCIe-69529 User Manual (32 pages)
8-CH 24-Bit 204.8 kS/s Dynamic Signal Acquisition Module
Brand:
JYTEK
| Category:
PCI Card
| Size: 1 MB
Table of Contents
Getting Service
2
Table of Contents
3
Introduction
7
1�1 Features
7
Applications
7
Specifications
8
1�3�1 Analog Input
8
Figure 1-1: Analog Input Channel Bandwidth, -1Dbfs 108Ks/S
11
Figure 1-2: Analog Input Channel Bandwidth, -1Dbfs 108Ks/S
11
Figure 1-3: Spurious Free Dynamic Range 54Ks/S
12
Figure 1-4: Spurious Free Dynamic Range 108Ks/S
12
1�3�2 Timebase
13
Table 1-1: Timebase
13
Figure 1-5: Spurious Free Dynamic Range 192Ks/S
13
1�3�3 Triggers
14
General Specifications
14
Table 1-2: Trigger Source & Mode
14
Table 1-3: Digital Trigger Input
14
Schematics and I/O
15
Figure 1-6: Pcie-69529 Side View
15
Figure 1-7: Pcie-69529 I/O Array
16
Software Support
17
1�5�1 Sdk
17
1�5�2 Dsa-Dask
17
Getting Started
18
2�1 Package Contents
18
Installation Environment
18
2�3 Installing the Module
19
Operations
20
Functional Block Diagram
20
3�2 Analog Input Channel
20
Analog Input Front-End Configuration
20
Figure 3-1: Analog Input Architecture
20
3�2�2 Input Range and Data Format
21
Table 3-1: Input Range and Data Format
21
3�2�3 ADC and Analog Input Filter
22
3�2�4 DMA Data Transfer
22
Table 3-2: Input Range Midscale Values
22
Table 3-3: ADC Sample Rates Vs DDS Output Clock
22
Figure 3-2: Linked List of PCI Address DMA Descriptors
23
3�3 Trigger Source and Trigger Modes
24
Figure 3-3: Trigger Architecture
24
Figure 3-4: External Digital Trigger
25
3�4 Trigger Mode
26
Table 3-4: Preferred Characteristics for Analog Triggers
26
Figure 3-5: Analog Trigger Conditions
26
Figure 3-6: Post-Trigger Acquisition
27
Figure 3-7: Delay Trigger Mode Acquisition
27
3�5 ADC Timing Control
28
3�5�1 Timebase
28
3�5�2 DDS Timing Vs� ADC
28
3�5�3 Filter Delay in ADC
28
Table 3-5: Timing Relationship between ADC and PLL Clock
28
Figure 3-8: Re-Trigger Mode Acquisition
28
Figure 3-9: Timebase Architecture
28
Synchronizing Multiple Modules
29
Table 3-6: ADC Filter Delay
29
Table 3-7: SSI Timing Signal Definitions
29
Ssi_Timebase
30
3�6�2 Ssi_Sync_Start
30
3�6�3 Ssi_Ad_Trig
30
Figure 3-10: SSI Architecture
30
Appendix A Calibration
31
Calibration Constant
31
Auto-Calibration
31
Important Safety Instructions
32
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