Getting Service Contact us should you require any service or assistance. SHANGHAI JYTEK Co., Ltd. Web site: http://www.jytek.com Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203 China Tel: +86-21-5047-5899 Fax: +86-21-5047-5899 Email: service@jytek.com Additional information, aids, and tips that help users perform tasks Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.
1 Introduction The PCIe-69529 is a high-performance 8-CH 24-Bit 204.8 kS/s dynamic signal acquisition module, specifically designed for applications such as structural health monitoring, noise, vibration, and harshness (NVH) measurement, and phased array data acquisition. The PCIe-69529 features 24-bit simultaneous sampling at 204.8 kS/s over 8 channels, and a 110 dB dynamic range, providing ample power for high-density, high channel count signal measurement, and vibration-optimized lower AC cutoff frequency of 0.5 Hz.
1�3 Specifications 1�3�1 Analog Input Channel Characteristics Channels Type Differential or pseudo-differential Coupling AC or DC, software selectable AC coupling cutoff frequency 0.5Hz ADC resolution 24-Bit ADC type Delta-sigma Input signal range ±10V, ±1V Sampling rate (FS) 8 kS/s to 204.8 kS/s, 768 μS/s increments for Fs >...
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-3 dB Bandwidth Sample rate -3 dB bandwidth Fs < 108 kS/s >0.4863 FS Fs > 108 kS/s >0.22 FS 1. Disable digital filter when Fs < 108 kS/s; Enable digital filter when Fs > 108 kS/s Flatness Flatness (dB) Input Range (V) 54 kS/s 108 kS/s...
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Total Harmonic Distortion plus noise (THD+N) THD+N (dBc) Input Range (V) 54 kS/s 108 kS/s 192 kS/s 20 Hz to 22 kHz 20 Hz to 45 kHz 20 Hz to 42 kHz ±1V ±10V 1. 1 kHz input tone and -1 dBFS input amplitude Intermodulation Distortion IMD (dBc) Input Range (V)
1�3�3 Triggers Trigger Source & Mode Trigger source Software, external digital trigger, analog trigger, and SSI Trigger mode Post trigger and delay trigger Table 1-2: Trigger Source & Mode Digital Trigger Input Sources Front panel SMB connector Compatibility 3.3 V TTL, 5 V tolerant Input high threshold 2.0 V Input low threshold (VIL)
Aside from programming libraries, such as DLLs, for most Windows-based systems, JYTEK also provides other drivers. 1�5�1 SDK For customers who want to write their own programs, JYTEK provides the following software development kits. • .NET driver for Windows, compatible with various application environments, such as C#, VB.NET, VC.NET, VB/VC++, BCB, and Delphi...
• Anti-static wrist strap • Antistatic mat JYTEK PCIe-69529 DSA modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.
2�3 Installing the Module 1. Turn off the computer. 2. Remove the top cover. 3. Select an available PCI express x4 slot and remove the bracket-retaining screw and the bracket cover. 4. Line up the PCI express digitizer with the PCI express slot on the backpanel. Slowly push down on the top of the PCI express digitizer until its card-edge connector is resting on the slot receptacle.
Following completion of A/D conversion, A/D data is buffered in a Data FIFO, and can then be transferred to PC memory for further processing. Transfer characteristics of the two input ranges of the PCIe-69529 are as follows. Data format of the PCIe-69529 is 2’s complement.
3�2�4 DMA Data Transfer The PCIe-69529, as a PCIe Gen1 X 4 device, provides a 204.8 KS/s sampling rate ADC, generating a 3.276 MByte/second rate. To provide efficient data transfer, a PCI bus- mastering DMA is essential for continuous data streaming, as it helps to achieve the full potential PCI Express bus bandwidth.
bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list to enable transfer of large amounts of data without memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system.
SSI_AD_TRIG Figure 3-3: Trigger Architecture The PCIe-69529 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PCIe-69529 supports internal software trigger, external digital trigger and SSI Bus Number 5 as well as analog trigger.
When configured as input the PCIe-69529 serves as a slave module and can accept trigger signals from SSI Bus Number 5, asserted from other PCIe-69529 modules. When configured as output, the PCIe-69529 serves as a master module and can output trigger signals to SSI Bus Number 5.
When configured as input the PCIe-69529 serves as a slave module and can accept trigger signals from SSI Bus Number 5, asserted from other PCIe-69529 modules. When configured as output, the PCIe-69529 serves as a master module and can output trigger signals to SSI Bus Number 5.
Post Trigger Mode If post trigger mode is configured, activity commences once the following trigger conditions are met: • The analog input channel acquires a programmed number of samples at a specified sampling rate • The analog output channel outputs pre-defined voltage at a specified output rate Figure 3-6: Post-Trigger Acquisition Delay Trigger Mode If delay trigger mode is configured, delay time from when the trigger event asserts to the...
Operation 1st Trigger Event Occurs 2nd Trigger Event Occurs start Time Trigger Data N samples N samples Figure 3-8: Re-Trigger Mode Acquisition 3�5 ADC Timing Control 3�5�1 Timebase Onboard Oscillator SYNC_CLK SSI_TIMEBASE ADC0_CLK ADC1_CLK SSI_TIMEBASE FPGA_MCLK Figure 3-9: Timebase Architecture An onboard timebase clock drives the sigma-delta ADC, with frequency exceeding the sample rate and produced by a PLL chip, with output frequency programmable to superior resolution.
The PCIe- 69529 utilizes the SSI Bus [0:7] as a System Synchronization Interface (SSI). Dedicate routing of timebase clock and trigger signals onto the SSI Bus enables the PCIe-69529 to simplify synchronization between multiple modules.
SSI bus achieving synchronization on the three timing signals, as follows. 3.6.1 SSI_TIMEBASE As output, the SSI_TIMEBASE signal transmits the onboard ADC timebase through the SSI bus. As input, the PCIe-69529 accepts the SSI_TIMEBASE signal as the source of the timebase. 3�6�2 SSI_SYNC_START Before a SSI master issues SSI_AD_TRIG to other SSI slaves, SSI_SYNC_START is first asserted by the master card, synchronizing all on-chip ADCs in both SSI Master and SSI Slave modules.
A�1 Calibration Constant The PCIe-69529 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PCIe-69529 driver loads these calibration constants, such that analog input path errors are minimized. JYTEK provides a software API for calibrating the PCIe-69529.
Important Safety Instructions For user safety, please read and follow all instructions, WARNINGS , CAUTIONS , and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. • Read these safety instructions carefully. • Keep this user’s manual for future reference. •...
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