IXYS zilog Z51F6412 Microcontroller Manuals

Manuals and User Guides for IXYS zilog Z51F6412 Microcontroller. We have 1 IXYS zilog Z51F6412 Microcontroller manual available for free PDF download: Manual

IXYS zilog Z51F6412 Manual (189 pages)

Brand: IXYS | Category: Microcontrollers | Size: 1 MB

Table of Contents
4
Overview
11
Description
11
Features
11
Ordering Information
12
Table 1-1 Ordering Information for the Z51F6412 MCU
12
Development Tools
13
Figure 1-2 Single Programmer
15
Figure 1-3 Gang Programmer
15
Block Diagram
16
Figure 2-1 Z51F6412 Block Diagram
16
Pin Assignmnet
17
Figure 3-1 Z51GF64 80-Pin LQFP Assignment
17
Figure 3-2 Z51GF64A 64 Pin LQFP Assignment
18
Package Diagram
19
Figure 4-1 80 Pin LQFP Package
19
Figure 4-2 64 Pin LQFP Package
20
Pin Description
21
Table 5-1 Normal Pin Description
21
Port Structures
24
General Purpose I/O Port
24
Figure 6-1 General Purpose I/O Port
24
External Interrupt I/O Port
25
Figure 6-2 External Interrupt I/O Port
25
Electrical Characteristics
26
Absolute Maximum Ratings
26
Recommended Operating Conditions
26
Table 7-1 Absolute Maximum Ratings
26
Table 7-2 Recommended Operation Conditions
26
A/D Converter Characteristics
27
Voltage Dropout Converter Characteristics
27
Table 7-3 A/D Converter Characteristics
27
Table 7-4 Voltage Dropout Converter Characteristics
27
Power-On Reset Characteristics
28
Brown out Detector Characteristics
28
Internal RC Oscillator Characteristics
28
Table 7-5 Power-On Reset Characteristics
28
Table 7-6 Brown out Detector Characteristics
28
Table 7-7 Internal RC Oscillator Characteristics
28
Ring-Oscillator Characteristics
29
PLL Characteristics
29
Table 7-8 Ring-Oscillator Characteristics
29
Table 7-9 PLL Characteristics
29
DC Characteristics
30
Table 7-10 DC Characteristics
30
AC Characteristics
31
Figure 7-1 AC Timing
31
Table 7-11 AC Characteristics
31
SPI Characteristics
32
Figure 7-2 SPI Timing
32
Table 7-12 SPI Characteristics
32
Typical Characteristics
33
Memory
34
Program Memory
34
Figure 8-1 Program Memory
34
Data Memory
35
Figure 8-2 Data Memory Map
35
XSRAM Memory
36
Figure 8-3 Lower 128 Bytes RAM
36
Figure 8-4 XDATA Memory Area
36
SFR Map
37
Table 8-1 SFR Map Summary
37
I/O Ports
40
Port Register
40
Table 9-1 Register Map
41
Px Port
42
Interrupt Controller
45
Overview
45
Table 10-1 Interrupt Group Priority Level
45
External Interrupt
46
Figure 10-1 External Interrupt Description
46
Block Diagram
47
Figure 10-2 Block Diagram of Interrupt
47
Interrupt Vector Table
48
Table 10-2 Interrupt Vector Address Table
48
Interrupt Sequence
49
Figure 10-3 Interrupt Vector Address Table
49
Effective Timing after Controlling Interrupt Bit
50
Figure 10-4 Effective Time of Interrupt Request after Setting Iex Registers
50
Multi Interrupt
51
Figure 10-5 Execution of Multi Interrupt
51
Interrupt Enable Accept Timing
52
Interrupt Service Routine Address
52
Saving/Restore General-Purpose Registers
52
Figure 10-6 Interrupt Response Timing Diagram
52
Figure 10-7 Correspondence between Vector Table Address and the Entry Address of ISP
52
Figure 10-8 Saving/Restore Process Diagram & Sample Source
52
Interrupt Timing
53
Figure 10-9 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
53
Interrupt Register Overview
54
Interrupt Register Description
55
Table 10-3 Register Map
55
Peripheral Hardware
61
Clock Generator
61
Figure 11-1 Clock Generator Block Diagram
61
Table 11-1 Register Map
62
Table 11-2 VDC Current Consumption
64
Bit
65
Figure 11-2 BIT Block Diagram
65
Table 11-3 Register Map
65
Wdt
67
Figure 11-3 WDT Block Diagram
67
Table 11-4 Register Map
67
Figure 11-4 WDT Interrupt Timing Waveform
69
Figure 11-5 Watch Timer Block Diagram
70
Table 11-5 Register Map
70
Timer/Pwm
73
Table 11-6 Operating Modes of Timer
73
Figure 11-6 Bit Timer/Event Counter2, 3 Block Diagram
74
Figure 11-7 Timer/Event Counter0, 1 Example
75
Figure 11-8 Operation Example of Timer/Event Counter0, 1
75
Figure 11-9 16 Bit Timer/Event Counter0, 1 Block Diagram
76
Figure 11-10 8-Bit Capture Mode for Timer0, 1
77
Figure 11-11 Input Capture Mode Operation of Timer 0, 1
78
Figure 11-12 Express Timer Overflow in Capture Mode
78
Figure 11-13 16-Bit Capture Mode of Timer 0, 1
79
Figure 11-14 PWM Mode
80
Table 11-7 PWM Frequency Vs. Resolution at 8 Mhz
80
Figure 11-15 Example of PWM at 4Mhz
81
Figure 11-16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz
81
Table 11-8 Register Map
82
Figure 11-17 Timer4 16-Bit Mode Block Diagram
86
Figure 11-18 16-Bit Capture Mode of Timer X
87
Figure 11-19 PWM Mode
88
Table 11-9 PWM Frequency Vs. Resolution at 8 Mhz
88
Figure 11-20 Example of PWM at 8Mhz
89
Table 11-10 Register Map
89
Buzzer Driver
95
Figure 11-21 Buzzer Driver Block Diagram
95
Table 11-11 Buzzer Frequency at 16Mhz
95
Table 11-12 Register Map
96
Usart
97
Figure 11-22 USART Block Diagram
98
Figure 11-23 Clock Generation Block Diagram
99
Table 11-13 Equations for Calculating Baud Rate Register Setting
99
Figure 11-24 Synchronous Mode Xckn Timing
100
Figure 11-25 Frame Format
101
Figure 11-26 Start Bit Sampling
105
Figure 11-27 Sampling of Data and Parity Bit
105
Figure 11-28 Stop Bit Sampling and Next Start Bit Sampling
106
Table 11-14 CPOL Funtionality
106
Figure 11-29 SPI Clock Formats When UCPHA=0
107
Figure 11-30 SPI Clock Formats When UCPHA=1
108
Table 11-15 Register Map
108
Table 11-16 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
114
Spi
115
Figure 11-31 SPI Block Diagram
115
Figure 11-32 SPI Transmit/Receive Timing Diagram at CPHA = 0
117
Figure 11-33 SPI Transmit/Receive Timing Diagram at CPHA = 1
117
Table 11-17 Register Map
117
Table 15-1 Register Map
117
I 2 C
120
Figure 11-34 I 2 C Block Diagram
120
Figure 11-35 Bit Transfer on the I C-Bus
121
Figure 11-36 START and STOP Condition
121
Figure 11-37 Data Transfer on the I 2 C-Bus
122
Figure 11-38 Acknowledge on the I 2 C-Bus
122
Figure 11-39 Clock Synchronization During Arbitration Procedure
123
Figure 11-40 Arbitration Procedure of Two Masters
123
Figure 11-41 Formats and States in the Master Transmitter Mode
126
Figure 11-42 Formats and States in the Master Receiver Mode
128
Figure 11-43 Formats and States in the Slave Transmitter Mode
130
Figure 11-44 Formats and States in the Slave Receiver Mode
132
12-Bit A/D Converter
137
Figure 11-45 ADC Block Diagram
137
Figure 11-46 A/D Analog Input Pin Connecting Capacitor
138
Figure 11-47 A/D Power(AVDD) Pin Connecting Capacitor
138
Figure 11-48 ADC Operation for Align Bit
138
Figure 11-49 Converter Operation Flow
139
Calculator_Ai
143
Figure 11-50 Calculator Block Diagram
143
Power down Operation
148
Overview
148
Peripheral Operation in IDLE/STOP Mode
148
Table 12-1 Peripheral Operation During Power down Mode
148
IDLE Mode
149
Figure 12-1 IDLE Mode Release Timing by External Interrupt
149
Figure 12-2 IDLE Mode Release Timing by /RESET
149
STOP Mode
150
Figure 12-3 STOP Mode Release Timing by External Interrupt
150
Figure 12-4 Mode Release Timing by /RESET
150
Release Operation of STOP1, 2 Mode
151
Figure 12-5 STOP1, 2 Mode Release Flow
151
Table 12-2 Register Map
152
Reset
153
Overview
153
Reset Source
153
Block Diagram
153
Figure 13-1 RESET Block Diagram
153
Table 13-1 Reset State
153
RESET Noise Canceller
154
Power on RESET
154
Figure 13-2 Reset Noise Canceller Time Diagram
154
Figure 13-3 Fast VDD Rising Time
154
Figure 13-4 Internal RESET Release Timing on Power-Up
155
Figure 13-5 Configuration Timing When Power-On
155
Figure 13-6 Boot Process Waveform
156
Table 13-2 Boot Process Description
156
External RESETB Input
157
Figure 13-7 Timing Diagram after RESET
157
Figure 13-8 Oscillator Generating Waveform Example
157
Brown out Detector Processor
158
Figure 13-9 Block Diagram of BOD
158
Figure 13-10 Internal Reset at the Power Fail Situation
158
Figure 13-11 Configuration Timing When BOD RESET
159
Table 13-3 Register Map
159
On-Chip Debug System
161
Overview
161
Two-Pin External Interface
162
Figure 14-1 Block Diagram of On-Chip Debug System
162
Figure 14-2 10-Bit Transmission Packet
163
Figure 14-3 Data Transfer on the Twin Bus
163
Figure 14-4 Bit Transfer on the Serial Bus
164
Figure 14-5 Start and Stop Condition
164
Figure 14-6 Acknowledge on the Serial Bus
164
Figure 14-7 Clock Synchronization During Wait Procedure
165
Figure 14-8 Connection of Transmission
165
Memory Programming
166
Overview
166
Flash Control and Status Register
166
Table 15-2 Program/Erase Time
168
Memory Map
170
Figure 15-1 Flash Memory Map
170
Figure 15-2 Address Configuration of Flash Memory
171
Serial In-System Program Mode
172
Figure 15-3 the Sequence of Page Program and Erase of Flash Memory
172
Figure 15-4 the Sequence of Bulk Erase of Flash Memory
173
Parallel Mode
177
Figure 15-5 Pin Diagram for Parallel Programming
177
Figure 15-6 Parallel Byte Read Timing of Program Memory
178
Figure 15-7 Parallel Byte Write Timing of Program Memory
179
Mode Entrance Method of ISP and Byte-Parallel Mode
180
Figure 15-8 ISP Mode
180
Figure 15-9 Byte-Parallel Mode
180
Security
181
Configure Option
182
Configure Option Control Register
182
Appendix
183

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