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IDT TSI384 User Manual

Pcie-to-pci bridge
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Tsi384 PCIe
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User Manual
May 5, 2014

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  • Page 1 ® ® Tsi384 PCIe -to-PCI Bridge ® User Manual May 5, 2014...
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Lane Reversal and Polarity Reversal ............44 Integrated Device Technology Tsi384 User Manual www.idt.com...
  • Page 4 INTx Interrupt Signaling ............72 Tsi384 User Manual...
  • Page 5 PCIe Clocking ..............114 Integrated Device Technology Tsi384 User Manual www.idt.com...
  • Page 6 Accessing SerDes TAP Controller............141 Tsi384 User Manual...
  • Page 7 Short-term Caching Period Register ..........200 Integrated Device Technology Tsi384 User Manual www.idt.com...
  • Page 8 14.10.6 PCIe Debug and Pattern Generator Control Register ........240 Tsi384 User Manual...
  • Page 9 Index ..............277 Integrated Device Technology Tsi384 User Manual www.idt.com...
  • Page 10 Contents Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...
  • Page 11 Tsi384 Device Architecture........
  • Page 12 Drive Strength and Equalization Waveform ........... . . 272 Tsi384 User Manual...
  • Page 13 Table 17: Abnormal Conditions and Tsi384’s Response to Split Completion Message ......100 Table 18: ECRC Errors .
  • Page 14 Part Numbers ................269 Tsi384 User Manual...

  • Page 15: About This Document

    • “Document Conventions” • “Revision History” Scope The Tsi384 PCIe-to-PCI Bridge User Manual discusses the features, capabilities, and configuration requirements for the Tsi384. Document Conventions This document uses the following conventions. Non-differential Signal Notation Non-differential signals are either active-low or active-high. An active-low signal has an active state of logic 0 (or the lower voltage level), and is denoted by a lowercase “n”.
  • Page 16 Preliminary – Contains information about a product that is near production-ready, and is revised as required. • Formal – Contains information about a final, customer-ready product, and is available once the product is released to production. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 17: Revision History

    Changed the minimum value of the T parameter for PCI 66 MHz to 2 ns (see Table July 2008, Formal • Removed reference to PCIE_REXT pin because it is not applicable to the Tsi384 • Changed the Pin Type definition of various signals (see “Signal Descriptions”) •...
  • Page 18 • Added error handling tables for PCIe and PCI/X (see “Error Handling Tables”) • Updated the power supply sequencing information to indicate that the Tsi384 does not have any specific sequencing constraints (see “Power Supply Sequencing”) • Redefined two SerDes registers (see “PCIe Debug and Pattern Generator Control Register”...

  • Page 19: Functional Overview

    • “Typical Applications” Overview The IDT Tsi384 is a high-performance bus bridge that connects the PCI Express (PCIe) protocol to the PCI and PCI-X bus standards (see Figure The Tsi384’s PCIe Interface is a superior performance, configurable port that supports 1, 2, or 4 lanes.

  • Page 20: Features

    Buffer Queue PCI/X PCI/X Interface JTAG Arbiter 80E1000_BK001_01 (Tsi384) Features The Tsi384’s key features are listed in the following sub-sections. 1.2.1 General Features • Forward bridge, PCIe to PCI/X • Single store and forward for optimal latency performance • Supports three modes of addressing: —...

  • Page 21: Pcie Features

    Up to eight outstanding memory reads • 4-KB read completion buffer 1.2.4 PCI Features • 32/64-bit addressing • 32/64-bit data bus • 25-, 33-, 50-, and 66-MHz operation • Up to eight outstanding read requests Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 22: Device Architecture

    1. Functional Overview • 4-KB read completion buffer • Short-term caching support Device Architecture A high-level, architectural diagram of the Tsi384 is displayed in Figure 2. For more information about data flow through the device, see “Upstream Data Path” “Downstream Data Path”.
  • Page 23 • Upstream posted write buffer PCI-X read completion (Tsi384 is target), from a split transaction, are also decoded and sent to the downstream read completion buffer. Transactions destined for downstream devices on the PCI/X bus, are subject to PCI/X ordering rules.
  • Page 24 Once the master on the PCI bus retries the read transaction, the transaction is checked to determine if the read data is returned. If it has the read data, the Tsi384 responds as the target and transfers the read data to the PCI bus. Note the upstream read completion buffer is not a simple FIFO, as the order that masters on the PCI bus retry is not deterministic.

  • Page 25: Typical Applications

    The downstream read request queue is managed with flow control credits to prevent overflowing. The Tsi384 latches the read transaction and attempts to reserve space in the downstream read completion buffer. If space is successfully reserved in the buffer, the Tsi384 acts as the master for the transaction and initiates a read transaction on the PCI/X bus.

  • Page 26: Figure 4: External Storage Application

    Figure 5: Server Add-in Cards for Networking and Storage PCI-X 133 MHz GbE/FC Controller Tsi384 GbE/FC Controller PCI-X 133 MHz PCIe x4 PCI 66 MHz SCSI Controller Tsi384 SCSI Controller PCI 66 MHz PCIe x4 Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 27: Signal Descriptions

    3.3V CMOS input with 265K (+/- 45K) pull-up resistor 3.3 Out 3.3V CMOS output PCI/X Bidir PCI/X bi-directional PCI/X Bidir OD PCI/X bi-directional open-drain PCI/X In PCI/X input PCI/X Out PCI/X output PCI/X OD PCI/X output open-drain Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 28: Pcie Interface Signals

    Design Recommendation PCIE_PERSTn 3.3 In Master reset in: Direct connect to the PERST# signal. 0 = Tsi384 in reset 1 = Tsi384 in normal mode PCIE_TXD_n[3:0] PCIE Diff Out Transmit Data. These differential pair DC blocking capacitors must be placed PCIE_TXD_p[3:0]...

  • Page 29: Pci/X Interface Signals

    PCI_CBE[7:4]. transaction type. PCI_CLK PCI/X In PCI Input Clock. This signal provides None. timing for the Tsi384, either from an external clock or from one of the PCI_CLKO[4:0] signals (see “Clocking”). PCI_CLKO[4:0] PCI/X Out PCI Output Clock. PCI_CLKO[3:0] are...
  • Page 30 Pull ups are not required on unused differently depending on whether or not outputs. the Tsi384 PCI/X arbiter is used. If the arbiter is used, then PCI_GNTn[3:0] are outputs used by the Tsi384 to grant access to the bus (see “PCI/X...
  • Page 31 Pull up (8.2K) to 3.3V. request access to the PCI/X bus. They PCI/X Bidir are used differently, however, depending on whether or not the Tsi384 PCI/X arbiter is used. If the PCI/X arbiter is used, then PCI_REQn[3:0] are inputs used by external masters to request access to the bus.

  • Page 32: Eeprom Interface Signals

    (CS) on the external EEPROM. SR_DIN 3.3 Out Serial ROM data in: This signal transfers output data from the Tsi384 to the EEPROM. SR_DOUT 3.3 In PU Serial ROM data out: This signal transfers input data from the EEPROM to the Tsi384.

  • Page 33: Jtag Interface Signals

    AND gate where externally to reset the TAP controller. inputs are TRST# and PERST#. For more information, see the Tsi384 Evaluation Board User Manual. TEST_BCE 3.3 In Test Boundary Scan Compatibility For 1149.1 Boundary Scan testing, this...

  • Page 34: Power-Up Signals

    PWRUP_CLK_MST 3.3 In PU Clock Master: None. 0 = Tsi384 is clock slave on the PCI/X bus; it requires an external PCI/X bus clock. 1 = Tsi384 is clock master on the PCI/X bus (clock master mode); it drives the PCI/X bus clock.
  • Page 35 GND, analog PLL power None. a. For filtering and decoupling information for these signals, see “Power Supply Filtering and Decoupling” in the Tsi384 Board Design Guidelines. b. For more information, see “Analog Power Supply Filtering” in the Tsi384 Board Design Guidelines.
  • Page 36 2. Signal Descriptions Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 37: Data Path

    Posted and completion buffers allow the Tsi384 to accept a few more cycles of data transfer even after the assertion of stall which indicates to the initiator in the PCI Core to stop the data transfer. This buffer design ensures idle cycles are not inserted in data cycles while forwarding TLPs to its egress block.

  • Page 38: Downstream Data Path

    PCI/X Cor e 3.1.2 Downstream Data Path In the downstream path, the Tsi384 uses one-stage buffering for each type of transaction (see Figure These buffers support the store and forward method, receive flow control, protocol differences, synchronization, and error handling requirements.

  • Page 39: Transaction Management

    Detec t e r PCIe Core PCI Core Transaction Management The following sub-sections describe how the Tsi384 handles upstream and downstream transactions. 3.2.1 Upstream Transaction Management Transactions that originate on the PCI/X Interface that are destined for the PCIe Interface are stored in...

  • Page 40: Downstream Transaction Management

    TLP header, payload, and any detected error information, is sent to the PCI Core. The Tsi384 uses receive flow control buffers in the PCI Core instead of in the PCIe Core to store downstream requests or completions to be forwarded on the PCI/X Interface.

  • Page 41: Upstream Posted Buffer

    Every 512-byte buffer also consists of 32-byte sub-sections in PCI mode and 128-byte subsections in PCI-X mode. In PCI mode, the Tsi384 allows the delayed response data transfer to the requester only if the programmed number of 32-byte chunks of data are accumulated in the data buffer (see CPL_INIT_COUNT in “PCI Miscellaneous Control and Status...

  • Page 42: Downstream Non-Posted Buffer

    A single transaction can use 512 bytes of buffer space. The Tsi384 uses an 8-deep request FIFO to store the request information, including the first and last Dwords byte enables. The Tsi384 initiates a transaction on the PCI/X Interface only after a complete packet is stored in the buffer.

  • Page 43: Prefetching Algorithm

    “Prefetch Control Register”. The default value of these bits indicates that either 128 bytes in 32-bit bus mode or 256 bytes in 64-bit bus mode is prefetched. The Tsi384 prefetches one cacheline if P_MRL is set to • Prefetch algorithm for memory read multiple command is controlled by P_MRM, MRM_66 and MRM_33 of the “Prefetch Control...

  • Page 44: Short Term Caching

    Register”. If the initiator generates a new transaction that requests the previously prefetched data, the Tsi384 returns that data. The Tsi384 discards data after some of the data for a request is returned to the initiator and one of the following conditions is met: •...

  • Page 45: Addressing

    “Opaque Addressing” Overview This chapter discusses the various types of address decoding performed by the Tsi384 when it forwards transactions upstream and downstream. The memory and I/O address ranges are defined using a set of base and limit registers in the bridge’s configuration header. The base and limit address registers define the address ranges that a bridge forwards downstream transactions.

  • Page 46: Figure 8: Memory-Mapped I/O Address Space

    VGA_EN bit in “PCI Bridge Control and Interrupt Register” The Tsi384 forwards memory transactions downstream from its PCIe Interface to its PCI/X Interface if a memory address is in the range defined by the Memory Base and Memory Limit registers (when the...

  • Page 47: Prefetchable Space

    VGA Enable bit in “PCI Bridge Control and Interrupt Register” The Tsi384 forwards memory transactions downstream from its PCIe Interface to its PCI/X Interface if a memory address is in the range defined by the Prefetchable Memory Base and Prefetchable Memory Limit registers.

  • Page 48: I/O Space

    Memory Mapped I/O I/O Space I/O Base, I/O Limit, I/O Base Upper 16 Bits, and I/O Limit Upper 16 Bits registers in the Tsi384 configuration header specify an address range that is used by the bridge to determine whether to forward I/O read and I/O write transactions across the bridge.

  • Page 49: Figure 10: I/O Address Space

    0x0_B000 – 0x0_BFFF 0x0_B000 – 0x0_BFFF 0x0_A000 – 0x0_AFFF 0x0_A000 – 0x0_AFFF 0x0_9000 – 0x0_9FFF 0x0_9000 – 0x0_9FFF 0x0_8000 – 0x0_8FFF 0x0_8000 – 0x0_8FFF 0x0_0000 – 0x0_7FFF 0x0_0000 – 0x0_7FFF Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 50: Vga Addressing

    Tsi384 blocks the forwarding of I/O transactions downstream if the I/O address is in the top 768 bytes of each naturally aligned 1-KB block. If the ISA Enable bit is clear, the Tsi384 forwards downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers.

  • Page 51: Non-Transparent Addressing

    Limit registers always define the range of addresses to be claimed on the PCIe link and forwarded to the PCI/X bus, cycles that are claimed have their addresses modified because of the difference in the base addresses of the windows on the two buses. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 52: Pcie To Pci/X Non-Prefetchable Address Remapping

    • SecNPAddr = PriNPAddr - PriSecNPDiff, where — SecNPAddr: Defines the remapped address that the Tsi384 presents on the PCI/X bus. — PriNPAddr: Defines the address presented to the Tsi384 that falls within the registers described in the previous paragraph.

  • Page 53: Pci/X To Pcie Address Remapping

    Secondary Upper Base Register”. • PriNTMALimit = SecNTMALimit + PriSecNTMADiff, where — SecNTMALimit: Defined by “NTMA Secondary Lower Limit Register” “NTMA Secondary Upper Limit Register”. — PriSecNTMADiff: See previous bullet. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 54: Figure 12: Memory Window Remapping Example

    I/O Address Remapping “PCI I/O Address Upper 16 Register” in the Tsi384 configuration space indicates the number of upper bits of the I/O address that are not used when forwarding downstream I/O space cycles to the PCI/X bus. This allows I/O addresses to be translated down into the address range that is available on the PCI/X bus.

  • Page 55: Opaque Addressing

    4. Addressing Opaque Addressing Opaque address ranges are defined in the Tsi384 configuration space. This feature can be enabled by setting OPQ_MEM_EN to 1 in the “SERRDIS_OPQEN_DTC Register”. Memory transactions with addresses that fall in the opaque address range are not claimed by either the PCIe or PCI/X Interfaces.
  • Page 56 4. Addressing Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 57: Configuration Transactions

    Tsi384. Type 1 transactions are converted to Type 0 transactions if they target devices that reside on the downstream Tsi384 bus. If the transaction is intended for a device that is downstream of the bus directly below the Tsi384, the transaction is passed through the Tsi384 as a Type 1 configuration transaction.

  • Page 58: Type 0 Configuration Transactions

    The Tsi384 responds to PCIe Type 0 configuration transactions that address its configuration space. This type of transaction configures the Tsi384 and is not forwarded downstream. The Tsi384 ignores Type 0 configuration transactions that originate on the PCI/X Interface. If a Type 0 configuration cannot be processed, the Tsi384 handles it as an Unsupported Request.

  • Page 59: Type 1 Configuration Transactions

    If a PCIe Type 1 configuration transaction’s Bus Number field is equal to the Secondary Bus Number value, and the conditions for conversion to a Special Cycle transaction are not met, the Tsi384 forwards the transaction to the PCI/X bus as a Type 0 configuration transaction. In this case, a device connected to the PCI/X Interface of the bridge is the target of the Type 0 configuration transaction.

  • Page 60: Type 1 To Type 1 Forwarding

    Unsupported Request on PCIe and a received Master-Abort on the destination bus. If the field is zero, the Tsi384 decodes the PCIe Device Number field and asserts a single address bit in the range PCI_AD[31:16] during the address phase (for device numbers in the range 0b0_0000 to 0b0_ 1111b).

  • Page 61: Pcie Enhanced Configuration Mechanism

    Extended Register Addressing. If a configuration transaction targets the PCI/X bus and has a non-zero value in the Extended Register Address field, the Tsi384 handles the transaction as if it received a Master-Abort on the PCI/X bus and then does the following: •...
  • Page 62 5. Configuration Transactions Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 63: Bridging

    “Transaction Ordering” Overview The Tsi384 provides a connection path between a PCI/X bus and a PCIe link. The main function of the Tsi384 is to allow transactions between a master or a transmitter on one bus\link, and a target or a receiver on the other bus\link.

  • Page 64: Buffer Size And Management

    The Tsi384 uses 2-KB retry buffering, which is large enough to ensure that under normal operating conditions upstream traffic is never throttled. Ack latency value, internal processing delays, and receiver L0s exit latency values, are considered for determining the Retry buffer size.

  • Page 65: Forwarding Of Pcie To Pci

    The Tsi384 attempts another outstanding request if the current request is retried or disconnected to improve the link bandwidth utilization. It does not attempt to read beyond the requested length. The Tsi384 decomposes the requests if the requested data length is greater than 128 bytes, and returns the completions in 128-byte boundary fragments.

  • Page 66: Forwarding Of Pcie To Pci-X

    6.6.2 PCIe Non-posted Requests The Tsi384 translates the PCIe Memory Read Requests into the PCI-X transactions that use one of the PCI-X memory read commands, either Memory Read DWORD or Memory Read Block, based on requested byte enables, prefetchable and non-prefetchable memory windows. PCIe Read Request command translation is completed as follows: •...

  • Page 67: Forwarding Of Pci To Pcie

    Since PCI read requests do not specify the amount of data to be read, the Tsi384 uses a programmable prefetch algorithm to determine the amount of data to be read on behalf of the original requester. The Tsi384 does not attempt to prefetch past the 4-KB address boundary on behalf of the original requester.

  • Page 68: Forwarding Of Pci-X To Pcie

    PCI-X Interface a with split response and then forwards them onto the PCIe Interface. Once the completion is returned for the forwarded request, the Tsi384 provides data for reads and status for the writes to the requester through split completion and split completion message transactions, respectively.

  • Page 69: Pci Transaction Support

    Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1101b Dual Address Cycle 1110b Memory Read Line 1111b Memory Write and Invalidate a. For unsupported transactions, see “PCIe as Originating Interface”. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 70: Pci-X Transaction Support

    1010b Configuration Read 1011b Configuration Write 1100b Split Completion 1101b Dual Address Cycle 1110b Memory Read Block 1111b Memory Write Block a. For unsupported transactions, see “PCI/X as Originating Interface”. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 71: Pcie Transaction Support

    Completion without Data CplD Completion with Data CplLk Completion without Data for MRR- Locked CplDLk Completion with Data for MRR - Locked a. For unsupported transactions, see “PCIe as Originating Interface”. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 72: Message Transactions

    PCIe messages are routed depending on specific bit field encodings in the message request header. 6.13.1 INTx Interrupt Signaling The Tsi384 forwards the INTx interrupts – PCI_INT[A:D]n – generated by PCI devices onto the PCIe Interface, as PCIe Assert_INTx and Deassert_ INTx messages (for more information, see “Interrupt Handling”).

  • Page 73: Transaction Ordering

    No – The second transaction is not allowed to pass the first transaction. The Tsi384 does not allow a posted transaction to pass another posted transaction even if the relaxed ordering attribute bit is set. However, the device allows a Read completion with the relaxed ordering attribute bit set to pass a posted transaction.
  • Page 74 6. Bridging Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 75: Pci/X Arbitration

    PCI Core. When the arbiter is disabled, there must be an external arbiter on the PCI/X bus that handles Tsi384 requests through the PCI_REQ[0]n signal, and grants bus access using the PCI_GNT[0] signal. Grant for the PCI Core is the muxed output of internal arbiter grant and external arbiter grant with PWRUP_EN_ARB as select signal.

  • Page 76: Pci/X Arbitration Scheme

    “PCI Miscellaneous Control and Status Register”). The Tsi384, by default, is assigned a high priority and the other requesters are also assigned a high priority. Based on the arbitration priority setting, requesters are divided into two priority levels (see Figure 19).

  • Page 77: Figure 19: Pci/X Arbitration Priority

    19, it is assumed that all PCI/X bus masters, including the Tsi384, are requesting the bus at the same time. Since the Tsi384 and devices A and B are assigned a high priority they are granted access to the bus first. Once device B is granted access, one of the bus requests from the low priority group —...
  • Page 78 7. PCI/X Arbitration Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 79: Interrupt Handling

    PCI/X Interface, it forwards it as a memory write TLP on its PCIe link. Both INTx messages and MSI/MSI-X transactions flow through the Tsi384’s upstream posted buffer, as displayed in Figure The Tsi384 does not contain an MSI capability structure. The bridge cannot generate MSIs; it can only forward them as posted memory writes. Integrated Device Technology Tsi384 User Manual www.idt.com...

  • Page 80: Interrupt Sources

    PCI Express Base Specification (Revision 1.1). Interrupt Sources The Tsi384 does not have an internal source of interrupts: it forwards legacy PCI_INT[D:A]n interrupts from the PCI/X Interface to the PCIe Interface in the form of Assert[D:A] and De-assert[D:A] messages with Tsi384 PCIe transaction IDs.

  • Page 81: Error Handling

    “Error Handling Tables” Overview This chapter discusses how the Tsi384 handles errors that occur during the processing of upstream and downstream transactions. For all errors that are detected by the bridge, it sets the appropriate Error Status bits – PCI/X Error bit(s) and PCIe Error status bit(s) – and generates an error message on PCIe, if enabled.
  • Page 82 PCIe Interface, regardless of the error reporting enable bits. The Tsi384 also supports Advisory Non-Fatal error messages in the case where a TLP Error detected is a Advisory Non-Fatal Error and the Advisory Non-Fatal Error mask bit, ANFE, in the “PCIe...

  • Page 83: Figure 21: Pcie Flowchart Of Device Error Signaling And Logging Operations

    9. Error Handling Figure 21: PCIe Flowchart of Device Error Signaling and Logging Operations Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 84: Pcie As Originating Interface

    9. Error Handling PCIe as Originating Interface This section describes how the Tsi384 handles error support for transactions that flow downstream from PCIe to PCI/X (see Figure 22). In the case of reception of a Write Request or Read Completion with a Poisoned TLP, the entire data...

  • Page 85: Received Poisoned Tlps

    Master-Abort Unsupported Request Target-Abort Completer Abort In the case of an Advisory Non-Fatal Error detection, the following actions are taken by the Tsi384: 1. If the severity of the TLP Error detected in “PCIe Uncorrectable Error Severity Register” Non-Fatal then: a.

  • Page 86: Received Ecrc Errors

    SERR_EN bit is set in the “PCI Control and Status Register”. 4. In all three of the previous cases the following actions are also taken by the Tsi384: • D_PE bit is set in “PCI Control and Status Register”...

  • Page 87: Pci/X Uncorrectable Data Errors

    “PCIe Device Control and Status Register” For an immediate read transaction, if the Tsi384 detects an uncorrectable data error on the destination bus it continues to fetch data until the byte count is satisfied, or the target on the destination bus ends the transaction.
  • Page 88 “PCIe Device Control and Status Register” If the target signals split response, the Tsi384 terminates the transaction as it would for a split request that did not have an error and takes no further action. If the returned split completion is a split completion error message, the bridge returns a PCIe Completion with Unsupported Request status to the requester.

  • Page 89: Pci/X Uncorrectable Address/Attribute Errors

    7. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in the “PCIe Device Control and Status Register” 9.2.5 Received Master-Abort on PCI/X Interface This section describes the actions taken by the Tsi384 when a Master-Abort is received on the PCI/X Interface. 9.2.5.1 Master Abort on a Posted Transaction...
  • Page 90 “PCIe Device Control and Status Register” 9.2.5.2 Master-Abort On PCI/X Interface for Non-Posted Transaction When the Tsi384 receives a Master-Abort on the PCI/X bus while forwarding a non-posted PCIe request, it does the following: 1. Returns a completion with Unsupported Request status on the PCIe 2.

  • Page 91: Received Target-Abort On Pci/X Interface

    “PCIe Device Control and Status Register” 9.2.6 Received Target-Abort On PCI/X Interface This section describes the functionality of the Tsi384 when a Target-Abort is received on the PCI/X Interface in response to posted, non-posted and split completion transactions. 9.2.6.1 Target Abort On A Posted Transaction...

  • Page 92: Pcie Unsupported Request Completion Status

    “PCIe Device Control and Status Register” 9.2.6.3 Target-Abort On PCI-X Interface For Split Completion When the Tsi384 forwards PCIe completions to the PCI-X Interface as split completions and it encounters a Target Abort, it takes the following actions: 1. Discards the entire transaction 2.

  • Page 93: Pcie Completer Abort Completion Status

    9.2.8 PCIe Completer Abort Completion Status When the Tsi384 receives a completion with Completer Abort status on the PCIe Interface in response to any forwarded non-posted PCI-X transaction, it takes the following actions: 1. R_TA bit is set in the “PCI Control and Status Register”...

  • Page 94: Pci/X As Originating Interface

    9. Error Handling PCI/X as Originating Interface This section describes how the Tsi384 handles errors for upstream transactions from PCI/X to PCIe (see Figure 23). The bridge supports TLP poisoning as a Transmitter to permit proper forwarding of parity errors that occur on the PCI/X Interface.

  • Page 95: Received Pci/X Errors

    9. Error Handling Table 16 describes the Tsi384 behavior on a PCI Delayed transaction that is forwarded by a bridge to PCIe as a Memory Read request or an I/O Read/Write request, and the PCIe Interface returns a completion with Unsupported Request or Completer Abort Completion status for the request.
  • Page 96 Uncorrectable Data Error on a Posted Write When the Tsi384 receives posted write transaction that is addressed such that it crosses the bridge and the bridge detects an uncorrectable data error on its secondary PCI/X Interface, it does the following: 1.
  • Page 97 9.3.1.4 Uncorrectable Data Error on Split Read Completion When the Tsi384 receives a Split Read Completion that crosses the bridge and the bridge detects an Uncorrectable Data Error on the PCI-X secondary interface, it does the following: 1. If P_PERESP bit is set in “PCI Bridge Control and Interrupt...
  • Page 98 “PCIe Device Control and Status Register” 9.3.1.7 Uncorrectable Attribute Error When the Tsi384 detects an Uncorrectable Attribute Error and parity error detection is enabled via the Parity Error Response Enable bit in “PCI Bridge Control and Interrupt Register” then the bridge takes the following actions: 1.

  • Page 99: Unsupported Request Completion Status

    A Completer Abort response on PCIe translates to a Delayed Transaction Target-Abort if the secondary interface is in PCI mode. The Tsi384 provides data to the requesting agent up to the point where data was successfully returned from the PCIe interface, and then signals Target-Abort. R_TA is set in “PCI...

  • Page 100: Split Completion Message With Completer Errors

    None Error 9.3.4.1 Split Completion Message with Master Abort When the Tsi384 receives a Split Completion message with Master-Abort, it takes the following actions: 1. Completion with Unsupported request is returned to the requester 2. R_MA is set in “PCI Secondary Status and I/O Limit and Base Register”...
  • Page 101 “PCIe Device Control and Status Register” 9.3.4.2 Split Completion Message with Target Abort When the Tsi384 receives a Split Completion message with Target Abort, it takes the following actions: 1. Completion with Completer Abort is returned to the requester 2. R_TA is set in “PCI Secondary Status and I/O Limit and Base Register”...
  • Page 102 “PCIe Secondary Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI Control and Status Register” or FTL_ERR_EN/NFTL_ERR_EN bit is set in “PCIe Device Control and Status Register” Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 103: Timeout Errors

    PCI mode, they act as endpoints for requests that they take ownership. When the Tsi384 detects a completion timeout it responds as if a completion with Unsupported Request status has been received and follows the rules for handling Unsupported Request Completions as described in “Unsupported...

  • Page 104: Other Errors

    Other Errors PCI devices can assert SERR# when detecting errors that compromise system integrity. When the Tsi384 detects SERR# on the secondary interface, it does the following: 1. S_SERR bit is set in “PCI Secondary Status and I/O Limit and Base Register”...

  • Page 105: Error Handling Tables

    [SERR_EN] bit is set in same register. “PCI Control and Status Register” [D_PE]. “PCI Control and Status Register” [MDP_D] is set if the Poisoned TLP is a read completion and [PERESP] is set in same register. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 106: Table 20: Malformed Tlp Errors

    IO request with TC > 0, or Attribute > 0 or Length > 1DW or LBE > 0 Configuration request with TC>0, or Attribute > 0 or Length >1DW or LBE > 0 Violations of RCB rules CRS response to non-configuration request Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 107: Table 21: Link And Flow Control Errors

    “PCIe Device Control and Status Register” [COR_ERR_DTD]. 3. Optional ERR_COR message sent. Replay timer expires “PCIe Correctable Error Status Register” [RT_TO]. “PCIe Device Control and Status Register” [COR_ERR_DTD]. 3. Optional ERR_COR message sent. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 108: Table 22: Uncorrectable Data/Address/Attribute Errors

    “PCI Bridge Control and Interrupt Register”. “PCI Control and Status Register” [S_SERR] if error message is sent and “PCIe Secondary Uncorrectable Error [SERR_EN] is set in same register. Status Register” [UDERR]. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 109: Table 23: Received Master/Target Abort Error

    “PCIe Secondary Uncorrectable Error [S_SERR] if error message is sent and Status Register” [R_TA]. Target-Abort on the PCI bus [SERR_EN] is set in same register. while forwarding a non-posted transaction from PCIe Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 110: Table 25: Request Errors

    “PCIe Device Control and Status Register” Non-configuration or message [UNS_REQ_DTD]. received while in D1, D2 or D3 “PCIe Device Control and Status Register” hot. [COR_ERR_DTD] if ANFE. Configuration Type 0 access with a non-zero function. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 111: Reset, Clocking, And Initialization

    The Tsi384 inputs resets from upstream devices, and drives reset to downstream devices. PCIE_PERSTn is the reset input to the bridge, and is normally connected to a power-on reset controller at the system level. The Tsi384 drives reset onto the PCI/X bus using PCI_RSTn (see Table 26).

  • Page 112: Pcie Link Reset

    A cold reset is applied after power up. This is a traditional power-on reset that is generally driven at the system level by a power-on reset controller. After release of PCIE_PERSTn, all of Tsi384’s registers are in their power-on reset state, including sticky bits. Clock (PCIE_REFCLK_n/p) and power must be valid prior to the release of PCIE_PERSTn.

  • Page 113: Pci/X Bus Reset

    A hot reset is also be initiated during a DL_down condition. DL_down means that the Tsi384 has lost communications at the physical or data link layer with the upstream device.

  • Page 114: Clocking

    Tx pins, PCIE_TXD_n/p[3:0] (note that only one lane is shown). The receive data is clocked into the Tsi384 with the recovered clock. The elastic buffer operates on the recovered byte clock (from K28.5) and the internal generated 125-MHz clock. The two clocks can vary by twice the ppm tolerance of the reference clock tolerance on any one device (300ppm).

  • Page 115: Figure 26: Pci/X Clocking

    PCI- X 13 3 MHz PCI- X 66 MHz PCI 6 6 MHz The PCI-X capability of the Tsi384 is determined by the choice of external components connected to the PCI_PCIXCAP signal (see Table 28). During initialization, logic controls PCI_PCIXCAP_PU, which is initially tri-stated.

  • Page 116: Figure 27: Master Mode Clocking

    PCI_M6 6EN PCI_SEL100 Decod er Logic PCI_PCIXCAP PCI_PC I XCAP_PU 0.0 1uF 10 K 0 .01uF PCI- X 13 3 MHz PCI- X 6 6 MHz PCI 6 6 MHz Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 117: Table 29: Master Mode And Clock Rate

    10K to ground PCI-X 100 MHz High PCI-X 133 MHz High Table 30: Master Mode External Clock Compensation Mode PWRUP_CLK_MST PWRUP_EXT_CLK_SEL Master with external clock compensation Master without external clock compensation Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 118: Figure 28: Slave Clocking

    The clock source is PCI_CLK. Clock compensation for the internal clock tree delay inside the Tsi384 is provided when the PCI/X bus is determined to be operating at greater than 33 MHz (for more information, see Table 31).

  • Page 119: Initialization

    Slave with Tsi384 Clock tree compensation >33 MHz 10.3 Initialization When the Tsi384 comes out of reset (level 0, 1, or 2), its clock speed and capabilities are determined according to Table 29 when in clock master mode, and Table 31 when in clock slave mode.

  • Page 120: Table 33: Initialization Pattern

    10. Reset, Clocking, and Initialization The Tsi384 drives the initialization pattern onto the PCI/X bus prior to the de-assertion of PCI_RSTn according to the following table. Table 33: Initialization Pattern DEVSEL STOP TRDY Mode Bus Rate De-asserted De-asserted De-asserted PCI 33...

  • Page 121: Power Management

    11.1 Overview The Tsi384 provides basic power management support to its PCI/X bus and PCIe link. PCI/X power management states are mapped to specific PCIe link states. The bridge also supports Active State Power Management (ASPM), where the device enters into power saving state and initiates exit when needed.

  • Page 122: Unsupported Features

    In the Tsi384, L0s entry is disabled by default. When L0s entry is enabled and the Tsi384 Transmit module is in idle state for more then 6 micro seconds – that is, there is no transmission of packets for 6 micro seconds – the Tsi384 Transmit module enters the L0s state. The bridge initiates exit from the L0s state when it has pending TLPs or DLLPs for transmission.

  • Page 123: L0 State

    The Tsi384 does not support L1 entry in ASPM. The L1 may be entered whenever the bridge is programmed to a D3 state. TLP and DLLP communication over the link is prohibited when the Tsi384 is in the L1 state. L1 exit can be initiated by the Tsi384 or an upstream device. 11.3.5 L2/L3 Ready The L2/L3 Ready state is a staging point for the L2 or L3 states.

  • Page 124: Link State Summary

    Recovery state L2/L3 Ready L2/L3 Ready - This arc indicates Psudo-state to the case where the prepare component platform does not for loss of power and use Vaux ref clock Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 125: Device Power States

    “PCI Power Management Control and Status Register” is set to 1 in the Tsi384 when software programs the bridge back to the D0 state. L1 exit can be initiated by the Tsi384 or an upstream device. 11.3.12 State Cold The Tsi384 transitions to the D3Cold state when its power is removed.

  • Page 126: D State Transitions

    TLP packets that are always routed in the direction of the root complex. To send a PM_PME message on its upstream link, the Tsi384 must transition the link to the L0 state if the link is not already in the L0 state. The PCI_PMEn pin is sampled every 100 microseconds for PM_PME message generation.

  • Page 127: Power State Summary

    Ready to remove power, will not respond to ready Power removed cold cold a. The Tsi384 drives PCI_CLKO[4:0], does not assert PCI_RSTn, responds to PCI_PMEn, does not participate in bus transactions. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 128 11. Power Management Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 129: Serial Eeprom

    12.1 Overview The Tsi384 uses an internal serial EEPROM Controller to configure its configuration space register (CSR) block with the values stored in an external serial EEPROM. The Controller is compatible with EEPROM devices that use the Serial Peripheral Interface, such as the Atmel AT25010A, AT25020A, AT25040A, AT25080A, AT25160A, AT25320A, and AT25640A.

  • Page 130: System Diagram

    Space Register SR_DIN The Tsi384 internal clock block generates an EEPROM clock of 7.8 MHz to supply to the external EEPROM. This clock is derived from the PCIe clock of frequency 125 MHz. The first two locations in the EEPROM – byte address 0x0000 and 0x0001 – contain the identification code.
  • Page 131 (byte count) is located. Thereafter, it continuously reads all the bytes and programs the CSR registers depending on the address provided in the EEPROM location. The Tsi384 has now determined the EEPROM Controller supports 9-bit addressing (it uses this mode for writes as well).

  • Page 132: Eeprom Image

    FFFBh CSR register r byte enable [3:0], CSR register r Address [11:8] Any number FFFCh CSR register r Data [7:0] Any number FFFDh CSR register r Data [15:8] Any number Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 133: Functional Timing

    Controller are provided in the following figures. Figure 32: 9-bit EEPROM Read Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_CLK SR_DIN SR_DIN SR_DIN High-Z High-Z SR_DOUT SR_DOUT SR_DOUT Opcode Opcode Address Address Data Data Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 134: Figure 33: 16-Bit Eeprom Read Timing

    High - Z Opcode Opcode Address Address Data Data Figure 34: 9-bit EEPROM Write Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_DIN SR_DIN SR_DOUT SR_DOUT High-Z High-Z Opcode Opcode Address Address Data Data Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 135: Figure 35: 16-Bit Eeprom Write Timing

    High-Z SR_DOUT SR_DOUT Figure 37: EEPROM RDSR Instruction Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_DIN SR_DIN High-Z High-Z SR_DOUT SR_DOUT Opcode Opcode Data Data Note: RDSR means Read Status Register Instruction. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 136 12. Serial EEPROM Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 137: Jtag

    — Bypass register — Device ID register — User test data register (DR) • Supports debug access of the Tsi384’s configuration registers — During mission mode or not — Bus arbitration with configuration cycles • Supports the following instruction opcodes —...

  • Page 138: Tap Controller Initialization

    13.2 TAP Controller Initialization After power-up of the Tsi384, the TAP controller must be put into its test-logic-reset state to disable the JTAG logic and allow the bridge to function normally. This can be completed by driving the JTAG_TMS signal high and pulsing the JTAG_TCK signal five or more times, or by asserting the JTAG_TRSTn signal.

  • Page 139: Jtag Register Access

    13.6.1 Register Access from JTAG The format for access the Tsi384’s DR register using JTAG is shown in the following figures. The same DR register is used for read and write access. Figure 38: Read/Write Access from JTAG — Serial Data In...

  • Page 140: Read Access To Registers From Jtag Interface

    Second bit shifted out is the Error bit. 1. Note that the address here is the DWORD address, not the byte address. Take the byte address and remove the 2 LSBs, >>2. Tsi384 User Manual Integrated Device Technology May 5, 2014...

  • Page 141: Dedicated Test Pins

    CRSEL instruction for writing and reading registers in the IP. To access the SerDes TAP controller through JTAG pins, JTAG_TDI pin of SerDes is connected to the JTAG_TDI pin and the TDO of SerDes is connected to the JTAG_TDI of the Tsi384’s top-level TAP controller through a mux with JTAG_BCE pin as selector.
  • Page 142 13. JTAG Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 143: Register Descriptions

    “Advanced Error Reporting Capability Registers” • “PCIe and SerDes Control and Status Registers” 14.1 Overview The following terms describe the Tsi384’s register attributes: • R - Read only. • RE - Read only; however, it can be modified by power-up signals or serial EEPROM.

  • Page 144: Pci Configuration Space

    14. Register Descriptions 14.2 PCI Configuration Space The Tsi384 device uses a standard PCI Type 1 configuration header. Table 37 shows the PCI 3.0 compatible Type 1 configuration space with constant values shown populated in the appropriate header fields. The PCIe 1.1 compatible capabilities options are located later in the configuration space starting...

  • Page 145: Table 38: Pci-X Capability Registers

    Table 40: PCIe Capability Registers Offset Page PCIe Capability Register Next Pointer Capability ID 0x0C0 Device Capability 0x0C4 Device Status Device Control 0x0C8 Link Capability 0x0CC Link Status Link Control 0x0D0 Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 146: Table 41: Advanced Error Reporting Capability Registers

    Secondary Uncorrectable Error Status Register 0x12C Secondary Uncorrectable Error Mask Register 0x130 Secondary Uncorrectable Error Severity Register 0x134 Secondary Error Capabilities and Control Register 0x138 0x13C 0x140 Secondary Header Log Register 0x144 0x148 Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 147: Register Map

    14. Register Descriptions 14.3 Register Map The following table lists the register map for the Tsi384. Table 42: Register Map Offset Name 0x000 PCI_ID “PCI Identification Register” 0x004 PCI_CSR “PCI Control and Status Register” 0x008 PCI_CLASS “PCI Class Register” 0x00C PCI_MISC0 “PCI Miscellaneous 0 Register”...
  • Page 148 “Secondary Bus Non-prefetchable Address Remap Control Register” 0x0E8 AR_SBNPBASE “Secondary Bus Non-prefetchable Upper Base Address Remap Register” 0x0EC AR_SBPPRECTRL “Secondary Bus Prefetchable Address Remap Control Register” 0x0F0 AR_SBPREBASEUPPER “Secondary Bus Prefetchable Upper Base Address Remap Register” Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...
  • Page 149 “PCIe Secondary Header Log 3 Register” 0x148 PCIE_SEC_HL4 “PCIe Secondary Header Log 4 Register” 0x14C-204 Reserved 0x208 REPLAY_LATENCY “Replay Latency Register” 0x20C ACKNAK_UPD_LAT “ACK/NACK Update Latency Register” 0x210 N_FTS “N_FTS Register” Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 150: Pci Identification Register

    15:0 Vendor ID 0x10E3 This field indicates the silicon vendor identification number. By default, the Tsi384 device reports a value of 0x10E3 indicating the vendor as IDT (formerly Tundra). This value can be overridden through serial EEPROM programming. Tsi384 User Manual...

  • Page 151: Pci Control And Status Register

    Unsupported Request Completion Status on its PCIe Interface. 0 = Unsupported Request Completion Status not received on the PCIe Interface 1 = Unsupported Request Completion Status received on the PCIe Interface Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 152 0 = No uncorrectable data error detected on the PCIe Interface 1 = Uncorrectable data error detected on the PCIe Interface This field is set by the Tsi384 if its Parity Error Response Enable bit is set and either of the following conditions occurs: •...
  • Page 153 This field does not apply for PCIe bridges. It always reads 0. PERESP Parity Error Response Enable This bit controls the Tsi384’s setting of the Master Data Parity Error bit in the Status register in response to a received poisoned TLP from PCIe.
  • Page 154 1 = Enable forwarding of memory transactions to the PCI/X Interface and any internal function. I/O Space Enable This bit controls the Tsi384’s response as a target to I/O transactions on the PCIe Interface that address a device that resides behind the bridge.

  • Page 155: Pci Class Register

    14. Register Descriptions 14.3.3 PCI Class Register This register indicates the PCI classification of the Tsi384. Register name: PCI_CLASS Register offset: 0x008 Reset value: 0x0604_0002 Bits 31:24 BASE 23:16 15:08 PROG 07:00 Bits Name Description Type Reset value 31:24 BASE...

  • Page 156: Pci Miscellaneous 0 Register

    Software programs the system cacheline size in DWORD counts. The value programmed is used by the Tsi384 for prefetching data from memory for Memory Read Line and Memory Line Multiple transactions on the primary bus interface. Software should set only one bit at anytime.

  • Page 157: Pci Bus Number Register

    S_LTIMER Secondary Latency Timer Undefined This value is used by the Tsi384 to perform burst transfers on the PCI/X Interface. The lower 3 bits are hardwired to 0 so that the timer is limited to 8-cycle granularity. This field defines the minimum amount of time in PCI clock cycles that the Tsi384 can retain ownership as a bus master on the PCI/X Interface.

  • Page 158: Pci Secondary Status And I/O Limit And Base Register

    Received Master Abort R/W1C This bit reports the detection of a Master-Abort termination by the Tsi384 when it is the master of a transaction on its PCI/X Interface. 0 = No Master-Abort detected. 1 = Master-Abort detected on the PCI/X Interface.
  • Page 159 Reset value S_TA Signaled Target Abort R/W1C The Tsi384 sets this bit to report the signaling of Target-Abort as target of a transaction on the PCI/X Interface. 0 = No Target-Abort signaled. 1 = Target-Abort signaled by the Tsi384 on its PCI/X Interface.
  • Page 160 07:04 IO_BA[3:0] I/O Base Address The Tsi384 uses this field for I/O address decoding. These bits define the lower bound of address range used by the bridge to forward an I/O transaction from one interface to the other. These 4 bits correspond to address bits <15:12>. The address bits <11:0>...

  • Page 161: Pci Memory Base And Limit Register

    This field defines the lower bound of the address range for forwarding memory-mapped I/O transactions. These bits correspond to address bits <31:20> of the address range. The lower 20 address bits (19:0) are 20’h0. 03:00 Reserved Reserved Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 162: Pci Pfm Base And Limit Register

    Bits <19:0> of the address range are 0xFFFFF. 19:16 ADD_LA_64 Addressing Capability — Memory Base Address The Tsi384 supports 64-bit addressing. 15:04 Prefetchable Memory Base Address This field defines the lower bound of the prefetchable memory address range. These bits correspond to address bits <31:20>...

  • Page 163: Pci Pfm Base Upper 32 Address Register

    “PCI PFM Base and Limit Register” to specify the upper bound of the 64-bit prefetchable address range. The 32 bits relate to address bits <63:32> of the Prefetchable Limit Address. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 164: Pci I/O Address Upper 16 Register

    32-bit address range used for decoding I/O transaction from the PCIe Interface to the PCI/X Interface. These bits relate to address bits <31:16> of I/O Base Address. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 165: Pci Capability Pointer Register

    Reset value 31:08 Reserved Reserved 07:00 CAP_PTR Capabilities Pointer 0x080 This register contains the head pointer for the capability list in the PCI configuration space (see “PCI-X Capability and Status Register”). Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 166: Pci Bridge Control And Interrupt Register

    Reserved DISCARD_SERR Discard Timer SERR# Enable This bit only applies in PCI mode. It enables the Tsi384 to generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the PCIe Interface when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge.
  • Page 167 Primary Discard Timer This bit does not apply to PCIe. It always reads 0. S_FPTP_EN Fast Back-to-Back Enable The Tsi384 cannot generate fast back-to-back transactions as a master on the PCI/X Interface. S_RESET Secondary Bus Reset This bit forces the assertion of PCI_RST# on the PCI/X Interface.
  • Page 168 1 KB. This bit has meaning only if VGA Enable bit is set. 1 = Executes 16-bit address decodes on VGA I/O accesses 0 = Executes 10-bit address decodes on VGA I/O accesses Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...
  • Page 169 (addresses defined above) from PCIe to PCI/X (if the I/O Enable and Memory Enable bits are set) independent of the I/O and memory address ranges, and independent of the ISA Enable bit. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 170 Reset value ISA_EN ISA Enable This bit modifies the response by the Tsi384 to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and Limit registers and are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh).
  • Page 171 The Tsi384 does not generate interrupts. Therefore, this register is hardwired to 0x00. 07:00 INT_LINE [7:0] Interrupt Line 0xFF The Tsi384 does not generate an interrupt. Therefore, the register is read only. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 172: Secondary Retry Count Register

    31:4 Reserved Reserved SEC_RT_CNT This field defines the number of retries that the Tsi384 will 0000 receive on the secondary bus for a requested transaction, before its internal retry counter expires. When the counter expires, the bridge discards the request.

  • Page 173: Pci Miscellaneous Control And Status Register

    Reserved Reserved P_ERR Parity Error Behavior This bit controls the behavior of the Tsi384 when it detects a data parity error during a non-posted write transaction. 0 = PCI_PERRn is asserted and the corrupted data is passed. 1 = PCI_PERRn is asserted and the transaction is asserted on the originating bus, appropriate status bits are set, data is discarded, and the request is not enqueued.
  • Page 174 22:21 Reserved Reserved ARB_PRI Internal Arbiter Priority This bit sets priority for Tsi384 requests. 0 = Internal requests from the Tsi384 are assigned low priority 1 = Internal requests from the Tsi384 are assigned high priority ARB_PRI3 Arbiter Priority 3 0 = Tsi384 assigns low priority to PCI_REQ3#.
  • Page 175 Reset value 10:08 CFG_RT Configuration Retry Timer The Tsi384 returns the Completion with CRS completion status for the received Type 1 configuration requests if this timer is expired before receiving the Completion from the targeted secondary device. 000 = 25 us...

  • Page 176: Pci Miscellaneous Clock Straps Register

    Reserved OP_MODE Operating Mode This bit overrides the PCIXCAP signal from PADS: 0 = Tsi384 samples the PCIXCAP from PADS 1 = Tsi384 overrides the PCIXCAP from PADS CS_MODE Clock Speed and Interface Mode This field defines the clock speed and Interface mode when...

  • Page 177: Upstream Posted Write Threshold Register

    00000 = 16 bytes 00001 = 32 bytes 00010 = 48 bytes 00011 = 64 bytes 00100 = 80 bytes 00101 = 96 bytes 00110 = 112 bytes 00111 = 128 bytes Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 178: Completion Timeout Register

    CPL_TO_EN Completion Timeout Enable This bit enables/disables the Completion Timeout function. The Tsi384 handles an upstream non-posted request as if completion is returned with UR if the completion is not returned before its Completion Timeout Timer is expired. 0 = Disable Completion Timeout Timer...

  • Page 179: Clock Out Enable Function And Debug Register

    12:08 CLKOUT_ENB This field enables and disables the five clocks 11111 (PCI_CLK_OUT[4:0]) supplied to the PCI/X secondary devices when the Tsi384 is enabled as clock master through the PWRUP_CLK_MST power-up signal. CLKOUT_ENB[0] 0 = Disable PCI_CLK_OUT[0] 1 = Enable PCI_CLK_OUT[0]...

  • Page 180: Serrdis_Opqen_Dtc Register

    1 = Enable opaque range in memory address space. Requests that fall in this range are handled with Unsupported Requests on primary interface and Master-Abort on secondary interface. Reserved Reserved Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 181: Opaque Addressing Registers

    The Opaque address range is defined in the memory address space. Any memory transaction hitting this range is not claimed by the Tsi384. Base and limit values are programmed in following device-specific registers. Opaque addressing decoding enabled by setting OPQ_MEM_EN to 1 in the “SERRDIS_OPQEN_DTC...

  • Page 182: Opaque Memory Upper Base Register

    Register name: PCI_OPQMEMLUP Register offset: 0x064 Reset value: 0x0000_0000 Bits 31:24 OPQ_UL 23:16 OPQ_UL 15:08 OPQ_UL 07:00 OPQ_UL Bits Name Description Type Reset value 31:00 OPQ_UL Opaque memory upper limit. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 183: Upstream Non-Transparent Address Remapping Registers

    14.5 Upstream Non-transparent Address Remapping Registers The Tsi384 supports address remapping, which is one of the requirements of non-transparent bridging. All transactions that fall in the non-transparent address range are mapped to different address locations according to following device-specific registers.

  • Page 184: Ntma Primary Upper Base Register

    Register offset: 0x070 Reset value: 0x0000_0000 Bits 31:24 NTMA_LBA 23:16 NTMA_LBA Reserved 15:08 Reserved 07:00 Reserved Bits Name Description Type Reset value 31:20 NTMA_LBA NTMA Secondary lower base address. 19:00 Reserved Reserved Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 185: Ntma Secondary Upper Base Register

    Register offset: 0x078 Reset value: 0x0000_0000 Bits 31:24 NTMA_LLA 23:16 NTMA_LLA Reserved 15:08 Reserved 07:00 Reserved Bits Name Description Type Reset value 31:20 NTMA_LLA NTMA Secondary lower limit address. 19:00 Reserved Reserved Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 186: Ntma Secondary Upper Limit Register

    NTMA_ULA NTMA Secondary Upper limit address. 14.6 PCI Capability Registers The Tsi384 device supports PCI/X and PCIe extended capabilities options. The Capabilities Pointer field in the “PCI Capability Pointer Register” (0x034) points to the first PCI/X capabilities option, while the first PCIe extended capability option is always located at 0x100 (see “PCIe Advanced Error...

  • Page 187: Pci-X Capability And Status Register

    011 = 133 MHz 100-111 = Reserved Split Request Delayed The Tsi384 sets this bit when it delays the forwarding of a request from the PCIe Interface to the PCI-X Interface due to insufficient buffer space to accept the Split Completion.
  • Page 188 0 = No Split Completion has been discarded. 1 = Split Completion is discarded. CAP133 133-MHz Capable This bit is hardwired to 1 because the Tsi384 can operate at 133-MHz on the PCI-X Interface. 64-bit Device This bit indicates the width of the PCI-X Interface.

  • Page 189: Pci-X Bridge Status Register

    Reserved 0x000 Split Request Delayed The Tsi384 sets this bit when it has a request to forward a transaction on the PCIe Interface but cannot because there is insufficient room within the limit specified in SPLIT_LMT in “PCI-X Upstream Split Transaction Control Register”.
  • Page 190 Number field (AD[15:11]) of the address of a Type 0 Configuration Write Request that is assigned to this bridge by the upstream PCIe device. The Tsi384 uses this number as described for the Function Number field. Each time the bridge is addressed by a PCIe Type 0...

  • Page 191: Pci-X Upstream Split Transaction Control Register

    This field is hardwired to 0x0020, indicating the size of the buffer in ADQs (32 ADQs), available for buffering Split Completions from the secondary bus interface to the primary bus interface. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 192: Pci-X Downstream Split Transaction Control Register

    This field is hardwired to 0x0004, indicating the size of the buffer in ADQs (4 ADQs), available for buffering Split Completions from the primary bus interface to the secondary bus interface. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 193: Pci Power Management Capability Register

    In the absence of Serial EEPROM information, the Tsi384 will report PME support for power levels down to D3 D2_SP D2 Support This field always returns 0 since the Tsi384 does not support the D2 power management state. D1_SP D1 Support This field always returns 0 since the Tsi384 does not support the D1 power management state.
  • Page 194 Next Pointer 0xC0 This field points to the next capability option: “PCIe Capabilities Register” (0x0C0). CAP_ID Capability ID 0x01 This field contains the value 0x01 indicating a power management capability option. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 195: Pci Power Management Control And Status Register

    Note: The Tsi384 does not support this feature; this bit always returns a 0. 14:13 DATA_SC Power Data Scale This field always returns 0 since the Tsi384 device does not support the DATA field. 12:9 DATA_SEL Power Data Select This field always returns 0 since the Tsi384 device does not support the DATA field.
  • Page 196 This field determines the current power state of the PCI function, and sets a new state. If the new state is not supported, the change is ignored. 00 = D0 01 = D1 10 = D2 11 = D3 Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 197: Eeprom Control Register

    EEPROM. 23:08 Address 0x0000 This is the EEPROM address to be read from or written into. 07:00 DATA DATA 0x00 This is the data to be written into the EEPROM. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 198: Secondary Bus Device Mask Register

    9, assert pin PCI_AD (Pin 31) instead. Reserved Reserved. Masking for device 8 is not implemented. Operation of the Tsi384 is unaffected by the value of this bit. DEVMSK_7 Device Mask 7 0 = Rerouting disabled for device 7.
  • Page 199 4, assert pin PCI_AD (Pin 31) instead. 19:18 Reserved Reserved. Masking for devices 3 and 2 is not implemented. Operation of the Tsi384 is unaffected by the value of these bits. DEVMSK_1 Device Mask 1 0 = Rerouting disabled for device 1.

  • Page 200: Short-Term Caching Period Register

    ST_CACHE Bits Name Description Type Reset value 31:00 ST_CACHE Short Term caching period 0x0000_ 0040 This field indicates the number of PCI clock cycles allowed before short-term caching is discarded. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 201: Retry Timer Status Register

    Secondary Retry timer status For more information on this timer, see “Secondary Retry Count Register”. 0 = Secondary retry timer has not expired 1 = Secondary retry timer has expired Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 202: Prefetch Control Register

    Reserved 0x00 P_MR 0 = The Tsi384 fetches a Dword of data in case of 32-bit PCI data bus mode, and two Dwords in case of 64-bit PCI data bus mode. 1 = The Tsi384 prefetches as per the value specified in MRL_66/MRL_33 fields on behalf of the PCI master for memory read command.

  • Page 203: Pcie Capability Registers

    6’h00 = 64 bytes 6’h01 = 128 bytes 6’h3F = 4096 bytes 14.7 PCIe Capability Registers In the Tsi384, the PCIe capability is located in PCI 2.3 configuration space at 0x0C0 and contains 20 bytes. Integrated Device Technology Tsi384 User Manual www.idt.com...

  • Page 204: Pcie Capabilities Register

    PCIe Reserved. It always reads 0. 29:25 INT_MN PCIe Interrupt Message Number 00000 The Tsi384 device does not have slot status or root port status. It always reads 0. SLOT_IMP PCIe Slot Implemented This field is not applicable for a bridge device. It always reads 0.

  • Page 205: Pcie Device Capabilities Register

    PCI Express Base Specification (Revision 1.1). This bit must be set by all devices conforming to the ECN, PCIe 1.1 Specification, or subsequent PCIe Base Specification revisions. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 206 L1 ASPM state. L0S_LAT PCIe Endpoint L0s Acceptable Latency This field indicates the acceptable latency for transition from L0s to L0 state. This field is set to 0b000 since the Tsi384 is not an endpoint. EXT_TAG PCIe Extended Tag Field Supported This field contains the value 0 indicating 5-bit tag fields are supported.

  • Page 207: Pcie Device Control And Status Register

    1 = Pending completion of Non-Posted Requests. AUX_PWR_DTD PCIe Aux Power Detected This field indicates whether the Tsi384 detected AUX power. The Tsi384, however, does not require the Auxiliary Power. 0 = No Aux power detected. 1 = Aux power detected.
  • Page 208 101 = 4096 bytes 110-111 = Reserved. EN_SNP_NREQ PCIe Enable Snoop Not Required The Tsi384 does not set the No Snoop attribute. This bit is hardwired to 0. AUX_PWR_PM_ PCIe Aux Power PM Enable When this bit is set the Tsi384 can draw AUX power independent of PME AUX power.
  • Page 209 Reset value MAX_PAY_SIZE PCIe Maximum Payload Size This field indicates the maximum payload size that can be used for data transmission by the Tsi384. This must be a subset of the size reported by MAX_SIZE in “PCIe Device Capabilities Register”.

  • Page 210: Pcie Link Capabilities Register

    Description Type Reset value 31:24 PORT_NUM PCIe Port Number 0x00 The Tsi384 always reports a port number of 0 for this field. 23:21 Reserved PCIe Reserved. This field always reads 0. 0x00 DLL_LNK_ACT_ Data Link Layer Link Active Reporting Capable...
  • Page 211 Note: The Tsi384 does not support CLK_PWR_MGT. This field always reads 0. 17:15 L1_EXIT PCIe L1 Exit Latency The Tsi384 does not support the L1 ASPM state. This field always returns 0. 14:12 L0S_EXIT PCIe L0s Exit Latency The Tsi384 L0s exit latency will be as 256-512ns which will be reported as 0b011.

  • Page 212: Pcie Link Control Register

    Data Link Control and Management State Machine. This bit is hardwired to 0. SLT_CLK_CONFIG Slot Clock Configuration. This bit indicates the Tsi384 uses the same physical reference clock that the platform provides on the connector. This bit can be loaded from the serial EEPROM as part of the PCB configuration information.
  • Page 213 1 = 128 bytes Reserved PCIe Reserved. It always reads 0. ASPM_CTL PCIe ASPM Control This field enables different levels of ASPM. 00: Disabled 01:L0s Entry enabled 10-11: = Reserved (not supported) Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 214: Downstream Non-Transparent Address Remapping Registers

    Reserved. 0x00 12:8 IO_SIZE This field describes how many upper bits of a downstream 0x00 I/O address are discarded. Reserved Reserved. NP_REMAPP_EN 1 = Enable non-prefetchable address remapping Reserved Reserved. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 215: Secondary Bus Non-Prefetchable Upper Base Address Remap Register

    Description Type Reset value 31:20 SEC_PRE_LBA Secondary bus prefetchable lowerbase. 0x000 19:4 Reserved Reserved. 0x0000 PRE_REMAP_EN 0 = Disable prefetchable address remapping 1 = Enable prefetchable address remapping Reserved Reserved. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 216: Secondary Bus Prefetchable Upper Base Address Remap Register

    Register name: AR_PBNPBASEUPPER Register offset: 0x0F4 Reset value: 0x0000_0000 Bits 31:24 PRI_NP_UBA 23:16 PRI_NP_UBA 15:08 PRI_NP_UBA 07:00 PRI_NP_UBA Bits Name Description Type Reset value 31:00 PRI_NP_UBA Primary bus non-prefetchable upper base. 0x0000_000 Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 217: Primary Bus Non-Prefetchable Upper Limit Remap Register

    Register name: AR_PBNPLIMITUPPER Register offset: 0x0F8 Reset value: 0x0000_0000 Bits 31:24 PRI_NP_ULA 23:16 PRI_NP_ULA 15:08 PRI_NP_ULA 07:00 PRI_NP_ULA Bits Name Description Type Reset value 31:00 PRI_NP_ULA Primary bus non-prefetchable upper Limit 0x0000_000 Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 218: Advanced Error Reporting Capability Registers

    This field is a PCI-SIG defined ID number that indicates the function and format of the extended capability. The Extended Capability ID for the Advanced Error Reporting Capability is 0x0001. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 219: Pcie Uncorrectable Error Status Register

    Completion Timeout Status R/W1CS FCPE Flow Control Protocol Error Status R/W1CS PTLP Poisoned TLP Status R/W1CS 11:5 Reserved Reserved 0x00 DLPE Data Link Protocol Error Status R/W1CS Reserved Reserved Undefined Undefined Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 220: Pcie Uncorrectable Error Mask Register

    Completion Timeout Mask R/WS FCPE Flow Control Protocol Error Mask R/WS PTLP Poisoned TLP Mask R/WS 11:5 Reserved Reserved 0x00 DLPE Data Link Protocol Error Mask R/WS Reserved Reserved Undefined Undefined Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 221: Pcie Uncorrectable Error Severity Register

    Data Link Protocol Error Severity R/WS Reserved Reserved Unused Reserved Note: Bit 0 is Training Error Status for PCIe 1.0a, but is not defined for the PCI Express Base Specification (Revision 1.1). Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 222: Pcie Correctable Error Status Register

    • TLP ended with EDB, but calculated CRC was not the logical NOT of the received CRC • Calculated CRC was not equal to the received CRC Reserved Reserved Receiver Error Status R/W1CS Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 223: Pcie Correctable Error Mask Register

    RT_TO Replay Timer Timeout Mask R/WS 11:9 Reserved Reserved RN_RO REPLAY_NUM Rollover Mask R/WS B_DLLP Bad DLLP Mask R/WS B_TLP Bad TLP Mask R/WS Reserved Reserved Receiver Error Mask R/WS Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 224: Pcie Advanced Error Capabilities And Control Register

    0x0000_00 EC_EN ECRC Check Enable R/WS 0 = Disable 1 = Enable EC_CAP ECRC Check Capable This bit indicates the Tsi384 can check ECRC. EG_EN ECRC Generation Enable R/WS 0 = Disable 1 = Enable EG_CAP ECRC Generation Capable This bit indicates the Tsi384 can generate ECRC.

  • Page 225: Pcie Header Log 1 Register

    Register name: PCIE_HL2 Register offset: 0x120 Reset value: 0x0000_0000 Bits 31:24 HEADER[95:88] 23:16 HEADER[87:80] 15:08 HEADER[79:72] 07:00 HEADER[71:64] Bits Name Description Type Reset value 31:00 HEADER[95:64] Header of TLP associated with error. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 226: Pcie Header Log 3 Register

    Register name: PCIE_HL4 Register offset: 0x128 Reset value: 0x0000_0000 Bits 31:24 HEADER[31:24] 23:16 HEADER[23:16] 15:08 HEADER[15:08] 07:00 HEADER[07:00] Bits Name Description Type Reset value 31:00 HEADER[31:00] Header of TLP associated with error. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 227: Pcie Secondary Uncorrectable Error Status Register

    Type Reset value 31:14 Reserved Reserved 0x0000_0 IB_ERR Internal Bridge Error Status (No Header Log). The Tsi384 never sets this bit. SERR_AD SERR# Assertion Detected (No Header Log) R/W1CS PERR_AD PERR# Assertion Detected R/W1CS DTDTE Delayed Transaction Discard Timer Expired Status...

  • Page 228: Pcie Secondary Uncorrectable Error Mask Register

    Unexpected Split Completion Error Mask R/WS Reserved Reserved R_MA Received Master-Abort Mask R/WS R_TA Received Target-Abort Mask R/WS MA_SC Master-Abort on Split Completion Mask R/WS TA_SC Target-Abort on Split Completion Mask R/WS Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 229: Pcie Secondary Uncorrectable Error Severity Register

    Unexpected Split Completion Error Severity R/WS Reserved Reserved R_MA Received Master-Abort Severity R/WS R_TA Received Target-Abort Severity R/WS MA_SC Master-Abort on Split Completion Severity R/WS TA_SC Target-Abort on Split Completion Severity R/WS Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 230: Pcie Secondary Error Capabilities And Control Register

    TRAN_ATT[15:08] 07:00 TRAN_ATT[07:00] Bits Name Description Type Reset value 31:00 TRAN_ATT[31:00] Transaction Attribute This field is [31:0] of the 36-bit value transferred on C/BE[3:0]# and AD[31:0] during the attribute phase. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 231: Pcie Secondary Header Log 2 Register

    This value is transferred on C/BE[3:0]# during the first address phase. TRAN_ATT[35:32] Transaction Attribute This field is [35:32] of the 36-bit value transferred on C/BE[3:0]# and AD[31:0] during the attribute phase. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 232: Pcie Secondary Header Log 3 Register

    The first address phase is logged in “PCIe Secondary Header Log 3 Register”, and the second address phase is logged in this field. In the case of a 32-bit address, this field is set to 0. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 233: Replay Latency Register

    Name Description Type Reset value 31:16 Reserved Reserved REPLAY_LAT_EN Replay Latency Enable 14:00 REPLAY_LATENCY Replay Latency timer value is overwritten by this value if 0x0000 REPLAY_LAT_EN is set to b1. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 234: Ack/Nack Update Latency Register

    UPDATE_LAT_EN is set to b1. ACKNAK_LAT_EN Ack/Nak Latency Enable 14:13 Reserved Reserved. 12:00 ACKNAK_LATENCY Ack/Nak Latency timer value is overwritten with this value if 0x0009 ACKNAK_LAT_EN is set to b1. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 235: N_Fts Register

    0x20 advertised to the other end component. Note: This value should fall in the L0s exit latency value range reported by the Tsi384. 14.10 PCIe and SerDes Control and Status Registers The following table outlines the PCIe SerDes and PCS layer registers. These registers are mainly for status reporting and testing.
  • Page 236 “PCIe Scope Control and Frequency Integrator Register” “PCIe Clock Module Control and Status Registers” 0x420 PCIE_CTL_STAT “PCIe Control and Level Status Register” 0x428 PCIE_CTL_OVRD “PCIe Control and Level Override Register” Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 237: Pcie Per-Lane Transmit And Receive Registers

    = -20*log(1-(tx_boost[3:0]+0.5)/32)dB, except that setting TX_BOOST to 0 produces 0dB of boost. This produces results up to 5.75dB in steps of ~0.37dB. Reserved Reserved Undefined Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 238: Pcie Output Status And Transmit Override Register

    TX_BOOST to 0 produces 0dB of boost. This produces results up to 5.75dB in steps of ~0.37dB. 21:3 ReservedP Preserve state on writes. Undefined Loss of signal output Undefined Reserved Reserved Undefined Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 239: Pcie Receive And Output Override Register

    Example: 3’b100 = 2.5dB boost ReservedP Preserve state on writes. RX_ALIGN_EN Enable Word Alignment 0 = Alignment (framer) disabled 1 = Alignment enabled ReservedP Preserve state on writes. HALF_RATE Digital half-rate data control Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 240: Pcie Debug And Pattern Generator Control Register

    2 = lfsr7 (x 3 = Fixed word (PAT0) 4 = DC balanced word (PAT0, ~PAT0) 5 = Fixed pattern: (000, PAT0, 3ff, ~PAT0) 6–7 = Reserved 15:0 Reserved Reserved Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 241: Pcie Pattern Matcher Control And Error Register

    Read operation on this register is pipelined. Two reads may be needed to get “current” value. The value is volatile; that is, the value may change at any time.The second read resets the counter. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 242: Pcie Ss Phase And Error Counter Control Register

    Read operation on this register is pipelined. Two reads may be needed to get “current” value. The value is volatile; that is, the value may change at any time.The second read resets the counter. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 243: Pcie Scope Control And Frequency Integrator Register

    Note: This field may require two “reads” to get a stable value. DTHR_F Bits below the useful resolution. Note: This bit may require two “reads” to get a stable value. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 244: 14.10.10 Pcie Clock Module Control And Status Registers

    1Vp-p). For more information on available settings, see Table 25:21 LOS_LVL Loss of Signal Detector level. 0x12 20:16 ACJT_LVL AC JTAG Comparator level. 0x00 15:0 Reserved Reserved Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 245: Pcie Control And Level Override Register

    Preserve state on writes. Undefined Table 44: TX_LVL Values TX_LVL Value TX_LVL[0:4] Vdiff-pp (mV) 0x00 5'b00000 929.8 0x01 5'b00001 939.4 0x02 5'b00010 949.1 0x03 5'b00011 958.8 0x04 5'b00100 968.5 0x05 5'b00101 978.2 Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 246: Table 44: Tx_Lvl Values

    0x16 5'b10110 1142.8 0x17 5'b10111 1152.5 0x18 5'b11000 1162.2 0x19 5'b11001 1171.9 0x1A 5'b11010 1181.6 0x1B 5'b11011 1191.3 0x1C 5'b11100 1200.9 0x1D 5'b11101 1210.6 0x1E 5'b11110 1220.3 0x1F 5'b11111 1230.0 Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 247: Electrical Characteristics

    3.3V DC PCIe analog supply voltage -0.5 DDA_PCIE Minimum signal input voltage -0.5 Maximum signal input voltage + 0.5 a. The V reference is dependent on the input pad supply rail. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 248: Recommended Operating Conditions

    Power Supply Ripple for Voltage ripple1 Supplies: V and V DD_PCI Power Supply Ripple for Voltage ripple2 Supplies: V DD_PCIE DDA_PCIE DDA_PLL Ambient temperature Junction temperature JUNC Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 249: Power Characteristics

    Total chip power 1.15 1.73 TOTAL a. All PCIe lanes are active for power and current measurements. 15.4 Power Supply Sequencing The Tsi384 does not have any power sequencing constraints. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 250: Dc Operating Characteristics

    PCI_CLK Input Pin Inductance IN_PCI Clock Pin Inductance CLK_PCI PCI_CLK 15.6 AC Timing Specifications This section discusses AC timing specifications for the Tsi384. 15.6.1 PCI/X Interface AC Signal Timing Table 50: PCI/X Clock (PCI_CLK) Specification PCI-X Symbol Parameter Units Notes...

  • Page 251: Table 51: Ac Specifications For Pci/X Interface

    Input Setup to clock for c, d point-to-point signals Input Hold time from clock Reset Active Time Reset Active to output float delay P[x]_REQ64_B to Reset clocks setup time Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 252: Pcie Differential Transmitter Output Specification

    Setup time applies only when the device is not driving the pin. g. All output drivers must be floated when PCIE_PERSTn is active. h. The Tsi384 acts as the central resource and will drive REQ64 low during reset since it is a 64-bit bridge. 15.6.2 PCIe Differential Transmitter Output Specification The following table lists the specification of parameters for the differential output of the PCIe lanes.
  • Page 253 Receiver Receiver Detection is present. See Section 4.3.1.8 of the PCI Express Base Specification (Revision 1.1). Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 254 This random timeout helps resolve conflicts in crosslink configuration by Timeout eventually resulting in only one Downstream and one Upstream Port. See Section 4.2.6.3 of the PCI Express Base Specification (Revision 1.1). Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...
  • Page 255 100 Ohms. Small signal resistance is measured by forcing a small change in differential voltage and dividing this by the corresponding change in current. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 256: Figure 41: Transmitter Eye Voltage And Timing Diagram

    15. Electrical Characteristics Figure 41: Transmitter Eye Voltage and Timing Diagram 1. This diagram is an excerpt from PCI Express Base Specification (Revision 1.1), Revision 1.1, “Transmitter Compliance Eye Diagrams,” page 225. Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 257: Pcie Differential Receiver Input Specifications

    See Notes 8 and 12. Powered Down DC 200K Ohms Required RX D+ as well as D- DC RX-HIGH-IMP-DC impedance when the Receiver Input Impedance terminations do not have power. See Note 13. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 258 13. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that the Receiver Detect circuit does not falsely assume a Receiver is powered on when it is not. This term must be measured at 200mV above the RX ground. Tsi384 User Manual Integrated Device Technology May 5, 2014...

  • Page 259: Figure 42: Minimum Receiver Eye Timing And Voltage Compliance Specification

    Figure 42: Minimum Receiver Eye Timing and Voltage Compliance Specification 1. This diagram is an excerpt from PCI Express Base Specification, Revision 1.1, “Differential Receiver (RX) Input Specifications,” page 230. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 260: Reference Clock

    15. Electrical Characteristics 15.6.4 Reference Clock The following table lists the Tsi384’s electrical characteristics for the differential SerDes reference clock input (PCIE_REFCLK_n/p). Table 54: Reference Clock (PCIE_REFCLK_n/p) Electrical Characteristics Symbol Parameter Min. Typ. Max. Unit Notes Input Voltage Swing Differential Input Voltage...

  • Page 261: Boundary Scan Test Signal Timing

    15. Electrical Characteristics 15.6.5 Boundary Scan Test Signal Timing The following table lists the test signal timings for the Tsi384. Table 55: Boundary Scan Test Signal Timings Symbol Parameter Units Notes JT_TCK Frequency JT_TCK High Time Measured at BSCH 1.5V,...

  • Page 262: Ac Timing Waveforms

    Power-up strapping hold from de-assertion of device reset Assertion of reset to outputs tri-state 15.7 AC Timing Waveforms This section contains AC timing waveforms for the Tsi384. Figure 44: Input Timing Measurement Waveforms test INPUT Valid test test...

  • Page 263: Figure 45: Output Timing Measurement Waveforms

    Figure 46: PCI/X T Rising Edge AC Test Load OV (max) Test Point Output 25 10pF Figure 47: PCI/X T Falling Edge AC Test Load OV (max) CC33 Test 25 Point Output 10pF Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 264: Figure 48: Pci/X Tov (Min) Ac Test Load

    15. Electrical Characteristics Figure 48: PCI/X T AC Test Load OV (min) CC33 Test 1K Point Output 1K 10pF Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 265: Packaging

    2. Dimensionning and tolerencing per ASME Y14.5-1994. 3. Dimension is measured at the maximum solder ball diameter, paralllel to Datum C. 4. Datum C is defined by the sperical crowns of the solder balls. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...

  • Page 266: Thermal Characteristics

    Failure mechanisms and failure rate of a device has an exponential dependence on the silicon operating temperatures. Therefore, the control of the package, and by extension the Junction temperature, is essential to ensure product reliability. The Tsi384 is specified safe for operation when the Junction temperature is within the recommended limits as shown in Table ...

  • Page 267: Moisture Sensitivity

    16. Packaging Example of Thermal Data Usage  Based on above data and specified conditions, the Junction temperature of the Tsi384 with a 0 m/s airflow can be determined using the following formula:  P + T JA * Where: •...
  • Page 268 16. Packaging Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 269: Ordering Information

    Tsi NNN(N) - SS(S) E P G (Z#) • ( ) – Indicates optional characters. • Tsi – IDT system interconnect product identifier. • NNNN – Product number (may be three or four digits). • SS(S) – Maximum operating frequency or data transfer rate of the fastest interface. For operating frequency numbers, M and G represent MHz and GHz.
  • Page 270 — Q - Plastic quad flatpack (QFP) • G – IDT products fit into three RoHS-compliance categories: — Y - RoHS Compliant (6of6) – These products contain none of the six restricted substances above the limits set in the EU Directive 2002/95/EC.

  • Page 271: Pcie Programmable Transmit And Receive Equalization

    The Tsi384’s programmable drive strength and transmit boost accommodates for electrical characteristics that can degrade the signal quality of a link connected to the Tsi384. Decreasing the drive strength of signals also provides the ability to reduce the power consumption of its PCIe port.

  • Page 272: Receive Equalization

    For example, setting RX_EQ_VAL[2:0] = 3’b100 results in a 2.5dB boost of the received signal. This boost is internal to the device and increases the eye opening when the signals arriving at the pins are degraded. Tsi384 User Manual Integrated Device Technology May 5, 2014...

  • Page 273: Glossary

    Fairness algorithm Arbitration logic that helps low and high priority devices gain fair access to a peripheral bus. This logic also helps prevent deadlocks among bus-mastering devices in a system. Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 274 — such as configuration, memory, and I/O — to other devices in the PCIe hierarchy. It also handles interrupts and power management events. The root complex appears as P2P bridge(s) to the PCIe links, and can support one or more PCIe ports. Tsi384 User Manual Integrated Device Technology May 5, 2014...
  • Page 275 This enables devices that are connected to multiple bridging devices to share a single, unified address space. Upstream port A PCIe port that points in the direction of the root complex (for example, an endpoint port). Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 276 Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...

  • Page 277: Index

    D state transitions L0 state D0 state L1 state D3cold state L2/L3 ready D3hot state L3 state DC and operating characteristics LDn state device power states LOs state device register map Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 278 Undefined power supply sequencing unexpected completion error prefetchable memory addressing unsupported request completion status errors prefetching algorithm upstream Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...
  • Page 279 Index data path non-transparent registers VGA addressing warm reset Integrated Device Technology Tsi384 User Manual www.idt.com May 5, 2014...
  • Page 280 Index Tsi384 User Manual Integrated Device Technology May 5, 2014 www.idt.com...
  • Page 281 Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.

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