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IDT Tsi350A User Manual

Pci-to-pci bridge
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Tsi350A
PCI-to-PCI Bridge
™
User Manual
80D5000_MA001_08
September 5, 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.

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Summary of Contents for IDT Tsi350A

  • Page 1 ® Tsi350A PCI-to-PCI Bridge ™ User Manual 80D5000_MA001_08 September 5, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Document

    “Revision History” on page 4 Scope The Tsi350A PCI-to-PCI Bridge User Manual discusses the features, capabilities, and configuration requirements for the Tsi350A. It is intended for hardware and software engineers who are designing system interconnect applications with the device. Document Conventions This document uses the following conventions.

  • Page 4: Revision History

    VSS. 80D5000_MA001_06, Formal, January 2008 This document supported the production version of the Tsi350A. The Tsi350A is a performance enhancement of the Tsi350 and there are no functional changes between the devices. All technical information in this document applies to both the Tsi350 and the Tsi350A.
  • Page 5 80D5000_MA001_04, Formal, March 2007 The following chapters were extensively edited: • “Signals and Pinout” on page 93 • “Electrical Characteristics” on page 119 • “Package Information” on page 169 Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...
  • Page 6 About this Document Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 7: Table Of Contents

    Type 0 Access to Tsi350A ........
  • Page 8 Data Parity Errors ............... . . 62 5.3.1 Configuration Write Transactions to Tsi350A Configuration Space......62 5.3.2 Read Transactions .
  • Page 9 256-pin PBGA Pin List ............112 Integrated Device Technology Tsi350A User Manual www.idt.com...
  • Page 10 Read Transaction Control Register— Offset 0x44 ........155 Tsi350A User Manual...
  • Page 11 Ordering Information ..............177 Integrated Device Technology Tsi350A User Manual www.idt.com...
  • Page 12 Contents Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...
  • Page 13 Tsi350A Downstream Data Path ........
  • Page 14 Figures Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...
  • Page 15 Tsi350A Response to Delayed Read Target Termination ........
  • Page 16 Tables Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 17: Functional Overview

    The Tsi350A allows the two PCI buses to operate concurrently. This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may increase system performance in applications such as multimedia.

  • Page 18: Figure 1: Block Diagram

    Bus Arbiter 80D5000_BK001_02 Option card designers can use Tsi350A to implement multiple-device PCI option cards. Without a PCI-to- PCI bridge, PCI loading rules would limit option cards to one device. The PCI Local Bus Specification loading rules limit PCI option cards to a single connection per PCI signal in the option card connector.

  • Page 19: Features

    1. Functional Overview > Overview of the Tsi350A Figure 2: System Block Diagram Device Device Device Device Tsi350A Device Device 80D5000_TA001_02 PCI Bus 1.1.1 Features • Industry-standard 32-bit, 66-MHz PCI bridge • Fully PCI Local Bus Specification, Revision 2.3 compliant •...

  • Page 20: Compliance

    (4 bytes) to 32 memory locations (128 bytes) as needed. Tsi350A will start giving data on originating bus once the first four locations of the buffer are filled or the transaction is completed on the target bus.

  • Page 21: Jtag Controller

    1.2.3 Hot Swap Interface Tsi350A is designed with an interface for Hot Swap support. This allows the user to insert or extract the bridge card without powering down the system. During insertion and extraction process, the bridge indicates to system software about the Hot Swap event by driving HS_ENUM_b. It also provides a visual indication to the user through the HS_LED signal.

  • Page 22: Architecture

    To prevent deadlocks and to maintain data coherency, a set of ordering rules is imposed on the forwarding of posted and delayed transactions across Tsi350A. The queue structure, along with the order in which the transactions in the queues are initiated and completed, supports these ordering requirements.

  • Page 23: Posted Write Queue

    1. Functional Overview > Data Path Figure 3: Tsi350A Downstream Data Path 1.4.1 Posted Write Queue The posted write queue contains the address and data of memory write transactions targeted for the opposite interface. The posted write transaction can consist of an arbitrary number of data phases, subject to the amount of space in the queue and disconnect boundaries.

  • Page 24: Read Data Queue

    Read data for up to four transactions, subject to the burst size of the read transactions and available queue space, can be stored. The read data queue for Tsi350A consists of 128 bytes in each direction. Tsi350A User Manual...

  • Page 25: Pci Interface

    Tsi350A support for each transaction when Tsi350A initiates transactions as a master, on the primary bus and on the secondary bus, and when Tsi350A responds to transactions as a target, on the primary bus and on the secondary bus.

  • Page 26: Table 1: Tsi350A Pci Transactions

    2. PCI Interface > Transaction Types • Tsi350A does not generate Type 0 configuration transactions on the primary interface, nor does it respond to Type 0 configuration transactions on the secondary PCI interface. The PCI-to-PCI Bridge Architecture Specification does not support configuration from the secondary bus.

  • Page 27: Transaction Phases

    A 32-bit address uses a single address phase. This address is driven on AD[31:0], and the bus command is driven on C/BE_b[3:0]. Tsi350A supports the linear increment address mode only, which is indicated when the lower two address bits are equal to 0. If either of the lower two address bits is nonzero, Tsi350A automatically disconnects the transaction after the first data transfer.

  • Page 28: Data Phase

    8 Dwords of data. This enables Tsi350A to accept write data without obtaining access to the target bus. Tsi350A can accept one Dword of write data every PCI clock cycle; that is, no target wait states are inserted. This write data is stored in internal posted write buffers and is subsequently delivered to the target.

  • Page 29: Memory Write And Invalidate Transactions

    If the value in the cache line size register does meet the memory write and invalidate conditions, that is, the value is a nonzero power of 2 less than or equal to 16 Dwords, Tsi350A returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. For a cache line size of 16 Dwords, Tsi350A disconnects a memory write and invalidate transaction on every cache line boundary.

  • Page 30: Delayed Write Transactions

    If the initiator repeats the write transaction before the data has been transferred to the target, Tsi350A returns a target retry to the initiator. Tsi350A continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, Tsi350A does not make a new entry into the delayed transaction queue.

  • Page 31: Write Transaction Address Boundaries

    Buffering Multiple Write Transactions Tsi350A continues to accept posted memory write transactions as long as space for at least 1 Dword of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, Tsi350A returns a target disconnect to the initiator.

  • Page 32: Read Transactions

    2. PCI Interface > Read Transactions Read Transactions Delayed read forwarding is used for all read transactions crossing Tsi350A.Delayed read transactions are treated as either prefetchable or non-prefetchable. Prefetching is a useful technique for hiding the latency of a burst read transaction but its use is restricted.

  • Page 33: Calculating The Prefetch Count

    A target disconnects the ongoing transaction The following rules are true when determining the prefetch count behaviour of the Tsi350A: • If the maximum prefetch count is programmed less than Cache Line Size, the Tsi350A prefetches data up to first cache line boundary. •...

  • Page 34: Prefetchable Read Transactions

    The amount of data that is prefetched depends on the type of transaction. The amount of prefetching may also be affected by the amount of free buffer space available in the Tsi350A, and by any read address boundaries encountered.

  • Page 35: Delayed Read Requests

    0 for all remaining data phases. If Tsi350A receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered.
  • Page 36 For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. Tsi350A can accept 1 Dword of read data each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred during a...

  • Page 37: Configuration Transactions

    Configuration Transactions Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All Tsi350A registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, Tsi350A also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation.

  • Page 38: Type 0 Access To Tsi350A

    PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. Tsi350A performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. Tsi350A must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it.

  • Page 39: Table 5: Device Number To Idsel S_Ad Pin Mapping

    Leaves unchanged the function number and register number fields. • Tsi350A asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device...
  • Page 40 2. PCI Interface > Configuration Transactions Tsi350A can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary.

  • Page 41: Type 1 To Type 1 Forwarding

    Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When Tsi350A detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, Tsi350A forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge.

  • Page 42: Transaction Termination

    The bus command on C/BE_b is a configuration write command. When Tsi350A initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and decode only the bus command.

  • Page 43: Master Termination Initiated By Tsi350A

    When a master abort is received in response to a posted write transaction, Tsi350A discards the posted write data and makes no more attempts to deliver the data. Tsi350A sets the received master abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface.

  • Page 44: Target Termination Received By Tsi350A

    2. PCI Interface > Transaction Termination 2.6.3 Target Termination Received by Tsi350A When Tsi350A initiates a transaction on the target bus and the target responds with DEVSEL_b, the target can end the transaction with one of the following types of termination: •...

  • Page 45: Table 7: Tsi350A Response To Posted Write Termination

    2. PCI Interface > Transaction Termination 2.6.3.2 Posted Write Target Termination Response When Tsi350A initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 7 shows Tsi350A response to each type of target termination that occurs during a posted write transaction.

  • Page 46: Target Termination Initiated By Tsi350A

    2.6.4.1 Target Retry Tsi350A returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. Tsi350A returns a target retry to an initiator when any of the following...
  • Page 47 The delayed transaction queue is full, and the transaction cannot be queued. • A transaction with the same address and command has been queued. • A locked sequence is being propagated across Tsi350A, and the write transaction is not a locked transaction. Target retry for delayed read transactions: •...
  • Page 48 2. PCI Interface > Transaction Termination • Tsi350A is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 2 attempts. When Tsi350A returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.

  • Page 49: Address Decoding

    PCI bus. Transactions falling outside these ranges are forwarded upstream from the secondary PCI bus to the primary PCI bus. Tsi350A uses a flat address space; that is, it does not perform any address translations. The address space has no “gaps”—addresses that are not marked for downstream forwarding are always forwarded upstream.

  • Page 50: Base And Limit Address Registers

    To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master enable bit is not set, Tsi350A ignores all I/O and memory transactions initiated on the secondary bus. Setting the master enable bit also allows upstream forwarding of memory transactions.

  • Page 51: Isa Mode

    When the ISA enable bit is set, devices downstream of Tsi350A can have I/O space mapped into the first 256 bytes of each 1 kB chunk below the 64 kB boundary, or anywhere in I/O space above the 64 kB boundary.

  • Page 52: Memory-Mapped I/O Base And Limit Address Registers

    Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. Tsi350A prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer.

  • Page 53: Prefetchable Memory Base And Limit Address Registers

    Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. Tsi350A prefetches for all types of memory read commands in this address space.

  • Page 54: Prefetchable Memory 64-Bit Addressing Registers

    If the prefetchable memory space on the secondary interface resides entirely in the first 4 GB of memory, both upper 32 bits registers must be set to 0. Tsi350A ignores all dual address cycle transactions initiated on the primary interface and forwards all dual address transactions initiated on the secondary interface upstream.

  • Page 55: Vga Support

    32 bits register and the prefetchable memory limit address upper 32 bits register must be initialized to nonzero values. Tsi350A ignores all single address memory transactions initiated on the primary interface and forwards all single address memory transactions initiated on the secondary interface upstream (unless they fall within the memory-mapped I/O or VGA memory range).

  • Page 56: Vga Snoop Mode

    0, which means that these addresses are aliased every 1 kB throughout the first 64 kB of I/O space. If both the VGA mode bit and the VGA snoop bit are set, Tsi350A behaves in the same way as if only the VGA mode bit were set...

  • Page 57: Transaction Ordering

    “General Ordering Guidelines” on page 58 Overview of Transaction Ordering To maintain data coherency and consistency, Tsi350A complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.3, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across Tsi350A. For a more detailed discussion of transaction ordering, see Appendix E of the PCI Local Bus Specification, Revision 2.3.

  • Page 58: General Ordering Guidelines

    Delayed read completion transactions have been completed on the target bus, and the read data has been queued in Tsi350A read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request;...

  • Page 59: Ordering Rules

    These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing Tsi350A in the same direction. Note that delayed completion transactions cross Tsi350A in the direction opposite that of the corresponding delayed requests.
  • Page 60 In this case, the read data is traveling in the same direction as the write data and the initiator of the read transaction is on the same side of Tsi350A as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator.

  • Page 61: Error Handling

    Address Parity Errors Tsi350A checks address parity for all transactions on both buses, for all address and all bus commands. When Tsi350A detects an address parity error on the primary interface, the following events occur: •...

  • Page 62: Data Parity Errors

    Tsi350A also asserts P_PERR_b. • If the parity error response bit is not set, Tsi350A does not assert P_PERR_b. Tsi350A sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. 5.3.2...

  • Page 63: Delayed Write Transactions

    • Tsi350A forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is prefetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator.
  • Page 64 • Tsi350A captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when Tsi350A is delivering data to the target on the primary bus and P_PERR_b is asserted by the target, the following events occur: •...

  • Page 65: Posted Write Transactions

    • Tsi350A asserts P_SERR_b and sets the signaled system error bit in the status register, if all of the following conditions are met: — The SERR_b enable bit is set in the command register.

  • Page 66: System Error (Serr_B) Reporting

    In compliance with the PCI-to-PCI Bridge Architecture Specification, Tsi350A asserts P_SERR_b when it detects the secondary SERR_b input, S_SERR_b, asserted and the SERR_b forward enable bit is set in the bridge control register. In addition, Tsi350A also sets the received system error bit in the secondary status register.
  • Page 67 • Master time-out on delayed transaction. The device-specific P_SERR_b status register reports the reason for Tsi350A’s assertion of P_SERR_b. Most of these events have additional device-specific disable bits in the P_SERR_b event disable register that make it possible to mask out P_SERR_b assertion for specific events. The master time-out condition has a SERR_b enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.
  • Page 68 5. Error Handling > System Error (SERR_b) Reporting Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 69: Exclusive Access

    When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target’s bus. When Tsi350A detects, on the primary bus, an initial locked transaction intended for a target on the secondary bus, Tsi350A samples the address, transaction type, byte enable bits, and parity.

  • Page 70: Ending Exclusive Access

    When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, Tsi350A transfers the read data back to the initiator, and the lock is then also established on the primary bus.
  • Page 71 When the last locked transaction is a delayed transaction, Tsi350A has already completed the transaction on the secondary bus. In this case, as soon as Tsi350A detects that the initiator has relinquished the P_LOCK_b signal by sampling it in the de-asserted state while P_FRAME_b is de-asserted, Tsi350A de-asserts the S_LOCK_b signal on the secondary bus as soon as possible.
  • Page 72 6. Exclusive Access > Ending Exclusive Access Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 73: Pci Bus Arbitration

    When P_GNT_b is asserted low by the primary bus arbiter after Tsi350A has asserted P_REQ_b, Tsi350A initiates a transaction on the primary bus during the next PCI clock cycle. If P_GNT_b is asserted to the Tsi350A and the Tsi350A's P_REQ_b is not asserted, the Tsi350A parks P_AD, P_CBE_b, and P_PAR by driving them to valid logic levels.

  • Page 74: Secondary Pci Bus Arbitration

    Each bus master, including Tsi350A, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter control register in device-specific configuration space.

  • Page 75: Secondary Bus Arbitration Using An External Arbiter

    PCI bus is idle. When P_GNT_b is de-asserted, Tsi350A tristates the P_AD, P_CBE_b, and P_PAR signals on the next PCI clock cycle. If Tsi350A is parking the primary PCI bus and wants to initiate a transaction on that bus, then Tsi350A can start the transaction on the next PCI clock cycle by asserting P_FRAME_b if P_GNT_b is still asserted.
  • Page 76 7. PCI Bus Arbitration > Bus Parking Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 77: General Purpose I/O

    • A live insertion bit can be used, along with the GPIO[3] pin, to bring Tsi350A gracefully to a halt through hardware, permitting live insertion of option cards behind Tsi350A. GPIO Control Registers...

  • Page 78: Secondary Clock Control

    The reset value for the output is zero. Secondary Clock Control Tsi350A uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs.

  • Page 79: Figure 6: Clock Mask Load And Shift Timing

    After the shift operation is complete, Tsi350A tristates the GPIO signals and can de-assert S_RST_b if the secondary reset bit is clear. Tsi350A then ignores MSK_IN. Control of the GPIO signal now reverts to Tsi350A GPIO control registers. The clock disable mask can be modified subsequently through a configuration write command to the secondary clock control register in device-specific configuration space.

  • Page 80: Live Insertion

    0. This means that, as a target, Tsi350A no longer accepts any I/O or memory transactions, on either interface. When read, the register bits still reflect the value originally written by a configuration write command; when GPIO[3] is de-asserted, the internal enable bits return to their original value (as they appear when read from the command register).

  • Page 81: Table 11: Tsi350A Hot-Swap Mode Selection

    Hot-swap terminals: HS_ENUM_b, HS_SWITCH_b, and HS_LED, cPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running system. The Tsi350A provides this functionality such that it can be implemented on a board that can be removed and inserted in a hot-swap system.
  • Page 82 8. General Purpose I/O > CompactPCI Hot-swap Support Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 83: Clocks

    P_CLK, and the secondary interface is synchronized to the secondary clock input, S_CLK. Primary and Secondary Clock Inputs Tsi350A operates between 0 MHz to 66 MHz on both interfaces. P_CLK and S_CLK can be synchronous or asynchronous in phase and frequency. 9.2.1...

  • Page 84: Secondary Clock Outputs

    9. Clocks > Secondary Clock Outputs Secondary Clock Outputs Tsi350A has 10 secondary clock outputs, S_CLK_O[9:0], that can be used as clock inputs for up to nine external secondary bus devices and for Tsi350A secondary clock input. The S_CLK_O outputs are derived from P_CLK (that is they are synchronous to the primary clock).

  • Page 85: Pci Power Management

    Support of the B2 secondary bus power state when in the D3hot power management state. Table 13 shows the states and related actions that Tsi350A performs during power management transitions. (No other transactions are permitted.) Table 13: Power Management Transitions...
  • Page 86 10. PCI Power Management > PME_b signals are routed from downstream devices around PCI-to-PCI bridges. PME_b signals do not pass through PCI-to-PCI bridges. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 87: Reset

    Programming bit 0, Chip Reset, in the Diagnostic Control register (41h) - Software can program this bit to '1' to assert S_RST_b on the secondary interface. The Tsi350A de-asserts S_RST_b automatically after 100 us and clears the bit to '0', provided the secondary reset bit is cleared in the “Bridge Control Register—Offset 0x3C”...

  • Page 88: Chip Reset

    Chip Reset The chip reset bit in the diagnostic control register can be used to reset Tsi350A and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. In addition, S_RST_b is asserted, and the secondary reset bit is automatically set.

  • Page 89: Jtag Module

    This chapter describes Tsi350A’s implementation of a joint test action group (JTAG) test port according to IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. Tsi350A contains a serial-scan test port that conforms to IEEE standard 1149.1. The JTAG test port consists of the following: •...

  • Page 90: Test Access Port (Tap) Controller

    The bypass register is a 1-bit shift register that provides a means for effectively bypassing the JTAG test logic through a single-bit serial connection through the chip from TDI to TDO. At board level testing, this helps reduce overall length of the scan ring. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08...

  • Page 91: Boundary-Scan Register

    The TAP controller leaves this state only when an appropriate JTAG test operation sequence is sent on the TMS and TCK pins. For Tsi350A to operate properly, the JTAG logic must be reset. JTAG can be reset in the following ways: If the JTAG logic is not being used, TRST_b must be tied to GND with a 100ohm resistor.
  • Page 92 12. JTAG Module > Initialization Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 93: Signals And Pinout

    “Pinout” on page 104 13.1 Overview of Signals and Pinout This chapter provides detailed descriptions of Tsi350A signal pins, grouped by function. Table 16 describes the signal pin functional groups, and the following sections describe the signals in each group.

  • Page 94: Table 17: Tsi350A Signal Types

    13. Signals and Pinout > Table 17 defines the signal type abbreviations used in the signal tables. Table 17: Tsi350A Signal Types Signal Type Description Standard input only. Standard output only. Tristate bi-directional. Sustained tristate. Active low signal must be pulled high for one cycle when de-asserting.

  • Page 95: Signals

    This bi-directional signal indicates the even parity of address P_AD[31:0] and command bits P_CBE[3:0]_b for an address phase or even parity of data and byte enables for a data phase of a PCI cycle. The PAR signal will be driven by Tsi350A, when it drives address or data on the AD bus.
  • Page 96 This input signal when high indicates that the current transaction is a locked transaction. P_IDSEL Primary Bus: IDSEL_b. Signal P_IDSEL is used as the chip select line for Type 0 configuration accesses to Tsi350A configuration space. When P_IDSEL is asserted during the address phase of a Type 0 configuration transaction, the Tsi350A responds to the transaction by asserting P_DEVSEL_b.

  • Page 97: Secondary Pci Bus Interface Signals

    S_CBE[3:0]_b for an address phase or even parity of data and byte enables for a data phase of a PCI cycle. Parity is always valid for the transfer that occurred the previous clock cycle. The PAR signal will be driven by Tsi350A, when it drives address or data on the AD bus. S_FRAME_b Secondary Bus: FRAME This bi-directional active low signal indicates the start of a PCI transaction.
  • Page 98 This bi-directional signal when high indicates that the current transaction on the Secondary Bus is a locked transaction. S_LOCK_b is de-asserted during the first address phase of a transaction and is asserted one clock cycle later by Tsi350A when it is propagating a locked transaction downstream.

  • Page 99: Secondary Bus Arbitration Signals

    S_GNT_b[8:0] Secondary Bus: Grant These are active low grant outputs from the Tsi350A to the devices on the Secondary Bus. Each grant line is connected to a device on the Secondary Bus. The S_GNT lines are asserted by the internal arbiter based on the priority. The grant line when active signals the device to take the ownership of the bus after the completion of current transaction on the bus.

  • Page 100: Clock Signals

    P_CLK. The secondary clocks are either same frequency as P_CLK or half the frequency as the primary input. The Tsi350A generates a divide by 2 clock when the S_M66EN pin is tied low and the P_M66EN input is high. The secondary output clocks can be disabled through the MSK_IN input during reset or by writing to the clock control register.

  • Page 101: Reset Signals

    Configure 66 MHz operation This input only pin is used to specify if Tsi350A is capable of running at 66 MHz. If the pin is tied high, then the device can be run at 66 MHz. If the pin is tied low, then Tsi350A can only function under the 33 MHz PCI specification.
  • Page 102 BPCCE Bus/power clock control management pin When signal BPCCE is tied high, and when Tsi350A is placed in the D3hot power state, it enables Tsi350A to place the secondary bus in the B2 power state. Tsi350A disables the secondary clocks and drives them to 0. When tied low, placing Tsi350A in the D3 hot power state has no effect on the secondary bus clocks.

  • Page 103: Jtag Signals

    JTAG serial data out Signal TDO is the serial output through which test instructions and data from the test logic leave the Tsi350A. This is a tri-state signal, enabled from the Test Access Port (TAP) controller. JTAG test mode select Signal TMS causes state transitions in the test TAP controller.

  • Page 104: Pinout

    13. Signals and Pinout > Pinout 13.3 Pinout 13.3.1 208-pin PQFP Pin List Table 26: Tsi350A 208 Pin List Signal Name S_REQ_b[1] S_REQ_b[2] S_REQ_b[3] S_REQ_b[4] S_REQ_b[5] S_REQ_b[6] S_REQ_b[7] S_REQ_b[8] S_GNT_b[0] S_GNT_b[1] S_GNT_b[2] S_GNT_b[3] S_GNT_b[4] S_GNT_b[5] S_GNT_b[6] S_GNT_b[7] S_GNT_b[8] S_CLK S_RST_b...
  • Page 105 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name GPIO[1] GPIO[0] S_CLK_O[0] S_CLK_O[1] S_CLK_O[2] S_CLK_O[3] S_CLK_O[4] S_CLK_O[5] S_CLK_O[6] S_CLK_O[7] S_CLK_O[8] S_CLK_O[9] P_RST_b BPCCE P_CLK P_GNT_b P_REQ_b P_AD[31] P_AD[30] Integrated Device Technology Tsi350A User Manual www.idt.com...
  • Page 106 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name P_AD[29] P_AD[28] P_AD[27] P_AD[26] P_AD[25] P_AD[24] P_CBE_b[3] P_IDSEL P_AD[23] P_AD[22] P_AD[21] P_AD[20] P_AD[19] P_AD[18] P_AD[17] P_AD[16] P_CBE_b[2] Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...
  • Page 107 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name P_FRAME_b P_IRDY_b P_TRDY_b P_DEVSEL_b P_STOP_b P_LOCK_b P_PERR_b P_SERR_b P_PAR P_CBE_b[1] P_AD[15] P_AD[14] P_AD[13] P_AD[12] P_AD[11] P_AD[10] P_M66EN Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...
  • Page 108 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name P_AD[9] P_AD[8] P_CBE_b[0] P_AD[7] P_AD[6] P_AD[5] P_AD[4] P_AD[3] P_AD[2] P_AD[1] P_AD[0] P_VIO CONFIG66 MSK_IN HS_ENUM_b HS_LED Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...
  • Page 109 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name TRST_b S_VIO S_AD[0] S_AD[1] S_AD[2] S_AD[3] S_AD[4] S_AD[5] S_AD[6] S_AD[7] S_CBE_b[0] S_AD[8] S_AD[9] S_M66EN S_AD[10] S_AD[11] Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...
  • Page 110 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name S_AD[12] S_AD[13] S_AD[14] S_AD[15] S_CBE_b[1] S_PAR S_SERR_b S_PERR_b S_LOCK_b S_STOP_b S_DEVSEL_b S_TRDY_b S_IRDY_b S_FRAME_b S_CBE_b[2] S_AD[16] S_AD[17] S_AD[18] S_AD[19] Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08...
  • Page 111 13. Signals and Pinout > Pinout Table 26: Tsi350A 208 Pin List Signal Name S_AD[20] S_AD[21] S_AD[22] S_AD[23] S_CBE_b[3] S_AD[24] S_AD[25] S_AD[26] S_AD[27] S_AD[28] S_AD[29] S_AD[30] S_AD[31] S_REQ_b[0] Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 112: 256-Pin Pbga Pin List

    13. Signals and Pinout > Pinout 13.3.2 256-pin PBGA Pin List Table 27: Tsi350A 256 Pin List Signal Name S_REQ_b[2] S_AD[31] S_AD[28] S_AD[25] S_AD[22] S_AD[19] S_AD[17] S_FRAME_b S_DEVSEL_b S_PERR_b S_PAR S_AD[13] S_AD[11] S_REQ_b[1] S_REQ_b[0] S_AD[27] S_CBE_b[3] S_AD[21] S_AD[18] S_CBE_b[2] S_IRDY_b...
  • Page 113 13. Signals and Pinout > Pinout Table 27: Tsi350A 256 Pin List Signal Name S_REQ_b[5] S_REQ_b[4] S_AD[29] S_AD[24] S_AD[23] S_AD[20] S_AD[16] S_TRDY_b S_LOCK_b S_AD[15] S_AD[8] S_GNT_b[0] S_REQ_b[6] S_REQ_b[3] S_AD[30] S_AD[26] S_SERR_b S_AD[14] S_M66EN S_AD[6] S_GNT_b[3] S_GNT_b[2] S_REQ_b[7] S_REQ_b[8] S_AD[9] S_AD[7]...
  • Page 114 13. Signals and Pinout > Pinout Table 27: Tsi350A 256 Pin List Signal Name S_AD[4] S_GNT_b[7] S_GNT_b[6] S_GNT_b[1] S_GNT_b[4] S_AD[5] S_AD[3] S_AD[2] S_AD[1] S_GNT_b[8] S_GNT_b[5] S_VIO TRST_b S_AD[0] S_RST_b S_CFN_b S_CLKI GPIO[1] GPIO[2] GPIO[3] GPIO[0] S_CLK_O[0] S_CLK_O[1] Tsi350A User Manual...
  • Page 115 13. Signals and Pinout > Pinout Table 27: Tsi350A 256 Pin List Signal Name P_VIO MSK_IN CONFIG66 S_CLK_O[2] S_CLK_O[3] S_CLK_O[5] S_CLK_O[6] P_AD[4] P_AD[2] P_AD[1] P_AD[0] S_CLK_O[4] S_CLK_O[8] S_CLK_O[9] P_CLK P_AD[6] P_AD[7] P_AD[5] P_AD[3] S_CLK_O[7] BPCCE P_AD[31] P_AD[28] P_AD[25] P_PAR P_AD[11]...
  • Page 116 13. Signals and Pinout > Pinout Table 27: Tsi350A 256 Pin List Signal Name P_CBE_b[0] P_RST_b P_REQ_b P_AD[27] P_IDSEL P_AD[22] P_AD[18] P_FRAME_b P_DEVSEL_b P_SERR_b P_AD[14] P_AD[9] P_GNT_b P_AD[24] P_CBE_b[3] P_AD[20] P_AD[17] P_CBE_b[2] P_TRDY_b P_LOCK_b P_AD[15] P_AD[12] P_M66EN P_AD[30] P_AD[29] P_AD[26]...

  • Page 117: Table 28: Tsi350A 256 Pin List - Power, Ground, And Reserved

    P_PERR_b P_CBE_b[1] P_AD[13] P_AD[10] Table 28: Tsi350A 256 Pin List - Power, Ground, and Reserved Name Pin Number A1, A16, B1, B2, B15, C3, C13, C14, D4, D13, D14, E5, E12, F6, F7, F8, F9, F10, F11, G2, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10,...
  • Page 118 13. Signals and Pinout > Pinout Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 119: Electrical Characteristics

    “Power Characteristics” on page 120 • “DC Specifications” on page 120 • “AC Timing Specifications” on page 122 14.1 Absolute Maximum Ratings The following tables contain the absolute maximum ratings for the Tsi350A. Table 29: Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units...

  • Page 120: Power Characteristics

    14. Electrical Characteristics > Power Characteristics 14.3 Power Characteristics The following table contains power characteristics for the Tsi350A. The value was measured in a typical configuration, including: • Primary PCI Bus: 66 MHz • Secondary PCI Bus: 66 MHz •...
  • Page 121 14. Electrical Characteristics > DC Specifications Table 32: Tsi350A DC Specifications Symbol Parameter Condition Exceptions Minimum Maximum Unit P_IDSEL pin capacitance IDSEL P_CLK, S_CLK pin capacitance a. These signals have special parameters for V Integrated Device Technology Tsi350A User Manual www.idt.com...

  • Page 122: Ac Timing Specifications

    14. Electrical Characteristics > AC Timing Specifications 14.6 AC Timing Specifications Figure Table 33, and Table 34 show the PCI signal timing specifications. Figure 7: PCI Signal Timing Measurement Conditions Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 123: Table 33: 33 Mhz Pci Signal Timing

    CLK to signal valid delay (point-to-point) 2 ns 6 ns Input setup time (bused signals) 3 ns (ptp) Input setup time to CLK (point-to-point) 5 ns Input signal hold time from CLK 0 ns Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...
  • Page 124 14. Electrical Characteristics > AC Timing Specifications Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 125: Registers

    Software changes the configuration register values that affect Tsi350A behavior only during initialization. Change these values subsequently only when both the primary and secondary PCI buses are idle, and the data buffers are empty; otherwise, the behavior of Tsi350A is unpredictable.
  • Page 126 15. Registers > Table 35: Tsi350A Configuration Space Register Names Starting Address Bits 31:24 Bits 23:16 Bits 15:8 Bits 7:0 BIST Header Type Primary Latency Timer Cache Line Size 0x0C Reserved 0x10 Reserved 0x14 Secondary latency timer Subordinate Bus Number...

  • Page 127: Reserved Register Addresses And Fields

    Table 36: Register Access Types Abbreviation Description Read Only Read or Write R/W1C Readable. Write 1 to Clear R/W1S Readable. Write 1 to Set.Writing a 1 triggers an event, bit reads as 0. Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 128: Pci-To-Pci Bridge Standard Configuration Registers

    Byte enable P_CBE_b[3:0] = 00xxb Reset Name Description Value 31:16 Device ID This 16-bit read only field contains the Device ID, which 0x0023 identifies the vendor of the device. Internally hardwired to be 0x0023. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 129: Primary Command Register-Offset 0X04

    15.2.3 Primary Command Register—Offset 0x04 These bits affect the behavior of Tsi350A primary interface, except where noted. Some of the bits are repeated in the bridge control register, to act on the secondary interface. This register must be initialized by configuration software.
  • Page 130 Controls Tsi350A’s response when a parity error is detected on the primary interface. 0 = Tsi350A does not assert P_PERR_b, nor does it set the data parity reported bit in the status register. Tsi350A does not report address parity errors by asserting P_SERR_b.

  • Page 131: Primary Status Register-Offset 0X04

    15. Registers > PCI-to-PCI Bridge Standard Configuration Registers 15.2.4 Primary Status Register—Offset 0x04 These bits affect the status of Tsi350A primary interface. Bits reflecting the status of the secondary interface are found in the secondary status register. • Dword address = 0x04 •...
  • Page 132 This bit is set to 1 when Tsi350A has asserted P_SERR_b. error Reset value: 0. Detected parity R/W1C This bit is set to 1 when Tsi350A detects an address or data error parity error on the primary interface. Reset value: 0. Tsi350A User Manual...

  • Page 133: Revision Id Register-Offset 0X08

    Dword address = 0x08 • Byte enable P_CBE_b[:0] = x0xxb Reset Name Type Description value 23:16 Subclass code Reads as 0x04 to indicate that this bridge device is a 0x04 PCI-to-PCI bridge. Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 134: Base Class Code Register-Offset 0X08

    Dword address = 0x08 • Byte enable P_CBE_b[3] = 0xxxb Reset Name Type Description value 31:24 Base class code Reads as 0x06 to indicate that this bridge device is a bridge 0x06 device. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 135: Cache Line Size Register-Offset 0X0C

    The cache line size should be written as a power of 2. If the value is not a power of 2 or is greater than 16, Tsi350A behaves as if the cache line size were 16 Dwords.

  • Page 136: Primary Bus Number Register-Offset 0X18

    Primary bus number Indicates the number of the PCI bus to which the primary interface is connected. Tsi350A uses this register to decode Type 1 configuration transactions on the secondary interface that should either be converted to special cycle transactions on the primary interface or passed upstream unaltered.

  • Page 137: Subordinate Bus Number Register-Offset 0X18

    All bits are writable, resulting in a granularity of one PCI clock cycle. 0 = Tsi350A ends the transaction after the first data transfer when Tsi350A’s secondary bus grant has been de-asserted, with the exception of memory write and invalidate transactions.

  • Page 138: I/O Base Address Register-Offset 0X1C

    I/O base address Defines the bottom address of an address range used [15:12] by Tsi350A to determine when to forward I/O transactions from one interface to the other. The upper 4 bits are writeable and correspond to address bits [15:12]. The lower 12 bits of the address are assumed 0.

  • Page 139: Secondary Status Register-Offset 0X1C

    15. Registers > PCI-to-PCI Bridge Standard Configuration Registers 15.2.18 Secondary Status Register—Offset 0x1C These bits reflect the status of Tsi350A secondary interface. W1C indicates that writing 1 to that bit sets the bit to 0. Writing 0 has no effect. •...
  • Page 140 S_SERR_b on the secondary interface. system error Reset value: 0. Detected parity error R/W1C This bit is set to 1 when Tsi350A detects an address or data parity error on the secondary interface. Reset value: 0. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 141: Memory Base Address Register-Offset 0X20

    Memory base address Defines the bottom address of an address range used [31:20] by Tsi350A to determine when to forward memory transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits [31:20]. The lower 20 bits of the address are assumed to be 0.

  • Page 142: Prefetchable Memory Base Address Register-Offset 0X24

    Prefetchable memory Defines the bottom address of an address range used base address [31:20] by Tsi350A to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits [31:20].

  • Page 143: Prefetchable Memory Base Address Upper 32 Bits Register-Offset 0X28

    Upper 32 prefetchable Defines the upper 32 bits of a 64-bit bottom address of memory base address an address range used by Tsi350A to determine when to [63:32] forward memory read and write transactions from one interface to the other. The memory address range adheres to 1 MB alignment and granularity.

  • Page 144: Prefetchable Memory Limit Address Upper 32 Bits Register-Offset 0X2C

    Upper 32 prefetchable Defines the upper 32 bits of a 64-bit top address of an memory limit address address range used by the Tsi350A to determine when to [63:32] forward memory read and write transactions from one interface to the other. Extra read transactions should have no side effects.

  • Page 145: I/O Base Address Upper 16 Bits Register-Offset 0X30

    Defines the upper 16 bits of a 32-bit bottom address of 16 bits [31:16] an address range used by Tsi350A to determine when to forward I/O transactions from one interface to the other. The I/O address range adheres to 4 kB alignment and granularity.

  • Page 146: Ecp Pointer Register-Offset 0X34

    • Dword address = 0x3C • Byte enable P_CBE_b[3:0] = xx0xb Reset Name Type Description value 15:8 Interrupt pin Reads as 0 to indicate that Tsi350A does not have an interrupt pin. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 147: Bridge Control Register-Offset 0X3C

    Controls Tsi350A’s response when a parity error is detected on the secondary interface. 0 = Tsi350A does not assert S_PERR_b, nor does it set the data parity reported bit in the secondary status register. Tsi350A does not report address parity errors by asserting P_SERR_b.
  • Page 148 FFFF FFFFh for read transactions. For posted write transactions, P_SERR_b is not asserted. 1 = Tsi350A returns a target abort on the initiator bus for delayed transactions. For posted write transactions, Tsi350A asserts P_SERR_b if the SERR_b enable bit is set in the command register.
  • Page 149 Primary master time-out Sets the maximum number of PCI clock cycles that Tsi350A waits for an initiator on the primary bus to repeat a delayed transaction request. The counter starts once the delayed transaction completion is at the head of the queue. If the master has not repeated...
  • Page 150 15. Registers > PCI-to-PCI Bridge Standard Configuration Registers Reset Name Type Description value 31:28 Reserved Reserved. Returns 0 when read. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 151: Device-Specific Configuration Registers

    15.3 Device-Specific Configuration Registers This section provides a detailed description of Tsi350A device-specific configuration registers. Each field has a separate description. Fields that have the same configuration address are selectable by turning on (driving low) the appropriate byte enable bits on P_CBE_b during the data phase. To select all fields of a configuration address, drive all byte enable bits low.

  • Page 152: Chip Control Register-Offset 0X40

    Controls when Tsi350A, as a target, disconnects memory disconnect control write transactions. 0 = Tsi350A disconnects on queue full or on a 4 kB boundary. 1 = Tsi350A disconnects on a cache line boundary, as well as when the queue fills or on a 4 kB boundary.

  • Page 153: Diagnostic Control Register-Offset 0X40

    Chip reset R/W1S Chip and secondary bus reset control. 1 = Causes Tsi350A to perform a chip reset. Data buffers, configuration registers, and both the primary and secondary interfaces are reset to their initial state. Tsi350A clears this bit once chip reset is complete.

  • Page 154: Arbiter Control Register-Offset 0X40

    Bits [24:16] correspond to request inputs S_REQ_b[8:0], respectively. Bit [25] corresponds to Tsi350A as a secondary bus master. 0 = Indicates that the master belongs to the low priority group.

  • Page 155: Read Transaction Control Register- Offset 0X44

    The read request retry from the secondary device will be registered as a new non-posted read request. 0 = Tsi350A follows PCI Bridge ordering rules. Integrated Device Technology Tsi350A User Manual www.idt.com...

  • Page 156: P_Serr_B Event Disable Register-Offset 0X64

    SERR_b enable bit in the command register is set. 1 = Signal P_SERR_b is not asserted if this event occurs. Reset value: 0. Posted write non Controls the Tsi350A’s ability to assert P_SERR_b when it is delivery unable to deliver posted write data after 2 attempts.

  • Page 157: Gpio Output Data Register-Offset 0X64

    Type Description value Delayed read—no Controls the Tsi350A’s ability to assert P_SERR_b when it is data from target unable to transfer any read data from the target after 2 attempts. 0 = Signal P_SERR_b is asserted if this event occurs and the SERR_b enable bit in the command register is set.

  • Page 158: Gpio Output Enable Control Register-Offset 0X64

    Reserved. Returns 0 when read. 31:28 GPIO input This read-only register reads the state of the GPIO[3:0] Undefined pins. This state is updated on the PCI clock cycle following a change in the GPIO pins. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 159: Secondary Clock Control Register-Offset 0X68

    0 = S_CLKOUT8 enabled (default). 1 = S_CLKOUT8 disabled and driven high. S_CLKOUT9 disable 0 = S_CLKOUT9 enabled (default). 1 = S_CLKOUT9 disabled and driven high. 15:14 Reserved Reserved: Return 0 when read. Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 160: P_Serr_B Status Register-Offset 0X68

    Reset value: 0. Posted write non R/W1C 1 = Signal P_SERR_b was asserted because the delivery Tsi350A was unable to deliver posted write data to the target after 2 attempts. Reset value: 0. Target abort R/W1C...

  • Page 161: Capability Id Register-Offset 0Xdc

    Dword address = 0xDC • Byte enable P_CBE_b[3:0] = xx0xb Reset Name Type Description value 15:8 NEXT_ITEM The next-item pointer returns 0xE4 to indicate that 0xE4 Tsi350A supports more than one extended capability. Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 162: Power Management Capabilities Register-Offset 0Xde

    Reads as 0 to indicate that this device does not support the D2 power management state. 31:27 PME_SUP PME_b Support. Reads as 0 to indicate that this device does not support the PME_b pin. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 163: Power Management Control And Status Register-Offset 0Xe0

    Reflects the current power state of this device. If an unimplemented power state is written to this register, Tsi350A completes the write transaction, ignores the write data, and does not change the value of this field. Writing a value of D0 when the previous state was D3 causes a chip reset to occur (without asserting S_RST_b).

  • Page 164: Ppb Support Extensions Registers-Offset 0Xe2

    15.3.16 Data Register—Offset 0xE3 • Dword address = 0xE0 • Byte enable P_CBE_b[3:0] = 0xxxb Reset Name Type Description value 31:24 Data Data register. This register is not implemented and reads 0x00. Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 165: Hs Capability Id Register- Offset 0Xe4

    Hot Swap Register Set. 15.3.18 HS Next Item Pointer Register— Offset 0xE5 Reset Name Type Description value 15:8 Hot Swap Next Pointer Returns 0x00 indicating that there are more list items in the capabilities list. Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 166: Hs Control Status Register- Offset 0Xe6

    Extraction The bridge sets this bit to indicate software that a board is about to be removed from the system. The bridge asserts HS_ENUM_b when this bit is set. Reset value: 0 Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...
  • Page 167 This bit will be set only after the following events: Ejector Handle is closed. P_RST_b de-asserted. The bridge asserts ENUM_b when this bit is set. Reset value: 0 Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...
  • Page 168 15. Registers > Device-Specific Configuration Registers Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 169: Package Information

    3.20 3.32 3.60 30.60 BSC. D1 E1 28.00 BSC. 0.08 0.25 0.08 Theta Theta1 Theta2 Theta3 8 REF 0.09 0.15 0.20 0.45 0.60 0.75 1.30 REF 0.20 0.17 0.20 0.27 0.50 BSC. Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 170: Figure 8: 208-Pin Pqfp Package Diagram - Top View

    A. Package Information > Package Characteristics Table 37: PQFP Symbol Values Millimeter Symbol Minimum Nominal Maximum 25.50 25.50 0.20 0.20 0.08 0.08 Figure 8: 208-pin PQFP Package Diagram - Top View Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 171: Figure 9: 208-Pin Pqfp Package Diagram - Side View

    A. Package Information > Package Characteristics Figure 9: 208-pin PQFP Package Diagram - Side View Figure 10: 208-pin PQFP Package Diagram - Side View Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 172: 256-Pin Pbga Package

    A. Package Information > Package Characteristics A.1.2 256-pin PBGA Package Figure 11: 256-pin PBGA Package Diagram - Top View Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 173: Figure 12: 256-Pin Pbga Package Diagram - Bottom View

    A. Package Information > Package Characteristics Figure 12: 256-pin PBGA Package Diagram - Bottom View Figure 13: 256-pin PBGA Package Diagram - Side View Integrated Device Technology Tsi350A User Manual www.idt.com 80D5000_MA001_08...

  • Page 174: Thermal Characteristics

    Failure mechanisms and failure rate of a device have an exponential dependence of the IC operating temperatures. Thus, the control of the package temperature, and by extension the Junction Temperature, is essential to ensure product reliability. The Tsi350A is specified safe for operation when the Junction Temperature is within the recommended limits.

  • Page 175: System-Level Characteristics

    A.2.3 Example on Thermal Data Usage Based on the Theta data and specified conditions, the following formula can be used to derive the junction temperature (Tj) of the Tsi350A with a 0m/s airflow: • Tj = Theta P + Tamb.
  • Page 176 A. Package Information > Thermal Characteristics Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...

  • Page 177: Ordering Information

    Ordering Information This appendix discusses Tsi350A’s ordering information. Ordering Information When ordering the Tsi350A please refer to the device by its full part number, as displayed in Table Table 40: Ordering Information Part Number Temp Package Description Tsi350A-66CQ Commercial 208-pin PQFP...
  • Page 178 B. Ordering Information > Ordering Information Tsi350A User Manual Integrated Device Technology 80D5000_MA001_08 www.idt.com...
  • Page 179 Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
  • Page 180 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology) TSI350A-66CLV...

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