Freescale Semiconductor MC68882 Manuals

Manuals and User Guides for Freescale Semiconductor MC68882. We have 1 Freescale Semiconductor MC68882 manual available for free PDF download: User Manual

Freescale Semiconductor MC68882 User Manual

Freescale Semiconductor MC68882 User Manual (409 pages)

FLOATING-POINT COPROCESSOR

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 15 MB

Table of Contents

(Continued)

6
- Table of Contents
  6
(Continued}

10
List of Tables

17
- Exception Status/Enable Byte
  24
- MC68881/MC68882 Programming Model
  24
- Accrued Exception Byte
  25
- Condition Code Byte
  25
- Mode Control Byte
  25
- Quotient Byte
  25
- Typical Coprocessor Configuration
  26
- MC68881 Simplified Block Diagram
  27
- MC68882 Simplified Block Diagram
  28
- Exponent and Mantissa Sizes
  31
- Condition Code Versus Result Data Type
  41
- Infinities
  47
  - Format of Normalized Numbers
    48
- Not-A-Numbers
  49
  - Format of Zero
    49
  - Format of Infinity
    49
- Binary Real Data Summary
  50
- Packed Decimal Real Data Format
  50
  - Format of Not-A-Numbers
    50
- Internal Data Format
  51
  - Binary Real Data Type Summary
    51
  - Packed Decimal Real Data Format
    51
- 3,5.1 Conversion to Extended Precision Data Format
  52
  - Intermediate Result Format
    52
- Format Conversions
  52
- Conversions to Other Data Formats
  53
- Data Format Details
  53
- Single Precision Binary Real Format
  54
- Double Precision Binary Real Format
  55
- Extended Precision Binary Real Format
  56
  - Packed Decimal Real Data Format Detail
    57
- Decimal String Type Definitions
  57
- Instruction Description Conventions
  59
- Instruction Groups
  59
- Data Movement Operations
  60
- Dyadic Operations
  60
  - Dyadic Operation Format
    60
- Monadic Operations
  61
  - Dyadic Operations
    61
  - Monadic Operation Format
    61
- Program Control Operations
  62
  - Dual Monadic Operation Format
    62
  - Conditional Test Mnemonics
    62
- Computational Accuracy
  63
- System Control Operations
  63
- Arithmetic Instructions
  64
- Transcendental Instructions
  65
- Conditional Test Definitions
  66
- Decimal Conversions
  66
- IEEE Nonaware Tests
  67
- IEEE Aware Tests
  69
- Addressing Modes
  70
- Detailed Instruction Descriptions
  70
- Miscellaneous Tests
  70
- Instruction Description Format
  71
- Operation Post Processing
  73
- Individual Instruction Descriptions
  75
- General Type Instruction Command Word Fields
  184
- Register Field Encoding
  185
- Extension Field Encoding for Arithmetic Operations
  186
- Source Format Field Encoding
  187
- Destination Format Field Encoding
  188
- Extension Field Encoding
  189
- Encoding for Move Fpcr Operations
  190
- Encodings for Move Multiple Fpn Operations
  192
- Conditional Predicate Evaluation Responses
  194
- Effective Address Field Encoding Summary
  197
- Conditional Predicate Field Encoding Summary
  198
  - MC68881 Concurrency - - FMUL Instruction
    210
- Minimum-Concurrency Instructions
  213
- Monadic Instructions
  213
- Dyadic Operations
  214
- Fully-Concurrent Instructions
  214
- Partial-Concurrency Instructions
  214
- Conditional Instructions
  215
  - MC68882 Concurrency - - FMUL Followed by FMUL and FMOVE
    216
  - Rolled Version of Linpack Loop
    218
- FMOVE Instruction Execution Times
  218
  - Optimized Linpack Loop
    219
- State Frame Sizes
  219
- MC68881/MC68882 Exception Vector Assignments
  228
  - EXC and ENABLE Byte Bit Assignments
    229
- Possible Operand Errors
  232
- Possible Divide-By-Zero Exceptions
  238
  - Intermediate Result Format
    240
  - Rounding Algorithm
    241
  - MC68881 State Frame Formats
    254
  - MC68882 State Frame Formats
    255
  - BIU Flag Format
    257
- BIU Flag Bit Definitions
  259
- MC68881/MC68882 Responses to Save Command
  260
- MC68881/MC68882 Format Word Definitions
  261
- MPU CPU Space Type Field Encoding
  266
- Coprocessor Interface Register Characteristics
  267
  - Coprocessor Instruction General Format
    273
  - FPCP Instruction Operation Word
    273
  - Null Primitive Format
    275
- Null Primitive Encodings
  276
  - Evaluate Effective Address and Transfer Data Primitive Format
    277
  - Transfer Single Main Processor Register Primitive Format
    278
- Coprocessor Valid Effective Address Codes
  278
- Evaluate Effective Address and Transfer Data Primitive Encoding
  278
- MC68881/MC68882 Primitive Responses
  284
- Effective Address Calculations
  319
- MC68881 Overall Execution Times
  320
- MC68882 Overall Execution Times
  321
- Timing Calculation Example
  322
- Move Control Register and MOVEM Execution Times
  323
- Instruction Start-Up Times
  331
  - Transfer Operand
    332
  - Null Primitive Time Values
    332
  - Operand Transfer Time - - External Operand
    332
  - Operand Transfer Time - - Immediate Operand
    332
    
    Input Operand Conversion
    333
    
    Arithmetic Calculation
    333
- Input Operand Conversion
  334
- Arithmetic Calculation Times - - Dyadic Operations
  336
  - Rounding and Exception Handling
    339
- Arithmetic Calculation Times - - Monadic Operations
  340
- Output Operand Conversion
  341
- Output Operand Conversion - - Binary Real Formats
  341
- Rounding Operation Time Values
  341
  - Conditional Termination
    342
  - Exception Handling Time Values
    342
    
    Multiple Register Transfer
    343
  - Conditional Termination Times Values
    343
    
    State Frame Transfer
    344
  - Multiple Register Transfer Time Values
    344
  - State Frame Transfer Time Values
    344
  - Instruction Termination Processing Time Values
    344
- Exception Processing Time Values
  345
  - Main Processor Instruction Overlap Timing
    346
  - Overlap Allowed Times - - Arithmetic Operations
    346
    
    Functional Signal Descriptions
    347
  - Data Bus (D0-D31)
    348
  - Size (SIZE)
    348
  - Coprocessor Interface Register Selection
    348
  - System Data Bus Size Configuration
    348
  - Address Strobe
    349
  - Chip Select (CS)
    349
  - Read/Write (R/W)
    349
  - Data Strobe (DS)
    349
- Data Transfer and Size Acknowledge (DSACK0, DSACK1)
  349
  - Clock (CLK)
    350
  - DSACK Assertions
    350
  - Sense Device (SENSE)
    351
  - Power (VCC and GND)
    351
  - No Connect (NC)
    352
  - Signal Summary
    352
  - VCC and GND Pin Assignments
    352
- Signal Summary
  353
  - Bus Operation
    355
- Basic Transfer Mechanism Overview
  355
  - 32-Bit Port Size
    356
  - 16-Bit Port Size
    357
  - 8-Bit Port Size
    358
  - Reset Operation
    359
  - Chip Select Timing
    360
- Bus Cycle Functional Descriptions
  361
  - Synchronous Read Cycles
    363
  - Asynchronous Read Cycles
    366
  - Asynchronous Write Cycles
    367
  - Inter-Cycle Timing Restrictions
    368
- Coprocessor Interface Protocol Restrictions
  369
- 16-Bit Data Bus Peripheral Processor Connection
  373
  - 8-Bit Data Bus Peripheral Processor Connection
    374
  - Peripheral Processor Operation
    374
    
    Electrical Specifications
    377
- M a X I M U M Ratings
  377
  - Thermal Characteristics - - Pga Package
    377
  - Power Considerations
    377
- DC Electrical Characteristics
  378
- AC Electrical Characteristics - - Clock Input
  379
- AC Electrical Characteristics = - Read and Write Cycles
  380
  - Ordering Information and Mechanical Data
    383
- Standard MC68881/MC68882 Order I N F O R M a T I O N
  383
- Pin Assignments
  384
- Package Dimensions
  385
  - Appendix Aglossary
    387
  - Appendix Babbreviations and Acronyms
    391
  - M I N I M U M Exception Handler
    396
- F P C P Vector Numbers
  404

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