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XRT86VX38
Exar XRT86VX38 Manuals
Manuals and User Guides for Exar XRT86VX38. We have
1
Exar XRT86VX38 manual available for free PDF download: Manual
Exar XRT86VX38 Manual (203 pages)
Brand:
Exar
| Category:
Amplifier
| Size: 1 MB
Table of Contents
Table of Contents
4
Table 1: Register Summary
8
Table 2:: Clock Select Register(CSR)
15
Table 3:: Line Interface Control Register (LICR) Hex Address: 0Xn101
17
Table 4:: General Purpose Input/Output 0 Control Register(GPIOCR0) Hex Address: 0X0102
19
Table 5:: General Purpose Input/Output 1 Control Register(GPIOCR1) Hex Address: 0X4102
20
Table 6:: Framing Select Register (FSR) Hex Address: 0Xn107
21
Table 7:: Alarm Generation Register (AGR) Hex Address: 0Xn108
23
Table 8:: Yellow Alarm Duration and Format When One Second Rule Is Not Enforced
24
Table 9: Yellow Alarm Format When One Second Rule Is Enforced
25
Table 10:: Synchronization MUX Register (SMR) Hex Address: 0Xn109
28
Table 11:: Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0Xn10A
31
Table 12: Framing Control Register (Fcr)
32
Table 13:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0Xn10C
34
Table 14:: Receive Signaling Change Register 0 (RSCR 0) Hex Address: 0Xn10D
35
Table 15:: Receive Signaling Change Register 1(RSCR 1)
35
Table 16:: Receive Signaling Change Register 2 (RSCR 2)
35
Table 17:: Receive in Frame Register (RIFR)
36
Table 18:: Data Link Control Register (DLCR1) Hex Address: 0Xn113
38
Table 19:: Transmit Data Link Byte Count Register (TDLBCR1) Hex Address: 0Xn114
39
Table 20:: Receive Data Link Byte Count Register (RDLBCR1) Hex Address: 0Xn115
40
Table 21:: Slip Buffer Control Register (SBCR) Hex Address: 0Xn116
41
Table 22:: FIFO Latency Register (FFOLR)
42
Table 23:: DMA 0 (Write) Configuration Register (D0WCR)
43
Table 24:: DMA 1 (Read) Configuration Register (D1RCR)
44
Table 25:: Interrupt Control Register (ICR)
45
Table 26: Lapd Select Register (Lapdsr)
46
Table 27:: Customer Installation Alarm Generation Register (CIAGR)
47
Table 28:: Performance Report Control Register (PRCR)
48
Table 29:: Gapped Clock Control Register (GCCR) Hex Address: 0Xn11E
49
Table 30:: Transmit Interface Control Register (TICR) Hex Address:0Xn120
51
Table 31:: Transmit Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)
52
Table 32: Transmit Interface Speed When Multiplexed Mode Is Enabled (Txmuxen = 1)
53
Table 33:: BERT Control & Status Register (BERTCSR0)
54
Table 35:: Receive Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)
58
Table 34:: Receive Interface Control Register (RICR) Hex Address: 0Xn122
59
Table 36: Receive Interface Speed When Multiplexed Mode Is Enabled (Txmuxen = 1)
59
Table 37:: BERT Control & Status Register (BERTCSR1)
60
Table 38:: Loopback Code Control Register - Code 0 (LCCR0) Hex Address: 0Xn124
63
Table 39:: Transmit Loopback Coder Register (TLCR)
64
Table 40:: Receive Loopback Activation Code Register - Code 0 (RLACR0) Hex Address: 0Xn126
64
Table 41:: Receive Loopback Deactivation Code Register - Code 0 (RLDCR0) Hex Address: 0Xn127
64
Table 42:: Receive Loopcode Detection Switch (RLCDS)
65
Table 43:: Defect Detection Enable Register (DDER)
66
Table 44:: Loopback Code Control Register - Code 1 (LCCR1) Hex Address: 0Xn12A
67
Table 45:: Receive Loopback Activation Code Register - Code 1 (RLACR1) Hex Address: 0Xn12B
68
Table 46:: Receive Loopback Deactivation Code Register - Code 1 (RLDCR1) Hex Address: 0Xn12C
68
Table 47:: Loopback Code Control Register - Code 2 (LCCR2) Hex Address: 0Xn12D
69
Table 48:: Receive Loopback Activation Code Register - Code 2 (RLACR2) Hex Address: 0Xn12E
70
Table 49:: Receive Loopback Deactivation Code Register - Code 2 (RLDCR2) Hex Address: 0Xn12F
70
Table 50:: Transmit Loopcode Generation Switch (TLCGS)
71
Table 51:: Loopcode Timer Select (LCTS)
71
Table 52:: Transmit SPRM and NPRM Control Register (TSPRMCR)
71
Table 53:: Data Link Control Register (DLCR2) Hex Address: 0Xn143
74
Table 54:: Transmit Data Link Byte Count Register (TDLBCR2) Hex Address: 0Xn144
75
Table 55:: Receive Data Link Byte Count Register (RDLBCR2) Hex Address: 0Xn145
76
Table 56:: Loopback Code Control Register - Code 3 (LCCR3) Hex Address: 0Xn146
77
Table 57:: Receive Loopback Activation Code Register - Code 3 (RLACR3) Hex Address: 0Xn147
78
Table 58:: Receive Loopback Deactivation Code Register - Code 3 (RLDCR3) Hex Address: 0Xn148
78
Table 59:: Loopback Code Control Register - Code 4 (LCCR4) Hex Address: 0Xn149
79
Table 60:: Receive Loopback Activation Code Register - Code 4 (RLACR4) Hex Address: 0Xn14A
80
Table 61:: Receive Loopback Deactivation Code Register - Code 4 (RLDCR4) Hex Address: 0Xn14B
80
Table 62:: Loopback Code Control Register - Code 5 (LCCR5) Hex Address: 0Xn14C
81
Table 63:: Receive Loopback Activation Code Register - Code 5 (RLACR5) Hex Address: 0Xn14D
82
Table 64:: Receive Loopback Deactivation Code Register - Code 5 (RLDCR5) Hex Address: 0Xn14E
82
Table 65:: Loopback Code Control Register - Code 6 (LCCR6) Hex Address: 0Xn14F
83
Table 66:: Receive Loopback Activation Code Register - Code 6 (RLACR6) Hex Address: 0Xn150
84
Table 67:: Receive Loopback Deactivation Code Register - Code 6 (RLDCR6) Hex Address: 0Xn151
84
Table 68:: Data Link Control Register (DLCR3) Hex Address: 0Xn153
86
Table 69:: Transmit Data Link Byte Count Register (TDLBCR3) Hex Address: 0Xn154
87
Table 70:: Receive Data Link Byte Count Register (RDLBCR3) Hex Address: 0Xn155
88
Table 71:: Loopback Code Control Register - Code 7 (LCCR7) Hex Address: 0Xn156
89
Table 72:: Receive Loopback Activation Code Register - Code 7 (RLACR7) Hex Address: 0Xn157
90
Table 73:: Receive Loopback Deactivation Code Register - Code 7 (RLDCR7) Hex Address: 0Xn158
90
Table 74:: BERT Control Register (BCR)
91
Table 75:: T1 SSM Messages
92
Table 76:: SSM BOC Control Register (BOCCR 0Xn170H)
93
Table 77:: SSM Receive FDL Register (RFDLR 0Xn171H)
94
Table 78:: SSM Receive FDL Match 1 Register (RFDLMR1 0Xn172H)
95
Table 79:: SSM Receive FDL Match 2 Register (RFDLMR2 0Xn173H)
95
Table 80:: SSM Receive FDL Match 3 Register (RFDLMR3 0Xn174H)
95
Table 81:: SSM Transmit FDL Register (TFDLR 0Xn175H)
96
Table 82:: SSM Transmit Byte Count Register (TBCR 0Xn176H)
96
Table 83:: Receive DS-0 Monitor Registers (RDS0MR)
97
Table 84:: Transmit DS-0 Monitor Registers (TDS0MR)
97
Table 85:: Device ID Register (DEVID)
98
Table 86:: Revision ID Register (REVID)
98
Table 87:: Transmit Channel Control Register 0-23 (TCCR 0-23)
99
Table 88:: Transmit User Code Register 0-23 (TUCR 0-23)
101
Table 89:: Transmit Signaling Control Register 0-23 (TSCR 0-23)
102
Table 90:: Receive Channel Control Register 0-23 (RCCR 0-23)
105
Table 91:: Receive User Code Register 0-23 (RUCR 0-23) Hex Address: 0Xn380 to 0Xn397
106
Table 92:: Receive Signaling Control Register 0-23 (RSCR 0-23) Hex Address: 0Xn3A0 to 0Xn3B7
107
Table 93:: Receive Substitution Signaling Register 0-23 (RSSR 0-23) Hex Address: 0Xn3C0 to 0Xn3D7
109
Table 94:: Receive Signaling Array Register 0 to 23 (RSAR 0-23) Hex Address: 0Xn500 to 0Xn517
110
Table 95:: LAPD Buffer 0 Control Register (LAPDBCR0)
111
Table 96:: LAPD Buffer 1 Control Register (LAPDBCR1)
111
Table 97:: PMON Receive Line Code Violation Counter MSB (RLCVCU)
112
Table 98:: PMON Receive Line Code Violation Counter LSB (RLCVCL)
112
Table 99:: PMON Receive Framing Alignment Bit Error Counter MSB (RFAECU) Hex Address: 0Xn902
113
Table 100:: PMON Receive Framing Alignment Bit Error Counter LSB (RFAECL) Hex Address: 0Xn903
113
Table 101:: PMON Receive Severely Errored Frame Counter (RSEFC)
114
Table 102:: PMON Receive CRC-6 BIT Error Counter - MSB (RSBBECU) Hex Address: 0Xn905
115
Table 103:: PMON Receive CRC-6 Bit Error Counter - LSB (RSBBECL) Hex Address: 0Xn906
115
Table 104:: PMON Receive Slip Counter (RSC)
116
Table 105:: PMON Receive Loss of Frame Counter (RLFC)
116
Table 106:: PMON Receive Change of Frame Alignment Counter (RCFAC) Hex Address: 0Xn90B
116
Table 107:: PMON LAPD1 Frame Check Sequence Error Counter 1 (LFCSEC1) Hex Address: 0Xn90C
117
Table 108:: PRBS Bit Error Counter MSB (PBECU)
117
Table 109:: PRBS Bit Error Counter LSB (PBECL)
117
Table 110: Transmit Slip Counter (Tsc)
118
Table 111:: Excessive Zero Violation Counter MSB (EZVCU)
118
Table 112:: Excessive Zero Violation Counter LSB (EZVCL)
118
Table 113:: PMON LAPD2 Frame Check Sequence Error Counter 2 (LFCSEC2) Hex Address: 0Xn91C
119
Table 114:: PMON LAPD2 Frame Check Sequence Error Counter 3 (LFCSEC3) Hex Address: 0Xn92C
119
Table 115:: Block Interrupt Status Register (BISR) Hex Address: 0Xnb00
120
Table 116:: Block Interrupt Enable Register (BIER) Hex Address: 0Xnb01
122
Table 117:: Alarm & Error Interrupt Status Register (AEISR) Hex Address: 0Xnb02
125
Table 118:: Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0Xnb03
126
Table 119:: Framer Interrupt Status Register (FISR) Hex Address: 0Xnb04
127
Table 120:: Framer Interrupt Enable Register (FIER) Hex Address: 0Xnb05
129
Table 121:: Data Link Status Register 1 (DLSR1) Hex Address: 0Xnb06
131
Table 122:: Data Link Interrupt Enable Register 1 (DLIER1)
133
Table 123:: Slip Buffer Interrupt Status Register (SBISR) Hex Address: 0Xnb08
135
Table 124:: Slip Buffer Interrupt Enable Register (SBIER) Hex Address: 0Xnb09
138
Table 125:: Receive Loopback Code 0 Interrupt and Status Register (RLCISR0) Hex Address: 0Xnb0A
140
Table 126:: Receive Loopback Code 0 Interrupt Enable Register (RLCIER0) Hex Address: 0Xnb0B
141
Table 127:: Excessive Zero Status Register (EXZSR)
142
Table 128:: Excessive Zero Enable Register (EXZER)
142
Table 129:: SS7 Status Register for LAPD1 (SS7SR1)
143
Table 130:: SS7 Enable Register for LAPD1 (SS7ER1)
143
Table 131:: Rxlos/Crc Interrupt Status Register (RLCISR)
144
Table 132:: Rxlos/Crc Interrupt Enable Register (RLCIER)
144
Table 133:: Receive Loopback Code 1 Interrupt and Status Register (RLCISR1) Hex Address: 0Xnb14
145
Table 134:: Receive Loopback Code 1 Interrupt Enable Register (RLCIER1) Hex Address: 0Xnb15
146
Table 135:: Data Link Status Register 2 (DLSR2) Hex Address: 0Xnb16
147
Table 136:: Data Link Interrupt Enable Register 2 (DLIER2)
149
Table 137:: SS7 Status Register for LAPD2 (SS7SR2)
151
Table 138:: SS7 Enable Register for LAPD2 (SS7ER2)
151
Table 139:: Receive Loopback Code 2 Interrupt and Status Register (RLCISR2) Hex Address: 0Xnb1A
152
Table 140:: Receive Loopback Code 2 Interrupt Enable Register (RLCIER2) Hex Address: 0Xnb1B
153
Table 141:: Receive Loopback Code 3 Interrupt and Status Register (RLCISR3) Hex Address: 0Xnb1C
154
Table 142:: Receive Loopback Code 3 Interrupt Enable Register (RLCIER3) Hex Address: 0Xnb1D
155
Table 143:: Receive Loopback Code 4 Interrupt and Status Register (RLCISR4) Hex Address: 0Xnb1E
156
Table 144:: Receive Loopback Code 4 Interrupt Enable Register (RLCIER4) Hex Address: 0Xnb1F
157
Table 145:: Receive Loopback Code 5 Interrupt and Status Register (RLCISR5) Hex Address: 0Xnb20
158
Table 146:: Receive Loopback Code 5 Interrupt Enable Register (RLCIER5) Hex Address: 0Xnb21
159
Table 147:: Receive Loopback Code 6 Interrupt and Status Register (RLCISR6) Hex Address: 0Xnb22
160
Table 148:: Receive Loopback Code 6 Interrupt Enable Register (RLCIER6) Hex Address: 0Xnb23
161
Table 149:: Receive Loopback Code 7 Interrupt and Status Register (RLCISR7) Hex Address: 0Xnb24
162
Table 150:: Receive Loopback Code 7 Interrupt Enable Register (RLCIER7) Hex Address: 0Xnb25
163
Table 151:: Data Link Status Register 3 (DLSR3) Hex Address: 0Xnb26
164
Table 152:: Data Link Interrupt Enable Register 3 (DLIER3) Hex Address: 0Xnb27
166
Table 153:: SS7 Status Register for LAPD3 (SS7SR3)
168
Table 154:: SS7 Enable Register for LAPD3 (SS7ER3)
168
Table 155:: Customer Installation Alarm Status Register (CIASR)
169
Table 156:: Customer Installation Alarm Status Register (CIAIER)
170
Table 157:: T1 BOC Interrupt Status Register (BOCISR 0Xnb70H)
171
Table 158:: T1 BOC Interrupt Enable Register (BOCIER 0Xnb71H)
173
Table 159:: T1 BOC Unstable Interrupt Status Register (BOCUISR 0Xnb74H)
174
Table 160:: T1 BOC Unstable Interrupt Enable Register (BOCUIER 0Xnb75H)
175
Table 161:: LIU Channel Control Register 0 (LIUCCR0)
177
Table 162:: Equalizer Control and Transmit Line Build out
178
Table 163:: LIU Channel Control Register 1 (LIUCCR1)
179
Table 164: Liu Channel Control Register 2 (Liuccr2)
181
Table 165:: LIU Channel Control Register 3 (LIUCCR3)
183
Table 166:: LIU Channel Control Interrupt Enable Register (LIUCCIER) Hex Address: 0X0Fn4
185
Table 167:: LIU Channel Control Status Register (LIUCCSR) Hex Address: 0X0Fn5
187
Table 168:: LIU Channel Control Interrupt Status Register (LIUCCISR) Hex Address: 0X0Fn6
191
Table 169:: LIU Channel Control Cable Loss Register (LIUCCCCR) Hex Address: 0X0Fn7
192
Table 170:: LIU Channel Control Arbitrary Register 1 (LIUCCAR1) Hex Address: 0X0Fn8
192
Table 171:: LIU Channel Control Arbitrary Register 2 (LIUCCAR2) Hex Address: 0X0Fn9
192
Table 172:: LIU Channel Control Arbitrary Register 3 (LIUCCAR3) Hex Address: 0X0Fna
193
Table 173:: LIU Channel Control Arbitrary Register 4 (LIUCCAR4) Hex Address: 0X0Fnb
193
Table 174:: LIU Channel Control Arbitrary Register 5 (LIUCCAR5) Hex Address: 0X0Fnc
193
Table 175:: LIU Channel Control Arbitrary Register 6 (LIUCCAR6) Hex Address: 0X0Fnd
194
Table 176:: LIU Channel Control Arbitrary Register 7 (LIUCCAR7) Hex Address: 0X0Fne
194
Table 177:: LIU Channel Control Arbitrary Register 8 (LIUCCAR8) Hex Address: 0X0Fnf
194
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