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Exar XRT86VX38 Manual

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8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2011
GENERAL DESCRIPTION
The XRT86VX38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short-
hual LIU integrated solution featuring R
(Relayless, Reconfigurable, Redundancy) and BITS
Timing element. The physical interface is optimized
with internal impedance, and with the patented pad
structure, the XRT86VX38 provides protection from
power failures and hot swapping.
The XRT86VX38 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
F
1. XRT86VX38 E
IGURE
Local PCM
XRT86VX38
Highway
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
System (Terminal) Side
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
3
technology
C
DS1 (T1/E1/J1) F
IGHT
HANNEL
Tx Overhead In
2-Frame
Tx Serial
Slip Buffer
Data In
Elastic Store
2-Frame
Rx Serial
Slip Buffer
Data Out
Elastic Store
PRBS
Performance
Generator &
Monitor
Analyser
Signaling &
JTAG
Alarms
INT
TxON
Memory
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VX38 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions
include
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
.
APPLICATIONS AND FEATURES (NEXT PAGE)
/LIU C
RAMER
OMBO
External Data
Link Controller
Rx Overhead Out
Tx LIU
Tx Framer
Interface
LLB
LB
Rx LIU
Rx Framer
Interface
LIU &
HDLC/LAPD
Loopback
Controllers
Control
Microprocessor
DMA
Interface
Interface
4
3
P
D[7:0]
A[11:0]
Select
Intel/Motorola µP
Configuration, Control &
Status Monitor
•
•
(510) 668-7000
FAX (510) 668-7017
XRT86VX38
REV. 1.0.3
Loop-backs,
Boundary
1:2 Turns Ratio
TTIP
TRING
1:1 Turns Ratio
RTIP
RRING
RxLOS
Line Side
WR
ALE_AS
RD
RDY_DTACK
•
www.exar.com
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  • Page 1 Data Link bits of the inbound T1/E1/J1 frames. with internal impedance, and with the patented pad structure, the XRT86VX38 provides protection from The XRT86VX38 fully meets all of the latest T1/E1/J1 power failures and hot swapping. specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/...
  • Page 2 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 APPLICATIONS  High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems  SONET/SDH terminal or Add/Drop multiplexers (ADMs)  T1/E1/J1 add/drop multiplexers (MUX)  Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 ...
  • Page 3 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/ REV. 1.0.3 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION  Extracts and inserts robbed bit signaling (RBS)  3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) ...

  • Page 4: Table Of Contents

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 LIST OF TABLES Table 1:: Register Summary .............................. 4 Table 2:: Clock Select Register(CSR) Hex Address: 0xN100 ..11 Table 3:: Line Interface Control Register (LICR) Hex Address: 0xN101 ....13 Table 4:: General Purpose Input/Output 0 Control Register(GPIOCR0) Hex Address: 0x0102 ......
  • Page 5 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 Table 59:: Loopback Code Control Register - Code 4 (LCCR4) Hex Address: 0xN149 ......75 Table 60:: Receive Loopback Activation Code Register - Code 4 (RLACR4) Hex Address: 0xN14A ....76 Table 61:: Receive Loopback Deactivation Code Register - Code 4 (RLDCR4) Hex Address: 0xN14B ....
  • Page 6 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 Table 118:: Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0xNB03 ....122 Table 119:: Framer Interrupt Status Register (FISR) Hex Address: 0xNB04 ....123 Table 120:: Framer Interrupt Enable Register (FIER) Hex Address: 0xNB05 ....
  • Page 7 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 Table 178:: LIU Global Control Register 0 (LIUGCR0) Hex Address: 0x0FE0 ..... 191 Table 179:: LIU Global Control Register 1 (LIUGCR1) Hex Address: 0x0FE1 ..... 193 Table 180:: LIU Global Control Register 2 (LIUGCR2) Hex Address: 0x0FE2 .....

  • Page 8: Table 1: Register Summary

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 DESCRIPTION OF THE CONTROL REGISTERS - T1 MODE All address on this register description is shown in HEX format. 1: R ABLE EGISTER UMMARY UNCTION YMBOL Control Registers (0xN100 - 0xN1FF)
  • Page 9 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1: R ABLE EGISTER UMMARY UNCTION YMBOL BERT Control & Status - Register 0 BERTCSR0 0xN121 Receive Interface Control Register RICR 0xN122 BERT Control & Status - Register 1...
  • Page 10 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1: R ABLE EGISTER UMMARY UNCTION YMBOL Receive Loopback Deactivation Code Register - Code 6 RLDCR6 0xN151 Data Link Control Register 3 DLCR3 0xN153 Transmit Data Link Byte Count Register 3...
  • Page 11 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1: R ABLE EGISTER UMMARY UNCTION YMBOL LAPDn Buffer 1 LAPD Buffer 1 Control Register LAPDBCR1 0xN700 - 0xN760 Performance Monitor Receive Line Code Violation Counter: MSB RLCVCU 0xN900...
  • Page 12 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1: R ABLE EGISTER UMMARY UNCTION YMBOL Slip Buffer Interrupt Enable Register SBIER 0xNB09 Receive Loopback code 0 Interrupt and Status Register RLCISR0 0xNB0A Receive Loopback code 0 Interrupt Enable Register...
  • Page 13 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1: R ABLE EGISTER UMMARY UNCTION YMBOL Customer Installation Alarm Interrupt Enable Register CIAIER 0xNB41 BOC Interrupt Status Register BOCISR 0xNB70 BOC Interrupt Enable Register BOCIER 0xNB71 Reserved 0xNB72 - 0xNB73...
  • Page 14 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1: R ABLE EGISTER UMMARY UNCTION YMBOL LIU Global Control Register 5 LIUGCR5 0x0FEA Reserved 0x0FEB - 0x0FFF...

  • Page 15: Table 2:: Clock Select Register(Csr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 1.0 REGISTER DESCRIPTIONS - T1 MODE All address on this register description is shown in HEX format 2: C (CSR) N100 ABLE LOCK ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION...
  • Page 16 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 2: C (CSR) N100 ABLE LOCK ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1:0 CSS[1:0] Clock Source Select These bits select the timing source for the Transmit T1 Framer block.

  • Page 17: Table 3:: Line Interface Control Register (Licr) Hex Address: 0Xn101

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 3: L (LICR) N101 ABLE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FORCE_LOS Force Transmit LOS (To the Line Side) This bit permits the user to configure the transmit direction circuitry (within the channel) to transmit the LOS pattern to the remote terminal equipment, as described below.
  • Page 18 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 3: L (LICR) N101 ABLE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Encode B8ZS Encode AMI or B8ZS/HDB3 Line Code Select This bit enables or disables the B8ZS/HDB3 encoder on the transmit path.

  • Page 19: Table 4:: General Purpose Input/Output 0 Control Register(Gpiocr0) Hex Address: 0X0102

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 4: G 0102 (GPIOCR0) ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 GPIO0_3DIR 1111 GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 Direction GPIO0_2DIR These bits permit the user to define the General Purpose I/O Pins,...

  • Page 20: Table 5:: General Purpose Input/Output 1 Control Register(Gpiocr1) Hex Address: 0X4102

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 5: G 4102 (GPIOCR1) ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 GPIO1_3DIR 0000 GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 Direction GPIO1_2DIR These bits permit the user to define the General Purpose I/O Pins,...

  • Page 21: Table 6:: Framing Select Register (Fsr) Hex Address: 0Xn107

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 6: F (FSR) N107 ABLE RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Signaling update on Enable Robbed-Bit Signaling Update on Superframe Boundary Superframe Boundaries on Both Transmit and Receive Direction...
  • Page 22 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 6: F (FSR) N107 ABLE RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FASTSYNC Faster Sync Algorithm This bit is used to specify one of the synchronization criteria that the Receive T1 Framer block employs.

  • Page 23: Table 7:: Alarm Generation Register (Agr) Hex Address: 0Xn108

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 7: A (AGR) N108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Yellow Alarm - One-Second Yellow Alarm Rule Enforcement One Second This bit is used to enforce the one-second yellow alarm rule according to the yel- Rule low alarm (RAI) transmission duration per the ANSI standards.

  • Page 24: Table 8:: Yellow Alarm Duration And Format When One Second Rule Is Not Enforced

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 7: A (AGR) N108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 5-4 YEL[1:0] Yellow Alarm (RAI) Duration and Format The exact function of these bits depends on whether or not the one-second yellow alarm rule is enforced.

  • Page 25: Table 9: Yellow Alarm Format When One Second Rule Is Enforced

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 7: A (AGR) N108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 5-4 YEL[1:0] (Continued) ABLE YELLOW ALARM FORMAT WHEN ONE SECOND RULE IS ENFORCED YEL[1:0] ELLOW LARM...
  • Page 26 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 7: A (AGR) N108 ABLE LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-2 Transmit AIS Transmit AIS Pattern Select[1:0]: Pattern These two bits permit the user to do the following.
  • Page 27 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 10: S MUX R (SMR) N109 ABLE YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved MFRAMEALIGN Transmit Multiframe Sync Alignment This bit forces Transmit T1 framer block to align with the backplane multiframe boundary (TxMSYNC_n).

  • Page 28: Table 10:: Synchronization Mux Register (Smr) Hex Address: 0Xn109

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 10: S MUX R (SMR) N109 ABLE YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Transmit Frame Sync Transmit Frame Sync Select Select This bit permits the user to configure the System-Side Terminal...
  • Page 29 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 10: S MUX R (SMR) N109 ABLE YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CRC-6 Bits Source CRC-6 Bits Source Select Select This bit permits the user to specify the source of the CRC-6 bits, within the outbound T1 data-stream, as depicted below.
  • Page 30 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 11: T N10A (TSDLSR) ABLE RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved Reserved Reserved 5-4 TxDLBW[1:0] Transmit Data Link Bandwidth[1:0] These two bits are used to select the bandwidth for data link mes- sage transmission.

  • Page 31: Table 11:: Transmit Signaling And Data Link Select Register (Tsdlsr) Hex Address:0Xn10A

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 11: T N10A (TSDLSR) ABLE RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxDL[1:0] Transmit Data Link Source Select [1:0] These two bits specify the source for data link bits that will be inserted in the outbound T1 frames.

  • Page 32: Table 12: Framing Control Register (Fcr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 12: F (FCR) N10B ABLE RAMING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reframe Force Reframe A ‘0’ to ‘1’ transition will force the Receive T1 Framer to restart the syn- chronization process.
  • Page 33 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 13: R & D (RSDLSR) N10C ABLE ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved Reserved Reserved 5-4 RxDLBW[1:0] Receive Data Link Bandwidth[1:0]: These two bits select the bandwidth for data link message reception.

  • Page 34: Table 13:: Receive Signaling & Data Link Select Register (Rsdlsr) Hex Address: 0Xn10C

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 13: R & D (RSDLSR) N10C ABLE ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 RxDL[1:0] Receive Data-Link Destination Select[1:0]: These bits specify the destination circuitry, that is used to process the Data-Link data, within the incoming T1 data-stream.

  • Page 35: Table 14:: Receive Signaling Change Register 0 (Rscr 0) Hex Address: 0Xn10D

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 14: R N10D (RSCR 0) ABLE ECEIVE IGNALING HANGE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Ch. 0 These bits indicate whether the Channel Associated signaling data, associated with Time-Slots 0 through 7 within the incoming T1 data- Ch.

  • Page 36: Table 17:: Receive In Frame Register (Rifr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 17: R (RIFR) N112 ABLE ECEIVE RAME EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION In Frame In Frame State This READ-ONLY bit indicates whether the Receive T1 Framer block is currently declaring the “In-Frame”...
  • Page 37 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 18: D (DLCR1) N113 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 Data Link SLC®96 DataLink Enable Enable This bit permits the user to configure the channel to support the transmission and reception of the “SLC-96 type”...

  • Page 38: Table 18:: Data Link Control Register (Dlcr1) Hex Address: 0Xn113

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 18: D (DLCR1) N113 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_IDLE Transmit Idle (Flag Sequence Byte) This bit configures the Transmit HDLC Controller Block #1 to uncon- ditionally transmit a repeating string of Flag Sequence octets (0X7E) in the data link channel to the Remote terminal.

  • Page 39: Table 19:: Transmit Data Link Byte Count Register (Tdlbcr1) Hex Address: 0Xn114

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 19: T (TDLBCR1) N114 ABLE RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxHDLC1 BUFAvail/ Transmit HDLC1 Buffer Available/Buffer Select BUFSel This bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below.

  • Page 40: Table 20:: Receive Data Link Byte Count Register (Rdlbcr1) Hex Address: 0Xn115

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 20: R (RDLBCR1) N115 ABLE ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RBUFPTR Receive HDLC1 Buffer-Pointer This bit Identifies which Receive HDLC1 buffer contains the most recently received HDLC1 message.

  • Page 41: Table 21:: Slip Buffer Control Register (Sbcr) Hex Address: 0Xn116

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 21: S (SBCR) N116 ABLE UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSB_ISFIFO Transmit Slip Buffer Mode This bit permits the user to configure the Transmit Slip Buffer to function as either “Slip-Buffer”...

  • Page 42: Table 22:: Fifo Latency Register (Ffolr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 21: S (SBCR) N116 ABLE UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SB_ENB(1) Receive Slip Buffer Mode Select These bits select modes of operation for the receive slip buffer. These two...

  • Page 43: Table 23:: Dma 0 (Write) Configuration Register (D0Wcr)

    1 =WR functions as a write strobe signal 4 - 3 Reserved Reserved DMA0_CHAN(2) Channel Select These three bits select which T1 channel within the XRT86VX38 uses DMA0_CHAN(1) the Transmit DMA_0 (Write) interface. 000 = Channel 0 DMA0_CHAN(0) 001 = Reserved...

  • Page 44: Table 24:: Dma 1 (Read) Configuration Register (D1Rcr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 24: DMA 1 (R (D1RCR) N119 ABLE ONFIGURATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 Reserved Reserved DMA1 RST DMA_1 Reset This bit resets the Receive DMA (Read) Channel 1 0 = Normal operation.

  • Page 45: Table 25:: Interrupt Control Register (Icr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 25: I (ICR) N11A ABLE NTERRUPT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-3 Reserved Reserved INT_WC_RUR Interrupt Write-to-Clear or Reset-upon-Read Select This bit configures all Interrupt Status bits to be either Reset Upon...

  • Page 46: Table 26: Lapd Select Register (Lapdsr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 26: LAPD S (LAPDSR) N11B ABLE ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:5] Reserved Reserved HDLC3en HDLC Controller 3 Enable This bit is used to enable or disable HDLC Controller 3. By default, the HDLC controller is Enabled, this bit set to "1".

  • Page 47: Table 27:: Customer Installation Alarm Generation Register (Ciagr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 27: C (CIAGR) N11C ABLE USTOMER NSTALLATION LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:4] Reserved Reserved [3:2] CIAG CI Alarm Transmit (Only in ESF) These two bits are used to enable or disable AIS-CI or RAI-CI gen- eration in T1 ESF mode only.

  • Page 48: Table 28:: Performance Report Control Register (Prcr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 28: P (PRCR) N11D ABLE ERFORMANCE EPORT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION LBO_ADJ_ENB Transmit Line Build Out Auto Adjustment: This bit is used to enable or disable the transmit line build out auto adjustment feature.

  • Page 49: Table 29:: Gapped Clock Control Register (Gccr) Hex Address: 0Xn11E

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 29: G (GCCR) N11E ABLE APPED LOCK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FrOutclk Framer Output Clock Reference This bit is used to enable or disable high-speed T1 rate on the T1OSCCLK and the E1OSCCLK output pins.
  • Page 50 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 30: T (TICR) N120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSyncFrD Tx Synchronous fraction data interface This bit selects whether TxCHCLK or TxSERCLK will be used for fractional data input if fractional interface is enabled.

  • Page 51: Table 30:: Transmit Interface Control Register (Ticr) Hex Address:0Xn120

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 30: T (TICR) N120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxFr1544 Fractional/Signaling Interface Enabled This bit is used to enable or disable the transmit fractional data interface, sig- naling input, as well as the 32MHz transmit clock and the transmit overhead Signal output.

  • Page 52: Table 31:: Transmit Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 30: T (TICR) N120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxIMODE[1:0] Transmit Interface Mode selection This bit determines the transmit interface speed. The exact function of these two bits depends on whether Multiplexed mode is enabled or disabled.

  • Page 53: Table 32: Transmit Interface Speed When Multiplexed Mode Is Enabled (Txmuxen = 1)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 30: T (TICR) N120 ABLE RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxIMODE[1:0] (Continued) 32: T ABLE RANSMIT NTERFACE PEED WHEN ULTIPLEXED ODE IS MUXEN = 1)

  • Page 54: Table 33:: Bert Control & Status Register (Bertcsr0)

    BERT_Switch BERT Switch This bit enables or disables the BERT switch function within the XRT86VX38 device. By enabling the BERT switch function, BERT functionality will be switched between the receive and transmit framer. T1 Receive framer will generate the BERT pattern and insert it onto the receive...
  • Page 55 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 33: BERT C & S (BERTCSR0) N121 ABLE ONTROL TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION UnFramedBERT Unframed BERT Pattern This bit enables or disables unframed BERT pattern generation (i.e.
  • Page 56 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 34: R (RICR) N122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSyncFrD Reserved Reserved Reserved RxPLClkEnb/ Receive payload clock enable/RxSYNC is Active Low RxSync is low This exact function of this bit depends on whether the T1 framer is configured to operate in base rate or high speed modes of operation.
  • Page 57 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 34: R (RICR) N122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxMUXEN Receive Multiplexed Mode Enable This bit enables or disables the multiplexed mode on the receive side. When...

  • Page 58: Table 35:: Receive Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 34: R (RICR) N122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 RxIMODE[1:0] Receive Interface Mode Selection[1:0] This bit determines the receive backplane interface speed. The exact func- tion of these two bits depends on whether Receive Multiplexed mode is enabled or disabled.

  • Page 59: Table 34:: Receive Interface Control Register (Ricr) Hex Address: 0Xn122

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 34: R (RICR) N122 ABLE ECEIVE NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 RxIMODE[1:0] (Continued):( 36: R ABLE ECEIVE NTERFACE PEED WHEN ULTIPLEXED ODE IS MUXEN = 1)

  • Page 60: Table 37:: Bert Control & Status Register (Bertcsr1)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 37: BERT C & S (BERTCSR1) N123 ABLE ONTROL TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION PRBSTyp PRBS Pattern Type This bit selects the type of PRBS pattern that the T1 Transmit/ Receive framer will generate or detect.
  • Page 61 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 37: BERT C & S (BERTCSR1) N123 ABLE ONTROL TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxBERTLock Lock Status This bit indicates whether or not the Receive or Transmit BERT lock has obtained.
  • Page 62 UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length. There are four lengths supported by the XRT86VX38 as presented in the table below: ECEIVE OOPBACK CTIVATION RXLBCALEN[1:0] ENGTH Selects 4-bit receive loopback code activa-...

  • Page 63: Table 38:: Loopback Code Control Register - Code 0 (Lccr0) Hex Address: 0Xn124

    UNCTION EFAULT ESCRIPTION PERATION 3-2 TXLBCLEN[1:0] Transmit Loopback Code Length This bit determines transmit loopback code length. There are four lengths supported by the XRT86VX38 as presented in the table below RANSMIT OOPBACK ODE ACTIVATION TXLBCLEN[1:0] ENGTH Selects 4-bit transmit loopback code...

  • Page 64: Table 39:: Transmit Loopback Coder Register (Tlcr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 39: T (TLCR) N125 ABLE RANSMIT OOPBACK ODER EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 TXLBC[6:0] 1010101 Transmit Loopback Code These seven bits determine the transmit loopback code. The MSB of the transmit loopback code is loaded first for transmission.

  • Page 65: Table 42:: Receive Loopcode Detection Switch (Rlcds)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 42: R (RLCDS) N128 ABLE ECEIVE ETECTION WITCH DDRESS UNCTION EFAULT ESCRIPTION PERATION RxLCDetSwitch7 Receive LoopCode Switch 7 If receive loopcode 7 is enabled, this bit will determine which input the loopcode will be detected on.

  • Page 66: Table 43:: Defect Detection Enable Register (Dder)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 42: R (RLCDS) N128 ABLE ECEIVE ETECTION WITCH DDRESS UNCTION EFAULT ESCRIPTION PERATION RxLCDetSwitch1 Receive LoopCode Switch 1 If receive loopcode 1 is enabled, this bit will determine which input the loopcode will be detected on.

  • Page 67: Table 44:: Loopback Code Control Register - Code 1 (Lccr1) Hex Address: 0Xn12A

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 44: L 1 (LCCR1) N12A ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 68: Table 45:: Receive Loopback Activation Code Register - Code 1 (Rlacr1) Hex Address: 0Xn12B

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 45: R 1 (RLACR1) N12B ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.

  • Page 69: Table 47:: Loopback Code Control Register - Code 2 (Lccr2) Hex Address: 0Xn12D

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 47: L 2 (LCCR2) N12D ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 70: Table 48:: Receive Loopback Activation Code Register - Code 2 (Rlacr2) Hex Address: 0Xn12E

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 48: R 2 (RLACR2) N12E ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.

  • Page 71: Table 50:: Transmit Loopcode Generation Switch (Tlcgs)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 50: T (TLCGS) N140 ABLE RANSMIT ENERATION WITCH DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 Reserved Reserved TxLCGenSwitch Transmit LoopCode Switch If the transmit loopcode is enabled, this bit will determine which direction the loopcode will be transmitted.
  • Page 72 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 52: T SPRM NPRM C (TSPRMCR) N142 ABLE RANSMIT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION U2_BIT U2 Bit This bit provides the contents of the U2 bit within the outgoing SPRM message.
  • Page 73 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 53: D (DLCR2) N143 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 Data Link SLC®96 DataLink Enable Enable This bit permits the user to configure the channel to support the transmission and reception of the “SLC-96 type”...

  • Page 74: Table 53:: Data Link Control Register (Dlcr2) Hex Address: 0Xn143

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 53: D (DLCR2) N143 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_IDLE Transmit Idle (Flag Sequence Byte) This bit configures the Transmit HDLC Controller Block #2 to uncon- ditionally transmit a repeating string of Flag Sequence octets (0X7E) in the data link channel to the Remote terminal.

  • Page 75: Table 54:: Transmit Data Link Byte Count Register (Tdlbcr2) Hex Address: 0Xn144

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 54: T (TDLBCR2) N144 ABLE RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxHDLC2 BUFAvail/ Transmit HDLC2 Buffer Available/Buffer Select BUFSel This bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below.

  • Page 76: Table 55:: Receive Data Link Byte Count Register (Rdlbcr2) Hex Address: 0Xn145

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 55: R (RDLBCR2) N145 ABLE ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RBUFPTR Receive HDLC2 Buffer-Pointer This bit Identifies which Receive HDLC2 buffer contains the most recently received HDLC2 message.

  • Page 77: Table 56:: Loopback Code Control Register - Code 3 (Lccr3) Hex Address: 0Xn146

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 56: L 3 (LCCR3) N146 ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 78: Table 57:: Receive Loopback Activation Code Register - Code 3 (Rlacr3) Hex Address: 0Xn147

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 57: R 3 (RLACR3) N147 ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.

  • Page 79: Table 59:: Loopback Code Control Register - Code 4 (Lccr4) Hex Address: 0Xn149

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 59: L 4 (LCCR4) N149 ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 80: Table 60:: Receive Loopback Activation Code Register - Code 4 (Rlacr4) Hex Address: 0Xn14A

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 60: R 4 (RLACR4) N14A ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.

  • Page 81: Table 62:: Loopback Code Control Register - Code 5 (Lccr5) Hex Address: 0Xn14C

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 62: L 5 (LCCR5) N14C ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 82: Table 63:: Receive Loopback Activation Code Register - Code 5 (Rlacr5) Hex Address: 0Xn14D

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 63: R 5 (RLACR5) N14D ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.

  • Page 83: Table 65:: Loopback Code Control Register - Code 6 (Lccr6) Hex Address: 0Xn14F

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 65: L 6 (LCCR6) N14F ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 84: Table 66:: Receive Loopback Activation Code Register - Code 6 (Rlacr6) Hex Address: 0Xn150

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 66: R 6 (RLACR6) N150 ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.
  • Page 85 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 68: D (DLCR3) N153 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 Data SLC®96 DataLink Enable Link Enable This bit permits the user to configure the channel to support the transmission and reception of the “SLC-96 type”...

  • Page 86: Table 68:: Data Link Control Register (Dlcr3) Hex Address: 0Xn153

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 68: D (DLCR3) N153 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_IDLE Transmit Idle (Flag Sequence Byte) This bit configures the Transmit HDLC Controller Block #3 to unconditionally transmit a repeating string of Flag Sequence octets (0X7E) in the data link channel to the Remote terminal.

  • Page 87: Table 69:: Transmit Data Link Byte Count Register (Tdlbcr3) Hex Address: 0Xn154

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 69: T (TDLBCR3) N154 ABLE RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxHDLC3 BUFAvail/ Transmit HDLC3 Buffer Available/Buffer Select BUFSel This bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below.

  • Page 88: Table 70:: Receive Data Link Byte Count Register (Rdlbcr3) Hex Address: 0Xn155

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 70: R (RDLBCR3) N155 ABLE ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RBUFPTR Receive HDLC2 Buffer-Pointer This bit Identifies which Receive HDLC3 buffer contains the most recently received HDLC3 message.

  • Page 89: Table 71:: Loopback Code Control Register - Code 7 (Lccr7) Hex Address: 0Xn156

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 71: L 7 (LCCR7) N156 ABLE OOPBACK ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This bit determines the receive loopback code activation length.

  • Page 90: Table 72:: Receive Loopback Activation Code Register - Code 7 (Rlacr7) Hex Address: 0Xn157

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 72: R 7 (RLACR7) N157 ABLE ECEIVE OOPBACK CTIVATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBAC[6:0] 1010101 Receive activation loopback code These seven bits determine the receive loopback activation code.

  • Page 91: Table 74:: Bert Control Register (Bcr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 74: BERT C (BCR) N163 ABLE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 Reserved Reserved 3-0 BERT[3:0] 0000 BERT Pattern Select 0010 =PRBS X20 + X3 + 1...

  • Page 92: Table 75:: T1 Ssm Messages

    T1 synchronization messages are sent through the FDL (Facility Data Link) bits by using a BOC (Bit Oriented Code) controller within the XRT86VX38 device. The most right bit position in the BOC code is sent first. The SSM message that are used in typical BITS applications are shown below. These messages are defined in specification ANSI T1.101-1999.

  • Page 93: Table 76:: Ssm Boc Control Register (Boccr 0Xn170H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 76: SSM BOC C (BOCCR 0 N170 ABLE ONTROL EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 TxABORT RMF[1:0] RBOCE BOCR RBF[1:0] SBOC Auto Clear Auto Clear BIT 7 - Transmit Abort Sequence Enable By default, the transmitter will send an IDLE flag after the SSM message (unless continous is set).

  • Page 94: Table 77:: Ssm Receive Fdl Register (Rfdlr 0Xn171H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 77: SSM R FDL R (RFDLR 0 N171 ABLE ECEIVE EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved RBOC[5:0] BITS [7:6] - Reserved BITS [5:0] - Receive BOC Message These bits contain the most recently received BOC message if the filter setting has been meet in bits[2:1] of register 0xn170h.

  • Page 95: Table 78:: Ssm Receive Fdl Match 1 Register (Rfdlmr1 0Xn172H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 78: SSM R FDL M (RFDLMR1 0 N172 ABLE ECEIVE ATCH EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved RFDLM1[5:0] BITS [7:6] - Reserved BITS [5:0] - Receive FDL Match 1 These bits can be used to set an expected value to be compared to the actual receive FDL message.

  • Page 96: Table 81:: Ssm Transmit Fdl Register (Tfdlr 0Xn175H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 81: SSM T FDL R (TFDLR 0 N175 ABLE RANSMIT EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved TBOC[5:0] BITS [7:6] - Reserved BITS [5:0] - Transmit BOC Message These bits are used to store the BOC message to be transmitted out the FDL bits.

  • Page 97: Table 83:: Receive Ds-0 Monitor Registers (Rds0Mr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 83: R DS-0 M (RDS0MR) ABLE ECEIVE ONITOR EGISTERS N160 N16F ( N163) N1C0 N1D0 DDRESS NOT INCLUDING UNCTION EFAULT ESCRIPTION PERATION 7-0 RxDS-0[7:0] 00000000 Receive DS-0 Monitor The contents of these registers will display a direct copy of the value currently being processed by the receive framer within the selected time slot.

  • Page 98: Table 85:: Device Id Register (Devid)

    7-0 REVID[7:0] 00000001 REVID This register is used to identify the revision number of the XRT86VX38. The value of this register for the first revision is A - 0x01h. : The content of this register is subject to change when a newer...

  • Page 99: Table 87:: Transmit Channel Control Register 0-23 (Tccr 0-23)

    Register 0xN300 represents D/E time slot 0, and 0xN317 represents D/E time slot 23. 5 - 4 TxZERO[1:0] Selects Type of Zero Suppression These bits select the type of zero code suppression used by the XRT86VX38 device ZERO[1:0] YPE OF UPPRESSION ELECTED No zero code suppression is used AT&T bit 7 stuffing is used...
  • Page 100 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 87: T 0-23 (TCCR 0-23) N300 N317 ABLE RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 TxCond(3:0) 0000 Transmit Channel Conditioning for Timeslot 0 to 23 These bits allow the user to substitute the input PCM data (Octets 0-23) with internally generated Conditioning Codes prior to transmission to the remote terminal equipment on a per-channel basis.

  • Page 101: Table 88:: Transmit User Code Register 0-23 (Tucr 0-23)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 88: T 0-23 (TUCR 0-23) N320 N337 ABLE RANSMIT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TUCR[7:0] b00010111 Transmit Programmable User code. These eight bits allow users to program any code in this register to...

  • Page 102: Table 89:: Transmit Signaling Control Register 0-23 (Tscr 0-23)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 89: T 0-23 (TSCR 0-23) N340 N357 ABLE RANSMIT IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION A (x) See Note Transmit Signaling bit A This bit allows user to provide signaling Bit A (Octets 0-23) if...
  • Page 103 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 89: T 0-23 (TSCR 0-23) N340 N357 ABLE RANSMIT IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSIGSRC[1] See Note Channel signaling control These bits determine the source for signaling information, see table...
  • Page 104 : Register 0xN360 represents D/E time slot 0, and 0xN377 represents D/E time slot 23. 5-4 RxZERO[1:0] Type of Zero Suppression These bits select the type of zero code suppression used by the XRT86VX38 device. YPE OF UPPRESSION ZERO[1:0] ELECTED No zero code suppression is used AT&T bit 7 stuffing is used...

  • Page 105: Table 90:: Receive Channel Control Register 0-23 (Rccr 0-23)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 90: R 0-23 (RCCR 0-23) N360 N377 ABLE ECEIVE HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 RxCOND[3:0] 0000 Receive Channel Conditioning for Timeslot 0 to 23 These bits allow the user to substitute the input line data (Octets 0-23) with internally generated Conditioning Codes prior to transmission to the back- plane interface on a per-channel basis.

  • Page 106: Table 91:: Receive User Code Register 0-23 (Rucr 0-23) Hex Address: 0Xn380 To 0Xn397

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 91: R 0-23 (RUCR 0-23) N380 N397 ABLE ECEIVE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-0 RxUSER[7:0] 11111111 Receive Programmable User code. These eight bits allow users to program any code in this register to...

  • Page 107: Table 92:: Receive Signaling Control Register 0-23 (Rscr 0-23) Hex Address: 0Xn3A0 To 0Xn3B7

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 92: R 0-23 (RSCR 0-23) N3A0 N3B7 ABLE ECEIVE IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SIGC_ENB Signaling substitution enable This bit enables or disables signaling substitution on the receive side.
  • Page 108 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 92: R 0-23 (RSCR 0-23) N3A0 N3B7 ABLE ECEIVE IGNALING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-2 RxSIGC[1:0]] Signaling conditioning [1:0] These bits allow user to select the format of signaling substitution on a per-channel basis, as presented in the table below.

  • Page 109: Table 93:: Receive Substitution Signaling Register 0-23 (Rssr 0-23) Hex Address: 0Xn3C0 To 0Xn3D7

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 93: R 0-23 (RSSR 0-23) N3C0 ABLE ECEIVE UBSTITUTION IGNALING EGISTER DDRESS N3D7 UNCTION EFAULT ESCRIPTION PERATION 7-4 Reserved Reserved SIG16-A, 4-A, 2-A 16-code/4-code/2-code Signaling Bit A This bit provides the value of signaling bit A to substitute the receive signaling bit A when 16-code or 4-code or 2-code signaling substitu- tion is enabled.

  • Page 110: Table 94:: Receive Signaling Array Register 0 To 23 (Rsar 0-23) Hex Address: 0Xn500 To 0Xn517

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 94: R 23 (RSAR 0-23) N500 N517 ABLE ECEIVE IGNALING RRAY EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 Reserved Reserved These READ ONLY registers reflect the most recently received sig- naling value (A,B,C,D) associated with timeslot 0 to 31.

  • Page 111: Table 95:: Lapd Buffer 0 Control Register (Lapdbcr0)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 95: LAPD B (LAPDBCR0) N600 ABLE UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-0 LAPD Buffer 0 LAPD Buffer 0 (96-Bytes) Auto Incrementing This register is used to transmit and receive LAPD messages within buffer 0 of the HDLC controller.

  • Page 112: Table 97:: Pmon Receive Line Code Violation Counter Msb (Rlcvcu)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 97: PMON R MSB (RLCVCU) N900 ABLE ECEIVE IOLATION OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RLCVC[15] Performance Monitor “Receive Line Code Violation” 16-bit Counter - Upper Byte: RLCVC[14] These RESET-upon-READ bits, along with that within the PMON...

  • Page 113: Table 99:: Pmon Receive Framing Alignment Bit Error Counter Msb (Rfaecu) Hex Address: 0Xn902

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 99: PMON R MSB (RFAECU) H ABLE ECEIVE RAMING LIGNMENT RROR OUNTER DDRESS N902 UNCTION EFAULT ESCRIPTION PERATION RFAEC[15] Performance Monitor “Receive Framing Alignment Error 16-Bit counter” - Upper Byte: RFAEC[14] These RESET-upon-READ bits, along with that within the “PMON...

  • Page 114: Table 101:: Pmon Receive Severely Errored Frame Counter (Rsefc)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 101: PMON R (RSEFC) N904 ABLE ECEIVE EVERELY RRORED RAME OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSEFC[7] Performance Monitor - Receive Severely Errored frame Counter (8-bit Counter) RSEFC[6] These Reset-Upon-Read bit fields reflect the cumulative number of...

  • Page 115: Table 102:: Pmon Receive Crc-6 Bit Error Counter - Msb (Rsbbecu) Hex Address: 0Xn905

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 102: PMON R CRC-6 BIT E - MSB (RSBBECU) N905 ABLE ECEIVE RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSBBEC[15] Performance Monitor “Receive Synchronization Bit Error 16-Bit Counter” - Upper Byte: RSBBEC[14] These RESET-upon-READ bits, along with that within the “PMON...

  • Page 116: Table 104:: Pmon Receive Slip Counter (Rsc)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 104: PMON R (RSC) N909 ABLE ECEIVE OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSC[7] Performance Monitor - Receive Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of...

  • Page 117: Table 107:: Pmon Lapd1 Frame Check Sequence Error Counter 1 (Lfcsec1) Hex Address: 0Xn90C

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 107: PMON LAPD1 F 1 (LFCSEC1) ABLE RAME HECK EQUENCE RROR OUNTER DDRESS N90C UNCTION EFAULT ESCRIPTION PERATION FCSEC1[7] Performance Monitor - LAPD 1 Frame Check Sequence Error Counter (8-bit Counter)

  • Page 118: Table 110: Transmit Slip Counter (Tsc)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 110: T (TSC) N90F ABLE RANSMIT OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSLIP[7] Performance Monitor - Transmit Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of...

  • Page 119: Table 113:: Pmon Lapd2 Frame Check Sequence Error Counter 2 (Lfcsec2) Hex Address: 0Xn91C

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 113: PMON LAPD2 F 2 (LFCSEC2) ABLE RAME HECK EQUENCE RROR OUNTER DDRESS N91C UNCTION EFAULT ESCRIPTION PERATION FCSEC2[7] Performance Monitor - LAPD 2 Frame Check Sequence Error Counter (8-bit Counter)

  • Page 120: Table 115:: Block Interrupt Status Register (Bisr) Hex Address: 0Xnb00

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 115: B (BISR) NB00 ABLE LOCK NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved For E1 mode only LBCODE Loopback Code Block Interrupt Status This bit indicates whether or not the Loopback Code block has an interrupt request awaiting service.
  • Page 121 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 115: B (BISR) NB00 ABLE LOCK NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLIP Slip Buffer Block Interrupt Status This bit indicates whether or not the Slip Buffer block has any out- standing interrupt request awaiting service.

  • Page 122: Table 116:: Block Interrupt Enable Register (Bier) Hex Address: 0Xnb01

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 116: B (BIER) NB01 ABLE LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved For E1 mode only LBCODE_ENB Loopback Code Block interrupt enable This bit permits the user to either enable or disable the Loopback Code Interrupt Block for interrupt generation.
  • Page 123 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 116: B (BIER) NB01 ABLE LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLIP_ENB Slip Buffer Block Interrupt Enable This bit permits the user to either enable or disable the Slip Buffer Block for interrupt generation.
  • Page 124 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 117: A & E (AEISR) NB02 ABLE LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Rx OOF Receive Out of Frame Defect State State This READ-ONLY bit indicates whether or not the Receive T1 Framer block is currently declaring the “Out of Frame”...

  • Page 125: Table 117:: Alarm & Error Interrupt Status Register (Aeisr) Hex Address: 0Xnb02

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 117: A & E (AEISR) NB02 ABLE LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Rx OOF RUR/ Change in Receive Out of Frame Defect Condition Interrupt Status.

  • Page 126: Table 118:: Alarm & Error Interrupt Enable Register (Aeier) Hex Address: 0Xnb03

    Line Code violation interrupt enable This bit permits the user to either enable or disable the “Line Code Viola- tion” interrupt within the XRT86VX38 device. If the user enables this inter- rupt, then the Receive T1 Framer block will generate an interrupt when Line Code Violation is detected.

  • Page 127: Table 119:: Framer Interrupt Status Register (Fisr) Hex Address: 0Xnb04

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 119: F (FISR) NB04 ABLE RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION DS0_Change Change in DS-0 Yellow Alarm Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in DS-0 Yellow Alarm”...
  • Page 128 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 119: F (FISR) NB04 ABLE RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION OOF_Status RUR/ Change in Receive Out of Frame Defect Condition Interrupt Status. This Reset-Upon-Read bit field indicates whether or not the “Change in Receive Out of Frame Defect Condition”...

  • Page 129: Table 120:: Framer Interrupt Enable Register (Fier) Hex Address: 0Xnb05

    Change in Signaling Bits Interrupt Enable This bit permits the user to either enable or disable the “Change in Sig- naling Bits” Interrupt, within the XRT86VX38 device. If the user enables this interrupt, then the Receive T1 Framer block will generate an inter- rupt when it detects a change in the any four signaling bits (A,B,C,D) in any one of the 24 signaling channels.
  • Page 130 Frame Mimic Detection Interrupt Enable This bit permits the user to either enable or disable the “Frame Mimic Detection” Interrupt, within the XRT86VX38 device. If the user enables this interrupt, then the Receive T1 Framer block will generate an inter- rupt when it detects the presence of Frame mimic bits (i.e., the payload...

  • Page 131: Table 121:: Data Link Status Register 1 (Dlsr1) Hex Address: 0Xnb06

    This READ ONLY bit indicates the type of data link message received by Receive HDLC 1 Controller. Two types of data link mes- sages are supported within the XRT86VX38 device: Message Ori- ented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Indicates Bit-Oriented Signaling (BOS) type data link message is...
  • Page 132 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 121: D 1 (DLSR1) NB06 ABLE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxEOT RUR/ Receive HDLC1 Controller End of Reception (RxEOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive HDLC1 Controller End of Reception (RxEOT) Interrupt has occurred since the last read of this register.

  • Page 133: Table 122:: Data Link Interrupt Enable Register 1 (Dlier1)

    Enable This bit enables or disables the “Receive HDLC1 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive HDLC1 Controller will generate an interrupt when it has started to receive a data link message.
  • Page 134 FCS Error Interrupt Enable This bit enables or disables the “Received FCS Error “Interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive HDLC1 Controller will generate an interrupt when it has detected the FCS error within the incoming data link message.

  • Page 135: Table 123:: Slip Buffer Interrupt Status Register (Sbisr) Hex Address: 0Xnb08

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 123: S (SBISR) NB08 ABLE UFFER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSB_FULL RUR/ Transmit Slip buffer Full Interrupt Status This Reset-Upon-Read bit indicates whether or not the Transmit Slip Buffer Full interrupt has occurred since the last read of this register.
  • Page 136 96 is in SYNC This READ ONLY bit field indicates whether or not frame synchroni- ® zation is achieved when the XRT86VX38 is configured in SLC framing mode. ® 0 = Indicates that frame synchronization is not achieved in SLC framing mode.
  • Page 137 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 123: S (SBISR) NB08 ABLE UFFER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSB_EMPT RUR/ Receive Slip buffer Empty Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer Empty interrupt has occurred since the last read of this regis- ter.

  • Page 138: Table 124:: Slip Buffer Interrupt Enable Register (Sbier) Hex Address: 0Xnb09

    Transmit Slip Buffer Full Interrupt Enable This bit enables or disables the Transmit Slip Buffer Full interrupt within the XRT86VX38 device. Once this interrupt is enabled, the transmit Slip Buffer Full interrupt is declared when the transmit slip buffer is filled. If the transmit slip buffer is full and a WRITE opera- tion occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ‘1’.
  • Page 139 Receive Slip Buffer Full Interrupt Enable This bit enables or disables the Receive Slip Buffer Full interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive Slip Buffer Full interrupt is declared when the receive slip buffer is filled. If the Receive slip buffer is full and a WRITE opera- tion occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ‘1’.

  • Page 140: Table 125:: Receive Loopback Code 0 Interrupt And Status Register (Rlcisr0) Hex Address: 0Xnb0A

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 125: R (RLCISR0) H NB0A ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 141: Table 126:: Receive Loopback Code 0 Interrupt Enable Register (Rlcier0) Hex Address: 0Xnb0B

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 126: R (RLCIER0) NB0B ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 142: Table 127:: Excessive Zero Status Register (Exzsr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 127: E (EXZSR) NB0E ABLE XCESSIVE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-1 Reserved Reserved EXZ_STATUS RUR/ Change in Excessive Zero Condition Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Excessive Zero Condition”...

  • Page 143: Table 129:: Ss7 Status Register For Lapd1 (Ss7Sr1)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 129: SS7 S LAPD1 (SS7SR1) NB10 ABLE TATUS EGISTER FOR DDRESS UNCTION EFAULT ESCRIPTION PERATION SS7_1_STATUS RUR/ SS7 Interrupt Status for LAPD Controller 1 This Reset-Upon-Read bit field indicates whether or not the “SS7”...

  • Page 144: Table 131:: Rxlos/Crc Interrupt Status Register (Rlcisr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 131: R LOS/CRC I (RLCISR) ABLE NTERRUPT TATUS EGISTER DDRESS NB12 UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved RxLOSINT RUR/ Change in Receive LOS condition Interrupt Status This bit indicates whether or not the “Change in Receive LOS condi- tion”...

  • Page 145: Table 133:: Receive Loopback Code 1 Interrupt And Status Register (Rlcisr1) Hex Address: 0Xnb14

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 133: R (RLCISR1) H NB14 ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 146: Table 134:: Receive Loopback Code 1 Interrupt Enable Register (Rlcier1) Hex Address: 0Xnb15

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 134: R (RLCIER1) NB15 ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 147: Table 135:: Data Link Status Register 2 (Dlsr2) Hex Address: 0Xnb16

    This READ ONLY bit indicates the type of data link message received by Receive HDLC 2 Controller. Two types of data link mes- sages are supported within the XRT86VX38 device: Message Ori- ented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Indicates Bit-Oriented Signaling (BOS) type data link message is...
  • Page 148 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 135: D 2 (DLSR2) NB16 ABLE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxEOT RUR/ Receive HDLC2 Controller End of Reception (RxEOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive HDLC2 Controller End of Reception (RxEOT) Interrupt has occurred since the last read of this register.

  • Page 149: Table 136:: Data Link Interrupt Enable Register 2 (Dlier2)

    Enable This bit enables or disables the “Receive HDLC2 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive HDLC2 Controller will generate an interrupt when it has started to receive a data link message.
  • Page 150 FCS Error Interrupt Enable This bit enables or disables the “Received FCS Error “Interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive HDLC2 Controller will generate an interrupt when it has detected the FCS error within the incoming data link message.

  • Page 151: Table 137:: Ss7 Status Register For Lapd2 (Ss7Sr2)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 137: SS7 S LAPD2 (SS7SR2) NB18 ABLE TATUS EGISTER FOR DDRESS UNCTION EFAULT ESCRIPTION PERATION SS7_2_STATUS RUR/ SS7 Interrupt Status for LAPD Controller 2 This Reset-Upon-Read bit field indicates whether or not the “SS7”...

  • Page 152: Table 139:: Receive Loopback Code 2 Interrupt And Status Register (Rlcisr2) Hex Address: 0Xnb1A

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 139: R (RLCISR2) H NB1A ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 153: Table 140:: Receive Loopback Code 2 Interrupt Enable Register (Rlcier2) Hex Address: 0Xnb1B

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 140: R (RLCIER2) NB1B ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 154: Table 141:: Receive Loopback Code 3 Interrupt And Status Register (Rlcisr3) Hex Address: 0Xnb1C

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 141: R (RLCISR3) H NB1C ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 155: Table 142:: Receive Loopback Code 3 Interrupt Enable Register (Rlcier3) Hex Address: 0Xnb1D

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 142: R (RLCIER3) NB1D ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 156: Table 143:: Receive Loopback Code 4 Interrupt And Status Register (Rlcisr4) Hex Address: 0Xnb1E

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 143: R (RLCISR4) H NB1E ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 157: Table 144:: Receive Loopback Code 4 Interrupt Enable Register (Rlcier4) Hex Address: 0Xnb1F

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 144: R (RLCIER4) NB1F ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 158: Table 145:: Receive Loopback Code 5 Interrupt And Status Register (Rlcisr5) Hex Address: 0Xnb20

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 145: R (RLCISR5) H NB20 ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 159: Table 146:: Receive Loopback Code 5 Interrupt Enable Register (Rlcier5) Hex Address: 0Xnb21

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 146: R (RLCIER5) NB21 ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 160: Table 147:: Receive Loopback Code 6 Interrupt And Status Register (Rlcisr6) Hex Address: 0Xnb22

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 147: R (RLCISR6) H NB22 ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 161: Table 148:: Receive Loopback Code 6 Interrupt Enable Register (Rlcier6) Hex Address: 0Xnb23

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 148: R (RLCIER6) NB23 ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 162: Table 149:: Receive Loopback Code 7 Interrupt And Status Register (Rlcisr7) Hex Address: 0Xnb24

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 149: R (RLCISR7) H NB24 ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-4 - Reserved (For E1 mode only) RXASTAT Receive Loopback Activation Code State...

  • Page 163: Table 150:: Receive Loopback Code 7 Interrupt Enable Register (Rlcier7) Hex Address: 0Xnb25

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 150: R (RLCIER7) NB25 ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-2 Reserved Reserved RXAENB Receive Loopback Activation Code Interrupt Enable This bit enables or disables the “Change in Receive Loopback Acti- vation Code”...

  • Page 164: Table 151:: Data Link Status Register 3 (Dlsr3) Hex Address: 0Xnb26

    This READ ONLY bit indicates the type of data link message received by Receive HDLC 3 Controller. Two types of data link messages are supported within the XRT86VX38 device: Message Oriented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Indicates Bit-Oriented Signaling (BOS) type data link message is...
  • Page 165 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 151: D 3 (DLSR3) NB26 ABLE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxEOT RUR/ Receive HDLC3 Controller End of Reception (RxEOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive HDLC3 Controller End of Reception (RxEOT) Interrupt has occurred since the last read of this register.

  • Page 166: Table 152:: Data Link Interrupt Enable Register 3 (Dlier3) Hex Address: 0Xnb27

    Enable This bit enables or disables the “Receive HDLC3 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive HDLC3 Controller will generate an interrupt when it has started to receive a data link message.
  • Page 167 FCS Error Interrupt Enable This bit enables or disables the “Received FCS Error “Interrupt within the XRT86VX38 device. Once this interrupt is enabled, the Receive HDLC3 Controller will generate an interrupt when it has detected the FCS error within the incoming data link message.

  • Page 168: Table 153:: Ss7 Status Register For Lapd3 (Ss7Sr3)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 153: SS7 S LAPD3 (SS7SR3) NB28 ABLE TATUS EGISTER FOR DDRESS UNCTION EFAULT ESCRIPTION PERATION SS7_3_STATUS RUR/ SS7 Interrupt Status for LAPD Controller 3 This Reset-Upon-Read bit field indicates whether or not the “SS7”...

  • Page 169: Table 155:: Customer Installation Alarm Status Register (Ciasr)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 155: C (CIASR) NB40 ABLE USTOMER NSTALLATION LARM TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:6] Reserved Reserved RxAIS-CI_state Receive Alarm Indication Signal-Customer Installation (AIS-CI) State This READ ONLY bit field indicates whether or not the Receive T1 Framer is currently detecting the Alarm Indication Signal-Customer Installation (AIS- CI) condition.

  • Page 170: Table 156:: Customer Installation Alarm Status Register (Ciaier)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 155: C (CIASR) NB40 ABLE USTOMER NSTALLATION LARM TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxAIS-CI RUR/ Change in Receive AIS-CI Condition Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in AIS- CI Condition”...

  • Page 171: Table 157:: T1 Boc Interrupt Status Register (Bocisr 0Xnb70H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 157: T1 BOC I (BOCISR 0 NB70 ABLE NTERRUPT TATUS EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RMTCH3 RMTCH2 BOCC RFDLAD RFDLF TFDLE RMTCH1 RBOC BIT 7 - Receive FDL Match 3 Event This bit is set when the receive FDL message is equal to the RFDL Match 3 message, and filter validation has occured.
  • Page 172 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 BIT 2 - TFDL Register Empty Event (Transmit End of Transfer) This bit is set when the TFDL register has been emptied according to amount of repetitions programmed into the TxBYTE count register 0xn178h.

  • Page 173: Table 158:: T1 Boc Interrupt Enable Register (Bocier 0Xnb71H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 158: T1 BOC I (BOCIER 0 NB71 ABLE NTERRUPT NABLE EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RMTCH3 RMTCH2 BOCC RFDLAD RFDLF TFDLE RMTCH1 RBOC BIT 7 - Receive FDL Match 3 Event This bit is used to enable the RFDL Match 3 message Interrupt.

  • Page 174: Table 159:: T1 Boc Unstable Interrupt Status Register (Bocuisr 0Xnb74H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 159: T1 BOC U (BOCUISR 0 NB74 ABLE NSTABLE NTERRUPT TATUS EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved Unstable Reserved BIT 7 - Reserved BIT 6 - Unstable SSM Message Interrupt Status This bit will be set to ’1’...

  • Page 175: Table 160:: T1 Boc Unstable Interrupt Enable Register (Bocuier 0Xnb75H)

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 160: T1 BOC U (BOCUIER 0 NB75 ABLE NSTABLE NTERRUPT NABLE EGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved Unstable Reserved BIT 7 - Reserved BIT 6 - Unstable SSM Message Interrupt Enable This bit is used to enable the Unstable SSM message Interrupt.
  • Page 176 Receiver ON: This bit permits the user to either turn on or turn off the Receive Sec- tion of XRT86VX38. If the user turns on the Receive Section, then XRT86VX38 will begin to receive the incoming data-stream via the RTIP and RRING input pins.

  • Page 177: Table 161:: Liu Channel Control Register 0 (Liuccr0)

    8 Arbitrary Pulse Segments provided in the LIU registers (0xNF08-0xNF0F), where n is the channel number. The XRT86VX38 device supports both long haul and short haul applications which can also be selected using the EQC[4:0] bits. Table 162 .presents the corresponding Transmit Line Build Out and...

  • Page 178: Table 162:: Equalizer Control And Transmit Line Build Out

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 162: E ABLE QUALIZER ONTROL AND RANSMIT UILD EQC[4:0] T1 M ECEIVE ENSITIVITY RANSMIT ABLE 0x00h T1 Long Haul/36dB 100TP 0x01h T1 Long Haul/36dB -7.5dB 100TP 0x02h T1 Long Haul/36dB -15dB 100TP...

  • Page 179: Table 163:: Liu Channel Control Register 1 (Liuccr1)

    Receive Jitter Attenuator Enable This bit permits the user to enable or disable the Jitter Attenuator in the Receive Path within the XRT86VX38 device. 0 = Disables the Jitter Attenuator to operate in the Receive Path within the Receive T1 LIU Block.
  • Page 180 Transmit Jitter Attenuator Enable This bit permits the user to enable or disable the Jitter Attenuator in the Transmit Path within the XRT86VX38 device. 0 = Disables the Jitter Attenuator to operate in the Transmit Path within the Transmit T1 LIU Block.

  • Page 181: Table 164: Liu Channel Control Register 2 (Liuccr2)

    Loop-Up Code of “00001” to the line for the selected channel num- ber n. When Network Loop-Up code is being transmitted, the XRT86VX38 will ignore the “Automatic Loop-Code detection and Remote Loop- Back activation” (NLCDE1 =“1”, NLCDE0 =“1” of register 0xNF03) in order to avoid activating Remote Digital Loop-Back automatically when the remote terminal responds to the Loop-Back request.
  • Page 182 This bit permits the user to either turn on or turn off the Transmit Driver of XRT86VX38. If the user turns on the Transmit Driver, then XRT86VX38 will begin to transmit T1 data (on the line) via the TTIP and TRING output pins.

  • Page 183: Table 165:: Liu Channel Control Register 3 (Liuccr3)

    Activation Enable: When this mode is enabled, the state of the NLCD bit (bit 3 of regis- ter 0xNF05) is reset to “0” and the XRT86VX38 is configured to monitor the receive data for the Loop-Up code. If the “00001” pattern is detected for longer than 5 seconds, then the NLCD bit (bit 3 of register 0xNF05) is set “1”, and Remote Loop-Back is activated.
  • Page 184 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 165: LIU C 3 (LIUCCR3) 0FN3 ABLE HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION INSBPV_n Insert Bipolar Violation: When this bit transitions from "0" to "1", a bipolar violation is inserted in the transmitted data stream of the selected channel number n.

  • Page 185: Table 166:: Liu Channel Control Interrupt Enable Register (Liuccier) Hex Address: 0X0Fn4

    This bit permits the user to either enable or disable the “Change of Transmit DMO Condition” Interrupt. If the user enables this interrupt, then the XRT86VX38 device will generate an interrupt any time when either one of the following events occur.
  • Page 186 This bit permits the user to either enable or disable the “Change of the Receive LOS Defect Condition” Interrupt. If the user enables this inter- rupt, then the XRT86VX38 device will generate an interrupt any time when either one of the following events occur.

  • Page 187: Table 167:: Liu Channel Control Status Register (Liuccsr) Hex Address: 0X0Fn5

    Transmit Out- put Line signal. 0 = Indicates that the Transmit Section of XRT86VX38 is NOT cur- rently declaring the Transmit DMO Alarm condition. 1 = Indicates that the Transmit Section of XRT86VX38 is currently declaring the Transmit DMO Alarm condition.
  • Page 188 Automatic Loop-code detection mode (i.e., If NLCDE1 = “1” and NLCDE0 =”1”), the state of the NLCD sta- tus bit is reset to “0” and the XRT86VX38 is programmed to monitor the receive input data for the Loop-Up code. This bit is set to a “1” to indicate that the Network Loop Code is detected for more than 5 seconds.
  • Page 189 This READ-ONLY bit indicates whether or not the Receive LIU Block is currently declaring the QRSS Pattern LOCK status. 0 = Indicates that the XRT86VX38 is NOT currently declaring the QRSS Pattern LOCK. 1 = Indicates that the XRT86VX38 is currently declaring the QRSS Pattern LOCK.
  • Page 190 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 168: LIU C (LIUCCISR) 0FN6 ABLE HANNEL ONTROL NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved DMOIS_n RUR/ Change of Transmit DMO (Drive Monitor Output) Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the “Change of...

  • Page 191: Table 168:: Liu Channel Control Interrupt Status Register (Liuccisr) Hex Address: 0X0Fn6

    XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 168: LIU C (LIUCCISR) 0FN6 ABLE HANNEL ONTROL NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AISDIS_n AIS Detection Interrupt Status: This bit is set to a "1" every time the AISD_n status has changed since the last read.

  • Page 192: Table 169:: Liu Channel Control Cable Loss Register (Liuccccr) Hex Address: 0X0Fn7

    Arbitrary Transmit Pulse Shape, Segment 2 These seven bits form the second of the eight segments of the transmit shape pulse when the XRT86VX38 is configured in “Arbi- trary Mode”. These seven bits represent the amplitude of the nth channel's arbi- trary pulse in signed magnitude format with Bit 6 as the sign bit and Bit 0 as the least significant bit (LSB).

  • Page 193: Table 172:: Liu Channel Control Arbitrary Register 3 (Liuccar3) Hex Address: 0X0Fna

    Arbitrary Transmit Pulse Shape, Segment 3 These seven bits form the third of the eight segments of the transmit shape pulse when the XRT86VX38 is configured in “Arbitrary Mode”. These seven bits represent the amplitude of the nth channel's arbi- trary pulse in signed magnitude format with Bit 6 as the sign bit and Bit 0 as the least significant bit (LSB).

  • Page 194: Table 175:: Liu Channel Control Arbitrary Register 6 (Liuccar6) Hex Address: 0X0Fnd

    Arbitrary Transmit Pulse Shape, Segment 7 These seven bits form the seventh of the eight segments of the transmit shape pulse when the XRT86VX38 is configured in “Arbi- trary Mode”. These seven bits represent the amplitude of the nth channel's arbi- trary pulse in signed magnitude format with Bit 6 as the sign bit and Bit 0 as the least significant bit (LSB).
  • Page 195 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 178: LIU G 0 (LIUGCR0) 0FE0 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Single Rail mode This bit must set to "1" for Single Rail mode to use LIU diagnotic fea- tures.
  • Page 196 Software Reset  P Registers: SRESET This bit allows users to reset the XRT86VX38 device. Writing a “1” to this bit and keeping it at ’1’ for longer than 10µs initiates a device reset through the microprocessor interface. Once the XRT86VX38 is reset, all internal circuits are placed in the reset state except the microprocessor register bits.
  • Page 197 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 179: LIU G 1 (LIUGCR1) 0FE1 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSYNC(Sect 13) G.703 Section 13 Transmit Pulse When this bit is set to ’1’, the LIU transmitter will send a T1 syn- chrnonous waveform as described in Section 13 of ITU-T G.703,...
  • Page 198 This bit allows users to tristate the output pins of all channels for in- circuit testing purposes. When In-Circuit-Testing is enabled, all output pins of the XRT86VX38 are “Tri-stated”. When In-Circuit-Testing is disabled, all output pins will resume to normal condition. 0 = Disables the In-Circuit-Testing Feature.
  • Page 199 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 182: LIU G 4 (LIUGCR4) 0FE9 ABLE LOBAL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved CLKSEL[3:0] 0001 Clock Select Input [3:0] These four bits allow users to select the programmable input clock rates for the MCLKIN input pin, according to the table below.
  • Page 200 Global Channel 0 Interrupt Status Indicator This Reset-Upon-Read bit field indicates whether or not an interrupt has occurred on Channel 0 within the XRT86VX38 device since the last read of this register. 0 = Indicates that No interrupt has occurred on Channel 0 within the XRT86VX38 device since the last read of this register.
  • Page 201 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 ORDERING INFORMATION RODUCT UMBER ACKAGE PERATING EMPERATURE ANGE   XRT86VX38IB256 256 PIn Fine Pitch Ball Grid Array C to +85   XRT86VX38IB329 329 PIn Fine Pitch Ball Grid Array...
  • Page 202 XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. 1.0.3 PACKAGE DIMENSIONS FOR 329 PIN FINE PITCH BALL GRID ARRAY 329 Fine Pitch Ball Grid Array (17.0 mm x 17.0 mm, fpBGA) Rev. 1.00 18 17 16 15 A1 corner...
  • Page 203 NPRM bit definitions to reg 0xN11D. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement.

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