Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics.
Page 4
Page 4 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 TECHNICAL MANUAL X19A-Q-002-05 Issue Date: 98/03/02...
EPSON Page 5 Vancouver Design Center Table of Contents INTRODUCTION SED1354 Color Graphics LCD / CRT Controller Product Brief SPECIFICATION SED1354 Hardware Functional Specification PROGRAMMER’S REFERENCE SED1354 Programming Notes and Examples SED1354 Register Summary UTILITIES 1354CFG.EXE File Configuration Program 1354SHOW Demonstration Program...
Page 6
Page 6 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 TECHNICAL MANUAL X19A-Q-002-05 Issue Date: 98/03/02...
Page 7
SED1354 COLOR GRAPHICS LCD/CRT CONTROLLER DESCRIPTION The SED1354 is a low cost, low power, color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The SED1354 architecture is designed to meet the requirements of embedded markets such as Office ®...
Fax: 02-712-9164 http://www.epson.co.jp Seiko Epson assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages.
The SED1354 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The SED1354 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system.
• Line-Doubling mode for simultaneous display of 240-line images on 240-line LCD and 480- line CRT. • Even-Scan and interlace modes for simultaneous display of 480-line images on 240-line LCD and 480-line CRT. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
• The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight – its power-on polarity is selected by an MD configuration pin. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
16-bit memory devices (FPM- DRAM or EDO-DRAM). 4.2.3 Display FIFO The Display FIFO block fetches display data from the Memory Controller for display refresh. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
The LCD Interface block performs frame rate modulation for passive LCD panels. It also generates the correct data format and timing control signals for various LCD and TFT panels. 4.2.6 Power Save The Power Save block contains the power save mode circuitry. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
• For MC68K Bus 2, this pin inputs the data strobe (DS#). • For Generic Bus, this pin inputs the write enable signal for the upper data byte (WE1#). See Table 5-7: “Host Bus Interface Pin Mapping,” on page 28. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
Page 29
Description This input pin is used to select between the memory and register address spaces of the SED1354. M/R# is set high to access the memory and low to M/R# access the registers. See Section 8.1, “Register Mapping” on page 87 .
100KΩ/100KΩ/120KΩ at 5.0V/3.3V/3.0V respectively) pull the reset states to 0. 56, 58, External pull-up resistors can be used to pull the reset states to 1. See Section 60, 62, 5.3, “Summary of Configuration Options” on page 27. 64, 66 SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
Page 31
• For symmetrical 2M byte DRAM and all 512K byte DRAM, this pin can be used as general purpose IO (GPIO2). See Table 5-8: “Memory Interface Pin Mapping,” on page 28 for summary. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Pin Name Type Pin # Driver Description Input clock for the internal pixel clock (PCLK) and memory clock CLKI (MCLK). PCLK and MCLK are derived from CLKI – see REG[19h] for details. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
This pin has multiple functions. • When MD9 = 0 at rising edge of RESET#, this pin is an active-low input used to place the SED1354 into suspend mode; see Section 13, “Power Save Modes” on page 124 for details.
Purpose IO (GPIO[11:4]). outputs. SUSPEND# pin configured as GPO output. SUSPEND# pin configured as SUSPEND# input. MD10 Active low LCDPWR or GPO polarities. Active high LCDPWR or GPO polarities. MD[15:11] Not used. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
EPSON Page 29 Vancouver Design Center Table 5-9: LCD, CRT, RAMDAC Interface Pin Mapping Monochrome Passive Color Passive Panel Panel Color TFT Panel SED1354 Single Single Pin Names Single Dual Single Dual Format 1 Format 2 4-bit 8-bit 8-bit 4-bit...
- 0.4 Type 2 - TS2, CO2 = -3 mA Type 3 - TS3, CO3 = -6 mA IO V = Max µA Output Leakage Current Output Pin Capacitance Bidirectional Pin Capacitance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Valid Hi-Z Hi-Z WAIT# Figure 7-1: SH-3 Read Bus Timing Note The SH-3 Wait State Control Register for the area in which the SED1354 resides must be set to a non-zero value. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
RD# rising edge to D[15:0] high impedance RD# falling edge to D[15:0] driven Read Data valid to WAIT# high BS# delay time CKIO to WAIT# low CKIO to WAIT# high CSn# high to WAIT# high impedance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Valid Hi-Z Hi-Z WAIT# Figure 7-2: SH-3 Write Bus Timing Note The SH-3 Wait State Control Register for the area in which the SED1354 resides must be set to a non-zero value. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
Write Enable delay time Write Data hold time 1 Write Data delay time Write Data hold time 2 BS# delay time CKIO to WAIT# low CKIO to WAIT# high CSn# high to WAIT# high impedance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
A[20:1], CS#, M/R# hold from AS# rising edge AS# low to DTACK# driven high CLK to DTACK# low AS# high to DTACK# high impedance AS# falling edge to D[15:0] valid D[15:0] hold from AS# rising edge SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
AS# low to DTACK# driven high CLK to DTACK# low AS# high to DTACK# high impedance UDS#/LDS# falling edge to D[15:0] driven D[15:0] valid to DTACK# falling edge UDS#/LDS# rising edge to D[15:0] high impedance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
AS#, DS# rising edge to R/W# rising edge AS# low to DSACK1# driven high CLK to DSACK1# low AS# high to DSACK1# high impedance R/W# falling edge to D[31:16] valid AS#, DS# rising edge to D[31:16] invalid SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
AS# low to DSACK1# driven high CLK to DSACK1# low AS# high to DSACK1# high impedance AS#, DS# falling edge to D[31:16] Read Data valid to DSACK1# low AS#, DS# rising edge to D[31:16] high impedance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
D[15:0] valid to WAIT# high RD0#, RD1# high to D[15:0] high impedance RD0#, RD1# low and CS# low to WAIT# driven low BCLK to WAIT# high RD0#, RD1# high to WAIT# high impedance SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
WE0#, WE1# high to A[20:0], CS#, M/R# invalid D[15:0] setup time D[15:0] hold from WE0#, WE1# high WE0#, WE1# low and CS# low to WAIT# driven low BCLK to WAIT# high WE0#, WE1# high to WAIT# high impedance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
RD0#, RD1# high to A[20:0], CS#, M/R# invalid RD0#, RD1# low to D[15:0] driven D[15:0] valid to WAIT# high RD0#, RD1# high to D[15:0] high impedance CS# low to WAIT# driven low RD0#, RD1# high to WAIT# high impedance SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
WE0#, WE1# high to A[20:0], CS#, M/R# invalid WE0#, WE1# low to D[15:0] valid D[15:0] hold from WE0#, WE1# high CS# low to WAIT# driven low WE0#, WE1# high to WAIT# high impedance Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read Timing Memory Clock RAS# CAS# MD(Read) Figure 7-12: EDO-DRAM Read Timing SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
2.45 t1 - 12 Access time from CAS# t1 - 10 1.45 t1 - 6 Access time from CAS# precharge, column address Read Data hold after CAS# low Read Data turn-off delay from RAS# Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
1.55 t1 0.45 t1 - 1 Write command setup time 0.45 t1 Write command hold time 0.45 t1 - 3 Write Data setup time 0.45 t1 - 2 Write Data hold time Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
1.55 t1 Read Data turn-off delay from WE# 1.45 t1 Write Data delay from WE# (REG[22h] bit 7 = 0) 0.45 t1 Write Data delay from WE# (REG[22h] bit 7 = 1) Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 01) 0.45 t1 - 1 Access time from CAS# 1 t1 - 2 Access time from CAS# precharge Read Data hold from CAS# or RAS# Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
2 t1 Write command setup time 0.45 t1 - 1 Write command hold time 0.45 t1 Write Data setup time 0.45 t1 - 3 Write Data hold time 0.45 t1 - 2 Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on Frames and FPFRAME active Note Where T is the period of FPFRAME and T is the period of the pixel clock. FPFRAME PCLK SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
1. t3, t5, and t7 are measured from the first CLKI after SUSPEND# inactive. 2. CLKI may be active throughout SUSPEND# active. 3. Where MCLK is the period of the memory clock. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
EPSON Page 81 Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Figure 7-43: TFT A.C. Timing Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
8 Registers 8.1 Register Mapping The SED1354 registers are all memory mapped. The system must provide the external address decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001.
When this bit = 1, 2-WE# DRAM is selected. When this bit = 0 2-CAS# DRAM is selected. bit 0 Memory Type When this bit = 1, FPM-DRAM is selected. When this bit = 0, EDO-DRAM is selected. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal. When these bits are all 0’s the MOD output signal toggles every FPFRAME. These bits are for passive LCD panels only. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Page 98
HRTC pulse and FPLINE pulse respectively. HRTC/FPLINE start position (pixels) = (HRTC/FPLINE Start Position Bits [4:0] + 1) × 8. The maximum HRTC start delay is 256 pixels. Note REG[05h] ≥ REG[06h] + REG[07h] bits [3:0]. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
LCD panel only configuration, this register should be programmed to half the panel size. Vertical display height in number of lines = (ContentsOfThisRegister) + 1. The maximum vertical display height is 1024 lines. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Page 100
LCDs, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1. The maximum VRTC start delay is 64 lines. Note REG[0Ah] bits [5:0] ≥ REG[0Bh] + REG[0Ch] bits [2:0]. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
Even Scan Only - the 640x480 image on the CRT is normal. The LCD (640x240) only receives the even scan lines. The image on the LCD does not flicker, but it may be hard to read text. SED1354 Hardware Functional Specification...
This bit enables the LCD control signals. Programming this bit from a 0 to a 1 starts the LCD power-on sequence. Programming this bit from a 1 to a 0 starts the LCD power-off sequence. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Page 104
Address registers. The starting address for screen 2 is given by the Screen 2 Display Start Address registers. See Section 10.2, “Image Manipulation” on page 114 and SED1354 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for more details.
Page 105
A virtual image can be formed by setting this register to a value greater than the width of the dis- play. The displayed image is a window into the larger virtual image. See Section 10, “Display Configuration” on page 112 for details. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
15/16 Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address register. See Section 10, “Display Configuration” on page 112 and SED1354 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details.
Disabling the half frame buffer results in reduced contrast on the LCD panel. This mode is not nor- mally used except in special circumstances such as simultaneous display on CRT and dual panel LCD. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Page 108
Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware. SED1354 Hardware Functional Specification X19A-A-002-06...
Page 109
Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Page 110
When GPIO0 is configured as an output, a “1” in this bit drives GPIO0 to high and a “0” in this bit drives GPIO0 to low. When GPIO0 is configured as an input, a read from this bit returns the status of GPIO0. SED1354 Hardware Functional Specification X19A-A-002-06...
Page 111
LCD backlight power: • When MD9 = 0 at rising edge of RESET#, SUSPEND# is an active-low Schmitt input used to put the SED1354 into suspend mode - see Section 13, “Power Save Modes” on page 124 for details.
= 1 or 2 = (1.5) T if EDO and N = 1.5 = (N + 0.5) T if FPM and N = 1 or 2 = (N if FPM and N = 1.5 SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
DRAM types, at maximum MCLK frequencies. Table 8-14: Optimal N , and N Values at Maximum MCLK Frequency DRAM Speed DRAM Type (ns) (ns) (#MCLK) (#MCLK) (#MCLK) bit 0 Reserved Must be set to 0 Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen is blanked). This allows the SED1354 to be dedicated to service CPU to memory accesses. When this bit = 0 the display FIFO is enabled.
Page 115
In 8-bpp mode, the 16 position Green LUT is arranged into two, 8 position “banks.” Only bit 0 of these two bits controls which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, and 15/16-bpp modes. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
DAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system. SED1354 Hardware Functional Specification X19A-A-002-06 Issue Date: 98/02/12...
Page 117
RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following table. Table 9-1: SED1354 Addressing M/R# Access Register access: •...
For example, for a 800x600 color panel the half frame buffer size is 120,000 bytes. In a 512K byte display buffer, the half-frame buffer resides from 62B40h to 7FFFFh. In a 2M byte display buffer, the half-frame buffer resides from 1E2B40h to 1FFFFFh. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization Note The Host-to-Display mapping described here assumes that a Little-Endian interface is being used. For 8/15/16 bit-per-pixel formats, R represent the red, green, and blue color components. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
Page 125
Half Frame Buffer is disabled by REG[1Bh] bit 0. CRT frame rates below 58Hz are deemed unacceptable and are not recorded here. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
EPSON Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the SED1354 to accommodate the important need for power reduction in the hand-held devices market. These modes are hardware suspend and software suspend. 13.1 Hardware Suspend •...
REG[07h] bit 6 respectively. Selectable: may be CBR refresh, self-refresh or no refresh at all. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled. Active for non-DAC register access only. Hardware Functional Specification SED1354 Issue Date: 98/02/12 X19A-A-002-06...
The second half of this guide introduces the Hardware Abstraction Layer (HAL), designed to make programming the SED1354 as easy as possible. Future SED135x products will support the HAL which will allow OEMs the ability to upgrade to future chips with relative ease.
• An “implementation specific” value is one required for the hardware implementation of the SED1354. Such a value must never change after initialization of all registers. Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx, and SDU1354B0C Evaluation Board User Manual, document number X19A-G-004-xx for more information on hardware implementation issues.
Page 143
1024 lines (offscreen). In normal operation, page 28 REG[0Fh] 0000 0011 these register bits should be programmed to the maximum value. • REG[0Fh] bits [7:2] = 0000 00 = n/a Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 144
• bits [6:4] = 000 = n/a page 30 and “CRT 0000 0000 Considerations” on page • bits [3:0] = 0000 = set GPIO[11:8] pins low when GPIOx is set to output SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 145
“LCD Power REG[1Ah] • b3 = 0 = LCD Power Enable (polarity is MD10 dependent) Sequencing and Power 0000 0000 Save Modes” on page 30 • bits [2:0] = unchanged Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
3.1 Display Buffer Location The SED1354 requires either a 512K byte or a 2M byte block of memory to be decoded by the system. System logic will determine the location of this memory block; the SDU1354B0C evalu- ation board decodes the display buffer at the 12M byte location of system memory.
LUT, and the blue bits represent an index into the blue LUT. Although eight bit- per-pixel only makes sense for a color panel, this memory model can be set on a monochrome panel, however only eight shades of gray will be visible. Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
The output bypasses the LUT and goes directly into the Frame Rate Modulator. Although 16 bit-per-pixel only make sense for a color panel, this memory model can be set on a monochrome panel, however only 16 shades of gray will be visible. SED1354 Programming Notes and Examples X19A-G-002-04...
Select Bit 1 Select Bit 0 The SED1354 LUT Registers are located at offsets 24h, 26h and 27h. They consist of a LUT address register, data register and bank register. Refer to the SED1354 Hardware Functional Specification document number X19A-A-002-xx for more details.
Page 150
To program index 3 of the current LUT, with Green bank select bits set to 11b and 2 bpp gray shade mode selected, you would program LUT address to [[3(bank select value)*4(entries in LUT]+3(index to modify)-1(to zero-base the value)]=14(0Eh). SED1354 Programming Notes and Examples X19A-G-002-04...
0 and 0Fh. • The SED1354 LUT is linear; increasing the LUT number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red Look-Up entry will always result in a bright red output.
Page 152
Vancouver Design Center Color Modes In color mode, the SED1354 supports three, 16 position, 4 bit wide color LUTs (red, green, and blue). Depending on the selected pixel size, these LUTs will provide from 1 to 4 banks. 1 bpp Color In 1 bpp color mode, the LUT is limited to a single 2 entry bank per color.
Page 153
[1:0] represent the blue LUT index. It is recommended that the three LUTs are programmed according to the following format: Table 3-11: Recommended LUT Values For 8 bpp Color Mode Address Green Blue bank 1 bank 1 bank 1 bank 1 Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 154
=4096 colors. Gray Shade Modes In gray shade mode, the SED1354 treats the Green LUT as a 16 position, 4 bit wide monochrome LUT. Depending on the selected pixel size, this LUT will provide from 1 to 4 banks. 1 bpp Gray Shade The SED1354 has no true Black-and-White mode.
Page 155
8 bpp Gray Shade When the SED1354 is configured for 8 bpp gray shade mode, bits [7:5] are ignored, bits [4:2] represent the green LUT index, and bits [1:0] are ignored. Only 3 bits of the 8 that actually represent any shade value, therefore the maximum gray shade combination is 8 shades.
Page 156
Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data. Resulting in a maximum of 2 =16 colors. SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
The size of the virtual display is limited by the amount of available display buffer. In the case of an SED1354 with 2M byte of display buffer, the maximum virtual width ranges from 16,368 pixels in 1 bpp mode to 1023 pixels in 16 bpp mode. The maximum vertical size at the horizontal maximum is 1025 lines.
Initialize the SED1354 registers for a 320x240 panel. (See Initializing the SED1354 on page 8). Determine the number of words required per line (the offset). In this case we want a width of 640 pixels and there are four pixels to every word.
Update the pixel paning register. Note The SED1354 provides a false indication of vertical non-display period when used with a dual panel display. In this case it is impossible to identify the false signal from the true non-display period. The result is that panning operations at less than 15 bpp may exhibit an occasional tear as the result of updating registers in the wrong order.
The following table shows this. Table 4-2: Active Pixel Pan Bits Color Depth (bpp) Pixel Pan bits used bits [3:0] bits [2:0] bits [1:0] bit 0 15/16 SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x200 viewport. Refer to Section 2, “Initializing the SED1354” on page 8 and Section 4.1, “Virtual Display” on page 23 for assistance with these settings.
The Split Screen feature of the SED1354 allows a programmer to set up a display for such an appli- cation. The figure below illustrates setting up a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239.
Set the screen 2 start address to the value we just calculated. Write the screen 2 start address registers [13h], [14h] and [15h] with the values 0x00, 0x4B and 0x00 respectively. Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
The SED1354 requires a timer between the time the LCD power is disabled and the time the LCD signals are shut down. Conversely, the LCD signals must be active prior to the power supply starting up. For simplicity, we have chosen to use the same time value for power up and power down procedures.
Set REG[0Dh] bit 0 to 1. This turns on the LCD outputs. Count x Vertical Non-Display Periods (VNDP); x corresponds to your power supply discharge time in Vertical Non-Display Periods. Set REG[1Ah] bit 3 to 0. This enables LCD Power. Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Deactivate Hardware Suspend through external circuitry. Count x Vertical Non-Display Periods (VNDP); x corresponds to your power supply discharge time in Vertical Non-Display Periods. Set REG[1Ah] bit 3 to 0. This enables LCD Power. SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
6 CRT Considerations 6.1 Introduction The CRT timing is based on both the “VESA Monitor Timing Standards Version 1.0” and “Frame Rate Calculation (Chapter 11)” in SED1354 Hardware Functional Specification. The following sections describe CRT considerations. 6.1.1 CRT Only For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set to single passive LCD panel.
40 MHz and 85 Hz respectively. When pixel depth is less than 8 bpp, the RAMDAC is programmed with the same values as the Look-Up Table. The SED1354 does not support Simulta- neous Display in a color depth greater than 8 bpp.
Page 169
EPSON Page 35 Vancouver Design Center Table 6-3: 8 bpp Recommended RAMDAC palette data for Simultaneous Display Address Address Address Address Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 170
Page 36 EPSON Vancouver Design Center Addres Addres Addres Addres SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 171
REG[26h] load look-up table REG[27h] set look-up table to bank 0 0000 0000 0000 0000 program program REG[2Ch] set write mode address to 0 RAMDAC RAMDAC REG[2Eh] load RAMDAC palette data Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Vancouver Design Center 7 Identifying the SED1354 Unlike previous generations of SED135x products, the SED1354 can be identified at any time after power on / reset. The SED1354 and future SED135x products can be identified by reading REG[00h]. The value of this register for the SED1354F0A is 04h.
The HAL is a processor independent programming library provided by Seiko Epson. HAL provides an easy method to program and configure the SED1354. HAL allows easy porting from one SED135x product to another and between system architectures. HAL is included in the utilities provided with the SED1354 evaluation system.
Page 174
Device - pointer to an allocated INT. This routine will set *Device to the registered device ID. Return Value: ERR_OK - operation completed with no problems ERR_INVALID_STD_DEVICE - device argument is not HAL_STDOUT or HAL_STDIN Note No registers are actually changed by calling seRegisterDevice(). SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
NewState - use the predefined definitions ENABLE and DISABLE. Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid ERR_FAILED - unable to complete operation because registers have not been initialized Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 176
Parameter: device - registered device ID pDispLogicalAddr - logical address is returned in this variable. Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 177
- offset from start of the display buffer pDword - returns value of dword. Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid. Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 178
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_HAL_BAD_ARG - argument VisibleScanlines is negative or is greater than vertical panel size. Note seSplitInit() must have been called once before calling seSplitScreen(). SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 179
- bpp is invalid in HAL structure (this would occur if the application changed the registers directly instead of calling seSetBitsPerPixel()). Note seVirtInit() must have been called once before calling seVirtMove(). Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 180
- offset from start of the display buffer val - value to write count - number of dwords to write Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
- pointer to an array of BYTE lut[16][3] lut[x][0] == RED component lut[x][1] == GREEN component lut[x][2] == BLUE component Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 182
- pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 183
GreenMask - all bits set to 1 are used by the green component. BlueMask - all bits set to 1 are used by the blue component. Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_INVALID_STD_DEVICE - device is not HAL_STDOUT or HAL_STDIN (but don't use HAL_STDIN for seDrawText()). Note seDrawText() currently doesn't write text to the display buffer. SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 185
Writes a character to platform (typically to a terminal). Parameter: device - registered device ID ch - character to send to platform Return Value: ERR_OK - operation completed with no problems ERR_FAILED - operation failed Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Seconds - delay time in seconds Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_FAILED - registers have not been initialized (for non-Intel platforms). SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 187
Rotates the bits in "val" right as many times as stated in "bits". Parameter: val - value to rotate bits - how many bits to rotate Return Value: bits 15-8: non-zero if carry flag set bits 7-0: rotated byte Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Vancouver Design Center 9 Sample Code 9.1 Introduction The following code samples demonstrate two approaches to initializing the SED1354 color graphics controller with/without using the 1354HAL API. These code samples are for example purposes only. 9.1.1 Sample code using 1354HAL API **------------------------------------------------------------------------- Created 1998, Epson Research &...
EPSON Page 55 Vancouver Design Center if (ChipId != ID_SED1354F0A) printf("ERROR: Did not detect SED1354.\n"); exit(1); if (seSetInit(Device) != ERR_OK) printf("ERROR: Could not initialize device.\n"); exit(1); /*************************************************************************** * Fill 2 MBytes of memory with 0xffffffff (white) * Note that 0x200000 == 2 M bytes. Divide by 4 for number of Dwords to fill ***************************************************************************/ seWriteDisplayDwords(Device, 0, 0xffffffff, 0x200000/4);...
Page 194
* 4 blue values are used. * Setup the pointer to the LUT data and reset the LUT index * register.Then, loop writing each of the RGB LUT data elements. *********************************************************************/ SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 195
/* Fill 2 M bytes of display buffer with 0xFF (white) */ pRegs = pRegs + DISP_MEMORY_OFFSET; for ( lLoopCounter = 0; lLoopCounter < DISP_MEMORY_SIZE; lLoopCounter++ ) *pRegs = 0xFF; pLUT++; Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Look-Up Table address to 0 0000 0000 0000 0000 0000 0000 REG[26h] load Look-Up Table load LUT load LUT load LUT REG[27h] set Look-Up Table to bank 0 0000 0000 0000 0000 0000 0000 SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 197
MCLK and PCLK divide 0000 0001 REG[24h] set Look-Up Table address to 0 0000 0000 REG[26h] load Look-Up Table load LUT REG[27h] set Look-Up Table to bank 0 0000 0000 Programming Notes and Examples SED1354 Issue Date: 98/04/14 X19A-G-002-04...
Page 198
Page 64 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 Programming Notes and Examples X19A-G-002-04 Issue Date: 98/04/14...
Page 199
Suspend Bit 1 Bit 0 2 These bits are used to identify the SED1354 at power on / RESET. Bit 9 Bit 8 3 When using Little-Endian the RAMDAC should be connected to the low byte of the CPU data bus and the lower...
Page 200
SED1354F0A Register Summary X19A-Q-001-02 6 Simultaneous Display Option Selection Simultaneous Display Option Simultaneous Display Option Select Bits [1:0] Normal Line Doubling Interlace Even Scan Only 7 Number of Bits per Pixel Selection Number Of Bits/Pixel Select Bits [2:0] Number of Bits/Pixel 110-111 Reserved 8 PCLK Divide Selection...
1354CFG gives a software/hardware developer an easy way to modify panel types, modes, etc. for the SED1354 utilities without recompiling. Once the correct operating environment has been deter- mined, the software/hardware developer can modify the source code manually for a permanent change.
1354 utility to be modified filename.exe is the list of HAL configuration changes script.ini (see See “Script Mode” on page 9) displays the usage screen no argument runs 1354CFG in the interactive mode SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
The full list of all the possible parameters to 1354CFG is included in the file 1354.INI. 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
<Alt> <V> to select the View menu. <Alt> <D> to select the Device menu. <Alt> <H> to select the Help menu. <↑>, <↓>, or the highlighted letter in the menu to select a menu item. SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
• Press <Tab> to highlight the Files box (or press <Alt><F>). Press <↓> to highlight 1354SHOW.EXE. Press <Enter>. All selections in 1354CFG can be made in one of the three ways listed above. Figure 2: 1354CFG Open File 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
• Save All - saves modifications to all 1354 files that are in the same directory as the file being saved. This function ensures that the display parameters are consistent. “Save All” is only avail- able for utilities run on an Intel (EXE) platform. • Exit - exits the 1354CFG application. SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
Examples” manual, document number X19A-G-002-xx for formulas and other information. Note Epson R&D Inc. cannot be held liable for damage done to the display as a result of software con- figuration errors. Cancel and Print commands are available in the Current/Advanced Configuration windows. Help is listed, but is not available for this version of 1354CFG.
Page 214
Page 14 EPSON Vancouver Design Center Figure 5: 1354CFG Current Configuration Figure 6: 1354CFG Advanced Configuration (Partial View of Screen) SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
EPSON Page 15 Vancouver Design Center Device Menu Figure 7: 1354CFG Device Menu The Device menu contains the following sub-menus where parameters for a SED1354 utility can be edited: • Panel • CRT • Advanced Memory • Power Management • Look-Up Table •...
Page 216
In addition to OK, Cancel, and Edit commands, a Help command is listed in the Panel Setup windows. In this version of 1354CFG, the Help files are unavailable. Figure 8: 1354CFG Panel Setup SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
Page 217
Panel Parameter Edit window displays for parameter editing. See figure 10, “1354CFG Panel Parameter Edit” below. In this example window, “X Resolution: 320 pixels” can be edited. Figure 10: 1354CFG Panel Parameter Edit 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
Page 218
In addition to OK, Cancel, and Edit commands, a Help command is listed in the CRT setup windows. In this version of 1354CFG, the Help files are unavailable. Figure 11: 1354CFG CRT Setup SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
Page 219
CRT Parameter Edit window displays for parameter editing. See figure 13, “1354CFG CRT Parameter Edit” below. In this example window, “Horiz Non-Display: 240 pixels” can be edited. Figure 13: 1354CFG CRT Parameter Edit 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
Page 220
In addition to OK, Cancel, and Edit commands, a Help command is listed in the Memory setup windows. In this version of 1354CFG, the Help files are unavailable. Figure 14: 1354CFG Advanced Memory Setup SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
Page 221
Memory Parameter Edit window is displayed for parameter editing. See figure 16, “1354CFG Memory Parameter Edit” below. In this example window, “Refresh Time: 4000 Cycles” can be edited. Figure 16: 1354CFG Memory Parameter Edit 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
In addition to OK, Cancel, and Edit commands, a Help command is listed in the Power setup windows. In this version of 1354CFG, the Help files are unavailable. Figure 17: 1354CFG Power Setup SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
Page 223
Power Parameter Edit window displays for parameter editing. See figure 19, “1354CFG Power Parameter Edit” below. In this example window, “Suspend Refresh: CBR Refresh” can be edited. Figure 19: 1354CFG Power Parameter Edit 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
In addition to OK, Cancel, and Edit commands, a Help command is listed in the LUT setup windows. In this version of 1354CFG, the Help files are unavailable. Figure 20: 1354CFG LUT Setup SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
Page 225
LUT Parameter Edit window displays for parameter editing. See figure 22, “1354CFG LUT Parameter Edit” below. In this example window, “Bits Per Pixel: 2” can be edited. Figure 22: 1354CFG LUT Parameter Edit 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
Edit and see the next section “Setup Parameter Edit.” In addition to OK, Cancel, and Edit commands, a Help command is listed in the Setup windows. In this version of 1354CFG, the Help files are unavailable. Figure 23: 1354CFG Setup SED1354 1354CFG.EXE Configuration Program X19A-B-001-02 Issue Date: 97/12/11...
There are three files in the Help menu. • Help: not available in this version of 1354CFG. • Help on Help: not available in this version of 1354CFG. • About: displays copyright and program version information. 1354CFG.EXE Configuration Program SED1354 Issue Date: 97/12/11 X19A-B-001-02...
Vancouver Design Center Comments It is assumed that the 1354CFG user is familiar with SED1354 hardware and software. Refer to the SED1354 “Functional Hardware Specification,” document number X19A-A-002-xx, and the SED1354 “Programming Notes and Examples” manual, document number X19A-G-002-xx for information.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 1354SHOW.EXE to a directory that is in the DOS path on your hard...
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
Page 234
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354SPLT Display Utility X19A-B-003-03 Issue Date: 98/02/12...
Page 235
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 1354SPLT.EXE to a directory that is in the DOS path on your hard drive.
Page 236
Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel. Repeat step 2 for the remaining bits-per-pixel colour depths: 1, 2, 4, 8, 15, and 16. Press <ESC> to exit the program. SED1354 1354SPLT Display Utility X19A-B-003-03 Issue Date: 98/02/12...
Page 237
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
Page 238
Page 6 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354SPLT Display Utility X19A-B-003-03 Issue Date: 98/02/12...
Page 240
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354VIRT Display Utility X19A-B-004-03 Issue Date: 98/02/12...
Page 241
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 1354VIRT.EXE to a directory that is in the DOS path on your hard drive.
Page 242
Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel. 3. Repeat steps 1 and 2 for the following bits-per-pixel values: 1, 2, 4, 8, 15, and 16. Press <ESC> to exit the program. SED1354 1354VIRT Display Utility X19A-B-004-03 Issue Date: 98/02/12...
Page 243
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
Page 244
Page 6 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354VIRT Display Utility X19A-B-004-03 Issue Date: 98/02/12...
Page 246
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354PLAY Diagnostic Utility X19A-B-005-03 Issue Date: 98/02/17...
Page 247
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 1354PLAY.EXE to a directory that is in the DOS path on your hard...
Page 248
1 2 3 4 starting at address 0). - Initializes the chip with user specified configuration. - Gets current mode information. M [bpp] - If “bpp” is specified then set that pixel depth. SED1354 1354PLAY Diagnostic Utility X19A-B-005-03 Issue Date: 98/02/17...
Page 249
This causes the file “dumpregs.scr” to be interpreted and the results to be sent to the file “results.” Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the SED1354 and reads the registers ; Note: after a semi-colon (;), all characters on a line are ignored...
Page 250
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached. Program Messages ERROR: Too many devices registered.
Page 252
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354BMP Demonstration Program X19A-B-006-02 Issue Date: 97/12/23...
Page 253
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached. 1354BMP Demonstration Program...
Page 254
A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly. SED1354...
Page 256
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354PWR Software Suspend Power Sequencing Utility X19A-B-007-02 Issue Date: 97/12/23...
Page 257
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. • SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 “Programming Notes and Examples” manual, document number X19A-G-002-xx. Installation PC platform: copy the file 1354PWR.EXE to a directory that is in the DOS path on your hard drive.
Page 258
CRT timing values will have to be changed to more closely match the panel's timing. • A CRT cannot show 15 or 16 bits-per-pixel. • Do not attach a 16-bit panel when using the CRT. SED1354 1354PWR Software Suspend Power Sequencing Utility X19A-B-007-02 Issue Date: 97/12/23...
Page 259
1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly. 1354PWR Software Suspend Power Sequencing Utility...
Page 260
Page 6 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 1354PWR Software Suspend Power Sequencing Utility X19A-B-007-02 Issue Date: 97/12/23...
Page 262
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-03 Issue Date: 98/02/03...
Page 263
Schematic Diagrams ........19 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual SED1354 Issue Date: 98/02/03...
Page 264
Page 4 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-03 Issue Date: 98/02/03...
Page 265
SED1354B0C Schematic Diagram (6 of 6) ..........24 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual SED1354 Issue Date: 98/02/03...
Page 266
Page 6 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-03 Issue Date: 98/02/03...
Page 267
This manual describes the setup and operation of the SDU1354B0C Rev. 1.0 Evaluation Board when used with the SED1354 Color Graphics LCD/CRT Controller in the ISA bus environment. For more information regarding the SED1354, refer to the SED1354 Hardware Functional Specifi- cation, document number X19A-A-002-xx.
Vancouver Design Center 2 Installation and Configuration The SED1354 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. SED1354 configuration inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one five-position DIP switch is provided for this purpose. All remaining config- uration inputs are hard-wired.
Page 269
EPSON Page 9 Vancouver Design Center 3 LCD / RAMDAC Interface Pin Mapping Table 3-1: LCD Signal Connector (J6) Color TFT Color Passive Mono Passive External SED1354 Connector RAMDAC Pin Names Pin No. 9-bit 12-bit 18-bit 4-bit 8-bit 16-bit 4-bit...
4 CPU / BUS Interface Connector Pinouts Table 4-1: CPU/BUS Connector (H1) Pinout Connector Comments Pin No. Connected to DB0 of the SED1354 Connected to DB1 of the SED1354 Connected to DB2 of the SED1354 Connected to DB3 of the SED1354 Ground...
Page 271
Table 4-2: CPU/BUS Connector (H2) Pinout Connector Comments Pin No. Connected to AB0 of the SED1354 Connected to AB1 of the SED1354 Connected to AB2 of the SED1354 Connected to AB3 of the SED1354 Connected to AB4 of the SED1354...
Voltage lines are provided on the header strips. • U3, a TIBPAL22V10 PAL, is currently used to provide the SED1354 CS# (pin 4), M/R# (pin 5) and other decode logic signals for ISA bus use. This functionality must now be provided exter- nally;...
Page 274
Vancouver Design Center 6.3 DRAM Support The SED1354 supports 256K x 16 as well as 1M x 16 DRAM (FPM and EDO) in symmetrical and asymmetrical formats. The SDU1354B0C board supports 5.0V 1M x 16 EDO-DRAM (42-pin SOJ package) in symmet- rical format, providing a 2M byte display buffer.
Page 275
When supporting an 18-bit TFT panel, the SED1354 can display 64K of a possible 262K colors. A maximum 16 of the possible 18-bits of LCD data is available from the SED1354. Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for details.
6.15 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the SED1354 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus. Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout,” on page 10 and Table 4-2 “CPU/BUS Connector (H2) Pinout,”...
EPSON Page 19 Vancouver Design Center 8 Schematic Diagrams Figure 1: SED1354B0C Schematic Diagram (1 of 6) SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual SED1354 Issue Date: 98/02/03 X19A-G-004-03...
Page 280
Page 20 EPSON Vancouver Design Center Figure 2: SED1354B0C Schematic Diagram (2 of 6) SED1354 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-03 Issue Date: 98/02/03...
Page 281
EPSON Page 21 Vancouver Design Center Figure 3: SED1354B0C Schematic Diagram (3 of 6) SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual SED1354 Issue Date: 98/02/03 X19A-G-004-03...
Page 282
Page 22 EPSON Vancouver Design Center Figure 4: SED1354B0C Schematic Diagram (4 of 6) SED1354 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-03 Issue Date: 98/02/03...
Page 283
EPSON Page 23 Vancouver Design Center Figure 5: SED1354B0C Schematic Diagram (5 of 6) SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual SED1354 Issue Date: 98/02/03 X19A-G-004-03...
Page 284
Page 24 EPSON Vancouver Design Center Figure 6: SED1354B0C Schematic Diagram (6 of 6) SED1354 SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual X19A-G-004-03 Issue Date: 98/02/03...
FPGA / processor combination. This manual describes how the SDU1354-D9000 Evaluation Board is used to provide a color LCD solution for the Windows CE environment. Reference SED1354 Hardware Functional Specification, document number X19A-A-002-xx. D9000 Development System, Hardware User Manual - Hitachi. Evaluation Board User Manual...
• SmallTypeZ x 2 form factor (requires two side-by-side SmallTypeZ slots). 2.1 SED1354 Color Graphics LCD Controller The SED1354 is a low cost, low power color / monochrome LCD / CRT controller capable of inter- facing to a wide range of CPUs and LCD displays.
EPSON Page 9 Vancouver Design Center 2.1.2 LCD Display Support The SED1354 provides a wide range of flexibility for display type and resolution. Display types include: • 4/8-bit monochrome passive. • 4/8/16-bit color passive. • Active matrix TFT. • other (EL, REC, etc.).
Page 11 Vancouver Design Center 2.1.4 CRT Support The SED1354 has all the necessary signals to interface to an external RAMDAC so a CRT is supported. The Brooktree Bt481A RAMDAC is supported on the SDU1354-D9000 evaluation board. Refer to the Programming Notes and Examples, document number X19A-G-002-xx for programming details.
Vancouver Design Center 3 D9000 Specifics 3.1 Interface Signals The SED1354 is intended for direct connection to most processors, so the FPGA in this environment simply acts as a pass-through for the required processor interface signals. Table 3-1: Interface Signals...
EPSON Page 13 Vancouver Design Center 3.1.1 Connector Pinout for Channel A10 and A11 Table 3-2: Connector Pinout for Channel A10 Channel A10 Pin # FPGA Signal SED1354 Signal Pin # FPGA Signal SED1354 Signal SmXY chA10p1 BCLK dc5v DC5V...
Page 298
Page 14 EPSON Vancouver Design Center Table 3-2: Connector Pinout for Channel A10 (Continued) Channel A10 Pin # FPGA Signal SED1354 Signal Pin # FPGA Signal SED1354 Signal chA10p11 chA10p12 chA10p13 chA10p34 chA10p14 chA10p15 chA10p16 chA10p17 chA10p33 chA10p18 chA10p19 chA10p20...
Page 299
EPSON Page 15 Vancouver Design Center Table 3-3: Connectors Pinout for Channel A11 Channel A11 Pin # FPGA Signal SED1354 Signal Pin # FPGA Signal SED1354 Signal SmXY chA11p1 dc5v DC5V chA11p2 chA11p3 WE0# dc3v DC3V chA11p4 RD/WR# chA11p5 WAIT#...
Page 300
Page 16 EPSON Vancouver Design Center Table 3-3: Connectors Pinout for Channel A11 (Continued) Channel A11 Pin # FPGA Signal SED1354 Signal Pin # FPGA Signal SED1354 Signal chA11p11 M/R# chA11p12 chA11p13 WE1# chA11p34 chA11p14 RESET# chA11p15 chA11p16 chA11p17 chA11p33...
Where 1 = closed/on and 0 = open/off 3.1.3 Memory Address (CS#, M/R#) Decode The SED1354 is a memory-mapped device for both the registers and display buffer access. The specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space requirements are: •...
Page 310
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 Power Consumption X19A-G-006-02 Issue Date: 97/12/24...
Page 311
– the higher the divide, the lower the power consumption. There are two power save modes in the SED1354: Software and Hardware SUSPEND. The power consumption of these modes is also affected by various system design variables.
Page 312
LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the SED1354 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.
Page 314
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 Interfacing to the Philips MIPS PR31500 / PR31700 Processor X19A-G-005-04 Issue Date: 98/01/17...
Page 316
Page 4 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 Interfacing to the Philips MIPS PR31500 / PR31700 Processor X19A-G-005-04 Issue Date: 98/01/17...
1.1 General Description The Philips PR31700 / PR31500 series of processors provide a PCMCIA card interface through the use of an ITE IT8368E PCMCIA / GPIO Buffer Chip. The SED1354 interfaces to the IT8368E by “sharing” its PCMCIA bus and address space.
A[25:13]. The IT8368E can be configured to provide this latched address, however, when using the SED1354, five MFIO pins are utilized for SED1354 control signals. Therefore, an external latch must be used to provide the high order ad- dress bits.
The schematic shows that this 16M byte range is further divided in half by using A23 to control the M/R# pin, providing 16M bytes to 24M bytes for the SED1354 register space and 24M bytes to 32M bytes for the SED1354 display buffer.
Vancouver Design Center 4 Software Epson provides software source code for both the test utilities and the Windows CE 2.0 display driver. The test utilities are configurable for different panel types using an MS-DOS program called 1354CFG or by modifying the source. The Windows CE 2.0 display driver can be customized by the OEM at the source level for different panel types, resolutions and color depths.
Page 322
Page 2 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-03 Issue Date: 97/12/24...
Page 324
Page 4 EPSON Vancouver Design Center THIS PAGE LEFT BLANK SED1354 Interfacing to the NEC VR4102™ Microprocessor X19A-G-007-03 Issue Date: 97/12/24...
Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the NEC V 4102 Microprocessor (uPD30102). For further information on either device refer to the respective technical specification.
Vancouver Design Center 2 SED1354 Configuration 2.1 Hardware Description The SED1354 is configured on power-up by latching the power-on state of the DRAM data pins, MD[15:0]. Refer to the SED1354 Hardware Specification, document number X19A-A-002-xx for details. The “partial” table below only shows those configuration settings important to this specific CPU interface.
Page 327
EPSON Page 7 Vancouver Design Center Table 2-2: NEC / SED1354 Truth Table NEC Signals Cycle SED1354 Signals SHB# RD0# = low 8-bit even address Read RD1# = high RD0# = high 8-bit odd address Read RD1# - low RD0# = low...
Vancouver Design Center 3 Software Epson provides software source code for both the test utilities and the Windows CE 2.0™ display driver. The test utilities are configurable for different panel types using an MS-DOS program called 1354CFG, or by modifying the source. The Windows CE 2.0™ display driver is customized by the OEM at the source level for different panel types, resolutions and color depths.
Need help?
Do you have a question about the SED1354 and is the answer not in the manual?
Questions and answers