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Conexant Fusion 878A Manuals
Manuals and User Guides for Conexant Fusion 878A. We have
1
Conexant Fusion 878A manual available for free PDF download: Manual
Conexant Fusion 878A Manual (180 pages)
PCI Video Decoder
Brand:
Conexant
| Category:
Media Converter
| Size: 2 MB
Table of Contents
Ordering Information
2
Related Documents
2
Table of Contents
3
List of Figures
9
1 Product Overview
13
Functional Overview
13
Table 1-1. Audio/Video Capture Product Family
13
Figure 1-1. Fusion 878A Detailed Block Diagram
14
Figure 1-2. Fusion 878A Audio/Video Decoder and Scaler Block Diagram
15
Detailed Features
16
Video Capture
16
Audio Capture
16
Analog Video and Digital Camera Capture
16
Intel Intercast™ Support
16
Video DMA Channels
17
Audio DMA Channels
17
Data Transport Engine
17
PCI Bus Interface
18
Ultralock
18
Scaling and Cropping
18
Input Interface
18
GPIO Port
19
Vertical Blanking Interval Data Capture
19
I 2 C Interface
19
HDTV Support
19
Pin Descriptions
20
Figure 1-3. Fusion 878A Pinout Diagram
20
Table 1-2. Pin Descriptions Grouped by Pin Function
21
2 Functional Description
25
Ultralock TM Functionality
25
The Challenge
25
Operating Principles of Ultralock
25
Figure 2-1. Ultralock Behavior for NTSC Square Pixel Output
26
Composite Video Input Formats
27
Table 2-1. Video Input Formats Supported by the Fusion 878A
27
Table 2-2. Register Values for Square Pixel Video Input Formats
27
Y/C Separation and Chroma Demodulation
28
Figure 2-2. Y/C Separation and Chroma Demodulation for Composite Video
28
Figure 2-3. Y/C Separation Filter Responses
29
Figure 2-4. Filtering and Scaling
30
Video Scaling, Cropping, and Temporal Decimation
31
Down-Scaling
31
Field Aligned Vertical Scaling
31
Horizontal and Vertical Scaling
31
Luminance Scaling
31
Figure 2-5. Optional Horizontal Luma Low-Pass Filter Responses
32
Figure 2-6. Combined Luma Notch, 2X Oversampling and Optional
32
Figure 2-7. Combined Luma Notch, 2X Oversampling and Optional
33
Figure 2-8. Combined Luma Notch and 2X Oversampling Filter Response
33
Figure 2-9. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters
34
Peaking
34
Figure 2-10. Peaking Filters
35
Figure 2-11. Luma Peaking Filters with 2X Oversampling Filter and Luma Notch
36
Chrominance Scaling
37
Scaling Registers
37
Image Cropping
40
Table 2-3. Scaling Ratios for Popular Formats Using Frequency Values
40
Figure 2-12. Effect of the Cropping and Active Registers
41
Cropping Registers
42
Figure 2-13. Regions of the Video Signal
42
Table 2-4. Square Pixel Values
42
Temporal Decimation
43
Video Adjustments
45
The Hue Adjust Register
45
The Contrast Adjust Register
45
The Saturation Adjust Registers
45
The Brightness Register
45
Automatic Chrominance Gain Control
46
Low Color Detection and Removal
46
Coring
47
Figure 2-14. Coring Map
47
VBI Data Output Interface
48
Figure 2-15. Regions of the NTSC Video Frame
48
Figure 2-16. Regions of the PAL Video Frame (Fields 1, 2, 5, and 6)
48
Figure 2-17. VBI Timing
49
VBI Line Output Mode
49
Figure 2-18. VBI Section Block Diagram
50
Video Data Format Conversion
51
Pixel Data Path
51
Video Control Code Status Data
51
Figure 2-19. Video Data Format Converter
52
Table 2-5. Color Formats
53
Ycrcb to RGB Conversion
54
Gamma Correction Removal
54
Ycrcb Sub-Sampling
54
Byte Swapping
55
Table 2-6. Byte Swapping Map
55
Video and Control Data FIFO
56
Logical Organization
56
Figure 2-20. Data FIFO Block Diagram
56
FIFO Data Interface
57
Table 2-7. Status Bits
57
Physical Implementation
58
FIFO Input/Output Rates
58
Table 2-8. FIFO Full/Almost Full Counts
58
Table 2-9. Table of PCI Bus Access Latencies
59
DMA Controller
60
Target Memory
61
RISC Program Setup and Synchronization
61
Figure 2-21. Audio/Video RISC Block Diagram
61
RISC Instructions
62
Table 2-10. RISC Instructions
62
Complex Clipping
67
Executing Instructions
68
Figure 2-22. Example of Complex Clipping
68
FIFO Overrun Conditions
69
FIFO Data Stream Resynchronization
70
Byte Alignment
71
Table 2-11. Write 640 Pixels in RGB8 Mode
71
Multifunction Arbiter
72
430FX Compatibility Mode
72
Normal PCI Mode
72
Interfacing with Non-PCI 2.1 Compliant Core Logic
73
Audio A/D
74
Input Gain Control
74
Muxing and Anti-Aliasing Filtering
74
Table 2-12. Gain Control
74
High Speed Serial Interface Mode
76
Asynchronous Data Parallel Mode: Raw Data Capture
77
Figure 2-23. Asynchronous Data Parallel Input Multiplexer Block
77
Digital Audio Packetizer
78
Audio FIFO Memory and Status Codes
78
PCI Bus Latency Tolerance for Audio Buffer
78
Table 2-13. Digital Audio Packetizer Programming Map
78
FIFO Interface
79
Figure 2-24. FIFO Interface
79
Audio Packets and Data Capture
80
Digital Audio Input
81
Digital Audio Input Mode
81
Figure 2-25. Audio Input Timing
81
Data Packet Mode
82
Figure 2-26. Data Packet Mode Timing
82
Audio Data Formats
83
Audio Dropout Detection
83
Figure 2-27. Audio Data Path
83
Table 2-14. Audio Data Formats
83
Digital Television Support
84
3 Electrical Interfaces
85
Input Interface
85
Analog Signal Selection
85
Multiplexer Considerations
86
Figure 3-1. Typical External Circuitry
86
Flash A/D Converters
87
A/D Clamping
87
Power-Up Operation
87
Automatic Gain Controls
87
Crystal Inputs and Clock Generation
87
Table 3-1. Recommended Crystals
89
Oversampling and Input Filtering
90
Figure 3-2. Clock Options
90
Figure 3-3. Luma and Chroma 2X Oversampling Filter
91
PCI Bus Interface
92
Figure 3-4. PCI Video Block Diagram
93
Figure 3-5. PCI Audio Block Diagram
93
General Purpose I/O Port
94
GPIO Pin Architecture
94
GPIO Modes in Fusion 878A
94
GPIO Normal Mode
94
Figure 3-6. GPIO Pin Architecture
94
Figure 3-7. GPIO Normal Mode
95
SPI Input Mode
96
Figure 3-8. GPIO SPI Input Mode
96
Table 3-2. SPI Input GPIO Signals
96
SPI Output Mode
97
Figure 3-9. GPIO SPI Output Mode
97
Table 3-3. SPI GPIO Output Signals
98
Figure 3-10. Basic Timing Relationships for SPI Output Mode
99
Figure 3-11. Video Timing in SPI Output Mode
100
GPIO SPI Mode Timing Parameters
101
Table 3-4. GPIO SPI Mode Timing Parameters
101
Digital Video Input Mode
102
Ccir656
102
Table 3-5. Pin Definition of GPIO Port When Using Digital Video-In Mode
102
Figure 3-12. CCIR 656 Interface to Digital Input Port
103
Modified SMPTE-125
103
GPIO Timing Diagram for SPI and Digital Video Input Modes
104
Figure 3-13. GPIO Timing Diagram
104
I 2 C Interface
105
Figure 3-14. the Relationship between SCL and SDA
105
Figure 3-15. I 2 C Typical Protocol Diagram
106
I2C Serial EEPROM Interface
107
EEPROM Address Mapping
107
Table 3-6. External EEPROM Memory Map
107
Subsystem Vendor ID
108
EEPROM Upload at PCI Reset
108
Register Load from BIOS
108
Table 3-7. EEPROM Upload Sequence
108
Programming and Write-Protect
109
Vital Product Data
109
Vital Product Data EEPROM Addressing
109
Table 3-8. VPD Read Sequence
110
Table 3-9. VPD Write Sequence
110
Vital Product Data Read Sequence
110
Vital Product Data Write Sequence
110
Power Management Interface
112
Pme
112
D3 Power States
112
JTAG Interface
113
Need for Functional Verification
113
JTAG Approach to Testability
113
Optional Device ID Register
114
Verification with the TAP Controller
114
Figure 3-16. Instruction Register
114
Table 3-10. Device Identification Register
114
4 PC Board Layout Considerations
115
Layout Considerations
115
Capacitors
115
Table 4-1. Capacitor Location
115
Components
116
Split Planes and Voltage Regulators
117
Latchup Avoidance
118
Figure 4-1. Optional Regulatory Circuitry
118
5 Control Register Definitions-Function 0
119
PCI Configuration Space
119
Figure 5-1. Function 0 PCI Configuration Space Header
120
PCI Configuration Registers (Header)
121
0X00-Vendor and Device ID Register
121
0X04-Command and Status Register
121
0X08-Revision ID and Class Code Register
122
0X0C-Header Type, Latency Timer Register
122
0X10-Base Address 0 Register
122
0X2C-Subsystem ID and Subsystem Vendor ID Register
122
0X3C-Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
123
0X34-Capabilities Pointer Register
123
0X40-Device Control Register
123
0X44-VPD Capability Register
124
0X48-VPD Data Register
124
0X4C-Power Management Capability Register
124
0X50-Power Management Support Registers
125
Local Registers (Memory Mapped)
126
0X000-Device Status Register (DSTATUS)
127
0X004-Input Format Register (IFORM)
128
0X008-Temporal Decimation Register (TDEC)
128
MSB Cropping Register)
129
Vertical Delay Register, Lower Byte
129
Vertical Active Register, Lower Byte
129
X08C—Odd Field (O_CROP)
129
Horizontal Delay Register, Lower Byte
130
Horizontal Active Register, Lower Byte
130
Horizontal Scaling Register, Upper Byte
130
Horizontal Scaling Register, Lower Byte
130
0X028-Brightness Control Register (BRIGHT)
131
Table 5-1. BRIGHT Parameters
131
Miscellaneous Control Register
132
0X02C-Even Field (E_CONTROL)
132
0X0Ac-Odd Field (O_CONTROL)
132
0X030-Luma Gain Register, Lower Byte (CONTRAST_LO)
133
Table 5-2. CONTRAST Parameters
133
0X034-Chroma (U) Gain Register, Lower Byte (SAT_U_LO)
134
0X038-Chroma (V) Gain Register, Lower Byte (SAT_V_LO)
135
0X03C-Hue Control Register (HUE)
136
Table 5-5. HUE Parameters
136
SC Loop Control Register
137
0X040-Even Field (E_SCLOOP)
137
0X0C0-Odd Field (O_SCLOOP)
137
0X044-White Crush up Register (WC_UP)
138
0X048-Output Format Register (OFORM)
138
Vertical Scaling Register, Upper Byte
139
0X04C-Even Field (E_VSCALE_HI)
139
0X0Cc-Odd Field (O_VSCALE_HI)
139
Vertical Scaling Register, Lower Byte
139
0X050-Even Field (E_VSCALE_LO)
139
0X0D0-Odd Field (O_VSCALE_LO)
139
0X054-Reserved
139
0X5B-Audio Reset Register (ARESET)
140
0X060-AGC Delay Register (ADELAY)
140
0X064-Burst Delay Register (BDELAY)
140
0X068-ADC Interface Register (ADC)
141
Video Timing Control Register
142
0X07C-Software Reset Register (SRESET)
142
0X078-White Crush down Register
143
0X080-Timing Generator Load Byte (TGLB)
143
0X084-Timing Generator Control (TGCTRL) Register
144
X0B0—Total Line Count Register (VTOTAL_LO)
145
0X0D4-Color Format Register (COLOR_FMT)
146
X0D8—Color Control Register (COLOR_CTL)
147
0X0E8-Field Capture Counter Register (FCAP)
148
X0E0—Vbi Packet Size Register (VBI_PACK_SIZE)
148
0X0F8-Integer Register (PLL-XCI)
149
0X0Fc-Digital Video Signal Interface Format (DVSIF) Register
149
0X100-Interrupt Status Register (INT_STAT)
150
0X104-Interrupt Mask Register (INT_MASK)
151
0X10C-GPIO and DMA Control Register (GPIO_DMA_CTL)
152
0X110-I2C Data/Control Register
153
0X114-RISC Program Start Address Register (RISC_STRT_ADD)
154
0X118-GPIO Output Enable Control Register (GPIO_OUT_EN)
154
0X120-RISC Program Counter Register (RISC_COUNT)
154
0X200-0X2Ff-GPIO Data I/O Register (GPIO_DATA)
154
6 Control Register Definitions-Function 1
155
PCI Configuration Space
155
Figure 6-1. Function 1 PCI Configuration Space Header
156
PCI Configuration Registers (Header)
157
0X00-Vendor and Device ID Register
157
0X04-Command and Status Register
157
0X08-Revision ID and Class Code Register
158
0X0C-Header Type Register
158
0X0C-Latency Timer Register
158
0X10-Base Address 0 Register
158
0X2C-Subsystem ID and Subsystem Vendor ID Register
159
0X34-Capabilities Pointer Register
159
0X3C-Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
159
0X40-Device Control Register
160
0X44-VPD Capability Register
160
0X48-VPD Data Register
161
0X4C-Power Management Capability Register
161
0X50-Power Management Support Register
162
Local Registers (Memory Mapped)
163
0X100-Interrupt Status Register (INT_STAT)
164
0X104-Interrupt Mask Register (INT_MASK)
165
0X10C-Audio Control Register (GPIO_DMA_CTL)
165
0X110-Audio Packet Lengths Register
167
7 Parametric Information
169
DC Electrical Parameters
169
Table 7-1. Recommended Operating Conditions
169
Table 7-2. Absolute Maximum Ratings
170
Table 7-3. DC Characteristics
170
AC Electrical Parameters
172
Figure 7-1. Clock Timing Diagram
172
Table 7-4. Clock Timing Parameters
172
Table 7-5. Power Supply Current Parameters
172
Table 7-6. JTAG Timing Parameters
172
Figure 7-2. JTAG Timing Diagram
173
Table 7-7. Decoder Performance Parameters
173
Package Mechanical Drawing
174
Figure 7-3. 128-Pin PQFP Package Mechanical Drawing
174
Appendix A. Acronym List
175
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